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Commit 1f888acd authored by Andi Kleen's avatar Andi Kleen Committed by Arnaldo Carvalho de Melo
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perf vendor events: Add WestmereEP-DP V2 event file 

Add a Intel event file for perf.
Signed-off-by: default avatarAndi Kleen <ak@linux.intel.com>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Sukadev Bhattiprolu <sukadev@linux.vnet.ibm.com>
Link: http://lkml.kernel.org/n/tip-vuq872d1qdfettbbxkw74yv1@git.kernel.org
[ Lowercased the directory and file names ]
Signed-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 6e82bdae
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tools/perf/pmu-events/arch/x86/mapfile.csv
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......@@ -29,3 +29,4 @@ GenuineIntel-6-37,v13,silvermont,core
GenuineIntel-6-4D,v13,silvermont,core
GenuineIntel-6-4C,v13,silvermont,core
GenuineIntel-6-2A,v15,sandybridge,core
GenuineIntel-6-2C,v2,westmereep-dp,core
tools/perf/pmu-events/arch/x86/westmereep-dp/cache.json 0 → 100644
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tools/perf/pmu-events/arch/x86/westmereep-dp/floating-point.json 0 → 100644
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[
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_ASSIST.ALL",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_ASSIST.INPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating poiint assists for invalid input value (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xF7",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_ASSIST.OUTPUT",
"SampleAfterValue": "20000",
"BriefDescription": "X87 Floating point assists for invalid output value (Precise Event)"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_COMP_OPS_EXE.MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "MMX Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "FP_COMP_OPS_EXE.SSE_DOUBLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP double precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "FP_COMP_OPS_EXE.SSE_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE and SSE2 FP Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_PACKED",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP packed Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "FP_COMP_OPS_EXE.SSE_FP_SCALAR",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE FP scalar Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "FP_COMP_OPS_EXE.SSE_SINGLE_PRECISION",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE* FP single precision Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "FP_COMP_OPS_EXE.SSE2_INTEGER",
"SampleAfterValue": "2000000",
"BriefDescription": "SSE2 integer Uops"
},
{
"EventCode": "0x10",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_COMP_OPS_EXE.X87",
"SampleAfterValue": "2000000",
"BriefDescription": "Computational floating-point operations executed"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "FP_MMX_TRANS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All Floating Point to and from MMX transitions"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "FP_MMX_TRANS.TO_FP",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from MMX to Floating Point instructions"
},
{
"EventCode": "0xCC",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "FP_MMX_TRANS.TO_MMX",
"SampleAfterValue": "2000000",
"BriefDescription": "Transitions from Floating Point to MMX instructions"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SIMD_INT_128.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer pack operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "SIMD_INT_128.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer arithmetic operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "SIMD_INT_128.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer logical operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_INT_128.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer multiply operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_INT_128.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shift operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "SIMD_INT_128.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer shuffle/move operations"
},
{
"EventCode": "0x12",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "SIMD_INT_128.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "128 bit SIMD integer unpack operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SIMD_INT_64.PACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit pack operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "SIMD_INT_64.PACKED_ARITH",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit arithmetic operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "SIMD_INT_64.PACKED_LOGICAL",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit logical operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SIMD_INT_64.PACKED_MPY",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit packed multiply operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SIMD_INT_64.PACKED_SHIFT",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shift operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x40",
"EventName": "SIMD_INT_64.SHUFFLE_MOVE",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit shuffle/move operations"
},
{
"EventCode": "0xFD",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "SIMD_INT_64.UNPACK",
"SampleAfterValue": "200000",
"BriefDescription": "SIMD integer 64 bit unpack operations"
}
]
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tools/perf/pmu-events/arch/x86/westmereep-dp/frontend.json 0 → 100644
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[
{
"EventCode": "0xD0",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MACRO_INSTS.DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Instructions decoded"
},
{
"EventCode": "0xA6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MACRO_INSTS.FUSIONS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Macro-fused instructions decoded"
},
{
"EventCode": "0x19",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "TWO_UOP_INSTS_DECODED",
"SampleAfterValue": "2000000",
"BriefDescription": "Two Uop instructions decoded"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-dp/memory.json 0 → 100644
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tools/perf/pmu-events/arch/x86/westmereep-dp/other.json 0 → 100644
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[
{
"EventCode": "0xE8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_CLEARS.EARLY",
"SampleAfterValue": "2000000",
"BriefDescription": "Early Branch Prediciton Unit clears"
},
{
"EventCode": "0xE8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "BPU_CLEARS.LATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Late Branch Prediction Unit clears"
},
{
"EventCode": "0xE5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "BPU_MISSED_CALL_RET",
"SampleAfterValue": "2000000",
"BriefDescription": "Branch prediction unit missed call or return"
},
{
"EventCode": "0xD5",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ES_REG_RENAMES",
"SampleAfterValue": "2000000",
"BriefDescription": "ES segment renames"
},
{
"EventCode": "0x6C",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "IO_TRANSACTIONS",
"SampleAfterValue": "2000000",
"BriefDescription": "I/O transactions"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "L1I.CYCLES_STALLED",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch stall cycles"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "L1I.HITS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch hits"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "L1I.MISSES",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I instruction fetch misses"
},
{
"EventCode": "0x80",
"Counter": "0,1,2,3",
"UMask": "0x3",
"EventName": "L1I.READS",
"SampleAfterValue": "2000000",
"BriefDescription": "L1I Instruction fetches"
},
{
"EventCode": "0x82",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LARGE_ITLB.HIT",
"SampleAfterValue": "200000",
"BriefDescription": "Large ITLB hit"
},
{
"EventCode": "0x3",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LOAD_BLOCK.OVERLAP_STORE",
"SampleAfterValue": "200000",
"BriefDescription": "Loads that partially overlap an earlier store"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "LOAD_DISPATCH.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All loads dispatched"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "LOAD_DISPATCH.MOB",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from the MOB"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "LOAD_DISPATCH.RS",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched that bypass the MOB"
},
{
"EventCode": "0x13",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "LOAD_DISPATCH.RS_DELAYED",
"SampleAfterValue": "2000000",
"BriefDescription": "Loads dispatched from stage 305"
},
{
"EventCode": "0x7",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "PARTIAL_ADDRESS_ALIAS",
"SampleAfterValue": "200000",
"BriefDescription": "False dependencies due to partial address aliasing"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0xf",
"EventName": "RAT_STALLS.ANY",
"SampleAfterValue": "2000000",
"BriefDescription": "All RAT stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "RAT_STALLS.FLAGS",
"SampleAfterValue": "2000000",
"BriefDescription": "Flag stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "RAT_STALLS.REGISTERS",
"SampleAfterValue": "2000000",
"BriefDescription": "Partial register stall cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "RAT_STALLS.ROB_READ_PORT",
"SampleAfterValue": "2000000",
"BriefDescription": "ROB read port stalls cycles"
},
{
"EventCode": "0xD2",
"Counter": "0,1,2,3",
"UMask": "0x8",
"EventName": "RAT_STALLS.SCOREBOARD",
"SampleAfterValue": "2000000",
"BriefDescription": "Scoreboard stall cycles"
},
{
"EventCode": "0x4",
"Counter": "0,1,2,3",
"UMask": "0x7",
"EventName": "SB_DRAIN.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "All Store buffer stall cycles"
},
{
"EventCode": "0xD4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SEG_RENAME_STALLS",
"SampleAfterValue": "2000000",
"BriefDescription": "Segment rename stall cycles"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SNOOP_RESPONSE.HIT",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HIT to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SNOOP_RESPONSE.HITE",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITE to snoop"
},
{
"EventCode": "0xB8",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOP_RESPONSE.HITM",
"SampleAfterValue": "100000",
"BriefDescription": "Thread responded HITM to snoop"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS.CODE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop code requests"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS.DATA",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop data requests"
},
{
"EventCode": "0xB4",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS.INVALIDATE",
"SampleAfterValue": "100000",
"BriefDescription": "Snoop invalidate requests"
},
{
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop code requests"
},
{
"EventCode": "0xB3",
"UMask": "0x4",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.CODE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop code requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop data requests"
},
{
"EventCode": "0xB3",
"UMask": "0x1",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.DATA_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop data requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE",
"SampleAfterValue": "2000000",
"BriefDescription": "Outstanding snoop invalidate requests"
},
{
"EventCode": "0xB3",
"UMask": "0x2",
"EventName": "SNOOPQ_REQUESTS_OUTSTANDING.INVALIDATE_NOT_EMPTY",
"SampleAfterValue": "2000000",
"BriefDescription": "Cycles snoop invalidate requests queued",
"CounterMask": "1"
},
{
"EventCode": "0xF6",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "SQ_FULL_STALL_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Super Queue full stall cycles"
}
]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/westmereep-dp/pipeline.json 0 → 100644
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tools/perf/pmu-events/arch/x86/westmereep-dp/virtual-memory.json 0 → 100644
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[
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_LOAD_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load misses"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "DTLB_LOAD_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss large page walks"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "DTLB_LOAD_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss caused by low part of address"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB second level hit"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walks complete"
},
{
"EventCode": "0x8",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_LOAD_MISSES.WALK_CYCLES",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB load miss page walk cycles"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "DTLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "DTLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss large page walks"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "DTLB_MISSES.PDE_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB misses casued by low part of address"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "DTLB_MISSES.STLB_HIT",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB first level misses but second level hit"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "DTLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "DTLB miss page walks"
},
{
"EventCode": "0x49",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "DTLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "DTLB miss page walk cycles"
},
{
"EventCode": "0x4F",
"Counter": "0,1,2,3",
"UMask": "0x10",
"EventName": "EPT.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "Extended Page Table walk cycles"
},
{
"EventCode": "0xAE",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_FLUSH",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB flushes"
},
{
"PEBS": "1",
"EventCode": "0xC8",
"Counter": "0,1,2,3",
"UMask": "0x20",
"EventName": "ITLB_MISS_RETIRED",
"SampleAfterValue": "200000",
"BriefDescription": "Retired instructions that missed the ITLB (Precise Event)"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "ITLB_MISSES.ANY",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "ITLB_MISSES.LARGE_WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss large page walks"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x2",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "200000",
"BriefDescription": "ITLB miss page walks"
},
{
"EventCode": "0x85",
"Counter": "0,1,2,3",
"UMask": "0x4",
"EventName": "ITLB_MISSES.WALK_CYCLES",
"SampleAfterValue": "2000000",
"BriefDescription": "ITLB miss page walk cycles"
},
{
"PEBS": "1",
"EventCode": "0xCB",
"Counter": "0,1,2,3",
"UMask": "0x80",
"EventName": "MEM_LOAD_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired loads that miss the DTLB (Precise Event)"
},
{
"PEBS": "1",
"EventCode": "0xC",
"Counter": "0,1,2,3",
"UMask": "0x1",
"EventName": "MEM_STORE_RETIRED.DTLB_MISS",
"SampleAfterValue": "200000",
"BriefDescription": "Retired stores that miss the DTLB (Precise Event)"
}
]
\ No newline at end of file
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