Commit 1ff3beca authored by Boris Brezillon's avatar Boris Brezillon Committed by Nicolas Ferre

ARM: at91/dt: add GPBR nodes

Add GPBR (General Purpose Block Backup Registers) nodes.
Signed-off-by: default avatarBoris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: default avatarNicolas Ferre <nicolas.ferre@atmel.com>
parent 9b5a0675
......@@ -974,6 +974,12 @@ watchdog@fffffd40 {
atmel,idle-halt;
status = "disabled";
};
gpbr: syscon@fffffd50 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd50 0x10>;
status = "disabled";
};
};
nand0: nand@40000000 {
......
......@@ -842,6 +842,12 @@ watchdog@fffffd40 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
gpbr: syscon@fffffd50 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd50 0x10>;
status = "disabled";
};
};
};
......
......@@ -939,6 +939,12 @@ rtc@fffffd50 {
clocks = <&slow_xtal>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x50>;
status = "disabled";
};
};
fb0: fb@0x00700000 {
......
......@@ -1206,6 +1206,12 @@ rtc@fffffdb0 {
interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x10>;
status = "disabled";
};
};
fb0: fb@0x00500000 {
......
......@@ -1074,6 +1074,12 @@ rtc@fffffd20 {
clocks = <&clk32k>;
status = "disabled";
};
gpbr: syscon@fffffd60 {
compatible = "atmel,at91sam9260-gpbr", "syscon";
reg = <0xfffffd60 0x10>;
status = "disabled";
};
};
};
......
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