Commit 20612d24 authored by Lukas Bulwahn's avatar Lukas Bulwahn Committed by Greg Kroah-Hartman

fpga: dfl-pci: rectify ReST formatting

Commit fa41d105 ("fpga: dfl-pci: locate DFLs by PCIe vendor specific
capability") provides documentation to the FPGA Device Feature List (DFL)
Framework Overview, but introduced new documentation warnings:

  ./Documentation/fpga/dfl.rst:
    505: WARNING: Title underline too short.
    523: WARNING: Unexpected indentation.
    523: WARNING: Blank line required after table.
    524: WARNING: Block quote ends without a blank line; unexpected unindent.

Rectify ReST formatting in ./Documentation/fpga/dfl.rst.
Tested-by: default avatarTom Rix <trix@redhat.com>
Acked-by: default avatarMoritz Fischer <mdf@kernel.org>
Acked-by: default avatarMatthew Gerlach <matthew.gerlach@linux.intel.com>
Signed-off-by: default avatarLukas Bulwahn <lukas.bulwahn@gmail.com>
Link: https://lore.kernel.org/r/20210111112113.27242-1-lukas.bulwahn@gmail.comSigned-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent 4540b9fb
......@@ -502,7 +502,7 @@ FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c)
could be a reference.
Location of DFLs on a PCI Device
===========================
================================
The original method for finding a DFL on a PCI device assumed the start of the
first DFL to offset 0 of bar 0. If the first node of the DFL is an FME,
then further DFLs in the port(s) are specified in FME header registers.
......@@ -514,6 +514,7 @@ data begins with a 4 byte vendor specific register for the number of DFLs follow
Offset/BIR vendor specific registers for each DFL. Bits 2:0 of Offset/BIR register
indicates the BAR, and bits 31:3 form the 8 byte aligned offset where bits 2:0 are
zero.
::
+----------------------------+
|31 Number of DFLS 0|
......
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