Commit 21e20e22 authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux

Pull clock fixes from Mike Turquette:
 "Late fixes for clock drivers.  All of these fixes are for user-visible
  regressions, typically boot failures or other unsafe system
  configuration that causes badness"

* tag 'clk-fixes-for-linus' of git://git.linaro.org/people/mike.turquette/linux:
  clk: clk-divider: fix divisor > 255 bug
  clk: exynos: File scope reg_save array should depend on PM_SLEEP
  clk: samsung: exynos5250: Add CLK_IGNORE_UNUSED flag for the sysreg clock
  ARM: dts: exynos5250: Fix MDMA0 clock number
  clk: samsung: exynos5250: Add MDMA0 clocks
  clk: samsung: exynos5250: Fix ACP gate register offset
  clk: exynos5250: fix sysmmu_mfc{l,r} gate clocks
  clk: samsung: exynos4: Correct SRC_MFC register
parents 2aa63ce0 778037e1
...@@ -159,6 +159,8 @@ clock which they consume. ...@@ -159,6 +159,8 @@ clock which they consume.
mixer 343 mixer 343
hdmi 344 hdmi 344
g2d 345 g2d 345
mdma0 346
smmu_mdma0 347
[Clock Muxes] [Clock Muxes]
......
...@@ -559,7 +559,7 @@ mdma0: mdma@10800000 { ...@@ -559,7 +559,7 @@ mdma0: mdma@10800000 {
compatible = "arm,pl330", "arm,primecell"; compatible = "arm,pl330", "arm,primecell";
reg = <0x10800000 0x1000>; reg = <0x10800000 0x1000>;
interrupts = <0 33 0>; interrupts = <0 33 0>;
clocks = <&clock 271>; clocks = <&clock 346>;
clock-names = "apb_pclk"; clock-names = "apb_pclk";
#dma-cells = <1>; #dma-cells = <1>;
#dma-channels = <8>; #dma-channels = <8>;
......
...@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table, ...@@ -87,7 +87,7 @@ static unsigned int _get_table_val(const struct clk_div_table *table,
return 0; return 0;
} }
static unsigned int _get_val(struct clk_divider *divider, u8 div) static unsigned int _get_val(struct clk_divider *divider, unsigned int div)
{ {
if (divider->flags & CLK_DIVIDER_ONE_BASED) if (divider->flags & CLK_DIVIDER_ONE_BASED)
return div; return div;
......
...@@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data; ...@@ -26,17 +26,17 @@ static struct clk_onecell_data clk_data;
#define ASS_CLK_DIV 0x4 #define ASS_CLK_DIV 0x4
#define ASS_CLK_GATE 0x8 #define ASS_CLK_GATE 0x8
/* list of all parent clock list */
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
#ifdef CONFIG_PM_SLEEP
static unsigned long reg_save[][2] = { static unsigned long reg_save[][2] = {
{ASS_CLK_SRC, 0}, {ASS_CLK_SRC, 0},
{ASS_CLK_DIV, 0}, {ASS_CLK_DIV, 0},
{ASS_CLK_GATE, 0}, {ASS_CLK_GATE, 0},
}; };
/* list of all parent clock list */
static const char *mout_audss_p[] = { "fin_pll", "fout_epll" };
static const char *mout_i2s_p[] = { "mout_audss", "cdclk0", "sclk_audio0" };
#ifdef CONFIG_PM_SLEEP
static int exynos_audss_clk_suspend(void) static int exynos_audss_clk_suspend(void)
{ {
int i; int i;
......
...@@ -39,7 +39,7 @@ ...@@ -39,7 +39,7 @@
#define SRC_TOP1 0xc214 #define SRC_TOP1 0xc214
#define SRC_CAM 0xc220 #define SRC_CAM 0xc220
#define SRC_TV 0xc224 #define SRC_TV 0xc224
#define SRC_MFC 0xcc28 #define SRC_MFC 0xc228
#define SRC_G3D 0xc22c #define SRC_G3D 0xc22c
#define E4210_SRC_IMAGE 0xc230 #define E4210_SRC_IMAGE 0xc230
#define SRC_LCD0 0xc234 #define SRC_LCD0 0xc234
......
...@@ -25,6 +25,7 @@ ...@@ -25,6 +25,7 @@
#define MPLL_LOCK 0x4000 #define MPLL_LOCK 0x4000
#define MPLL_CON0 0x4100 #define MPLL_CON0 0x4100
#define SRC_CORE1 0x4204 #define SRC_CORE1 0x4204
#define GATE_IP_ACP 0x8800
#define CPLL_LOCK 0x10020 #define CPLL_LOCK 0x10020
#define EPLL_LOCK 0x10030 #define EPLL_LOCK 0x10030
#define VPLL_LOCK 0x10040 #define VPLL_LOCK 0x10040
...@@ -75,7 +76,6 @@ ...@@ -75,7 +76,6 @@
#define SRC_CDREX 0x20200 #define SRC_CDREX 0x20200
#define PLL_DIV2_SEL 0x20a24 #define PLL_DIV2_SEL 0x20a24
#define GATE_IP_DISP1 0x10928 #define GATE_IP_DISP1 0x10928
#define GATE_IP_ACP 0x10000
/* list of PLLs to be registered */ /* list of PLLs to be registered */
enum exynos5250_plls { enum exynos5250_plls {
...@@ -120,7 +120,8 @@ enum exynos5250_clks { ...@@ -120,7 +120,8 @@ enum exynos5250_clks {
spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2, spi2, i2s1, i2s2, pcm1, pcm2, pwm, spdif, ac97, hsi2c0, hsi2c1, hsi2c2,
hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1, hsi2c3, chipid, sysreg, pmu, cmu_top, cmu_core, cmu_mem, tzpc0, tzpc1,
tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct, tzpc2, tzpc3, tzpc4, tzpc5, tzpc6, tzpc7, tzpc8, tzpc9, hdmi_cec, mct,
wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, wdt, rtc, tmu, fimd1, mie1, dsim0, dp, mixer, hdmi, g2d, mdma0,
smmu_mdma0,
/* mux clocks */ /* mux clocks */
mout_hdmi = 1024, mout_hdmi = 1024,
...@@ -354,8 +355,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { ...@@ -354,8 +355,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0), GATE(smmu_gscl2, "smmu_gscl2", "aclk266", GATE_IP_GSCL, 9, 0, 0),
GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0), GATE(smmu_gscl3, "smmu_gscl3", "aclk266", GATE_IP_GSCL, 10, 0, 0),
GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0), GATE(mfc, "mfc", "aclk333", GATE_IP_MFC, 0, 0, 0),
GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 1, 0, 0), GATE(smmu_mfcl, "smmu_mfcl", "aclk333", GATE_IP_MFC, 2, 0, 0),
GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 2, 0, 0), GATE(smmu_mfcr, "smmu_mfcr", "aclk333", GATE_IP_MFC, 1, 0, 0),
GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0), GATE(rotator, "rotator", "aclk266", GATE_IP_GEN, 1, 0, 0),
GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0), GATE(jpeg, "jpeg", "aclk166", GATE_IP_GEN, 2, 0, 0),
GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0), GATE(mdma1, "mdma1", "aclk266", GATE_IP_GEN, 4, 0, 0),
...@@ -406,7 +407,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { ...@@ -406,7 +407,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0), GATE(hsi2c2, "hsi2c2", "aclk66", GATE_IP_PERIC, 30, 0, 0),
GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0), GATE(hsi2c3, "hsi2c3", "aclk66", GATE_IP_PERIC, 31, 0, 0),
GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0), GATE(chipid, "chipid", "aclk66", GATE_IP_PERIS, 0, 0, 0),
GATE(sysreg, "sysreg", "aclk66", GATE_IP_PERIS, 1, 0, 0), GATE(sysreg, "sysreg", "aclk66",
GATE_IP_PERIS, 1, CLK_IGNORE_UNUSED, 0),
GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0), GATE(pmu, "pmu", "aclk66", GATE_IP_PERIS, 2, CLK_IGNORE_UNUSED, 0),
GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0), GATE(tzpc0, "tzpc0", "aclk66", GATE_IP_PERIS, 6, 0, 0),
GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0), GATE(tzpc1, "tzpc1", "aclk66", GATE_IP_PERIS, 7, 0, 0),
...@@ -492,6 +494,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = { ...@@ -492,6 +494,8 @@ static struct samsung_gate_clock exynos5250_gate_clks[] __initdata = {
GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0), GATE(mixer, "mixer", "mout_aclk200_disp1", GATE_IP_DISP1, 5, 0, 0),
GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0), GATE(hdmi, "hdmi", "mout_aclk200_disp1", GATE_IP_DISP1, 6, 0, 0),
GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0), GATE(g2d, "g2d", "aclk200", GATE_IP_ACP, 3, 0, 0),
GATE(mdma0, "mdma0", "aclk266", GATE_IP_ACP, 1, 0, 0),
GATE(smmu_mdma0, "smmu_mdma0", "aclk266", GATE_IP_ACP, 5, 0, 0),
}; };
static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = { static struct samsung_pll_rate_table vpll_24mhz_tbl[] __initdata = {
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment