Commit 227db574 authored by Robert Richter's avatar Robert Richter Committed by Dan Williams

cxl: Rename member @dport of struct cxl_dport to @dport_dev

Reading code like dport->dport does not immediately suggest that this
points to the corresponding device structure of the dport. Rename
struct member @dport to @dport_dev.

While at it, also rename @new argument of add_dport() to @dport. This
better describes the variable as a dport (e.g. new->dport becomes to
dport->dport_dev).
Co-developed-by: default avatarTerry Bowman <terry.bowman@amd.com>
Signed-off-by: default avatarTerry Bowman <terry.bowman@amd.com>
Signed-off-by: default avatarRobert Richter <rrichter@amd.com>
Reviewed-by: default avatarJonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/20230622205523.85375-5-terry.bowman@amd.comSigned-off-by: default avatarDan Williams <dan.j.williams@intel.com>
parent 06193378
...@@ -605,7 +605,7 @@ static int devm_cxl_link_parent_dport(struct device *host, ...@@ -605,7 +605,7 @@ static int devm_cxl_link_parent_dport(struct device *host,
if (!parent_dport) if (!parent_dport)
return 0; return 0;
rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport->kobj, rc = sysfs_create_link(&port->dev.kobj, &parent_dport->dport_dev->kobj,
"parent_dport"); "parent_dport");
if (rc) if (rc)
return rc; return rc;
...@@ -658,7 +658,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport, ...@@ -658,7 +658,7 @@ static struct cxl_port *cxl_port_alloc(struct device *uport,
if (iter->host_bridge) if (iter->host_bridge)
port->host_bridge = iter->host_bridge; port->host_bridge = iter->host_bridge;
else if (parent_dport->rch) else if (parent_dport->rch)
port->host_bridge = parent_dport->dport; port->host_bridge = parent_dport->dport_dev;
else else
port->host_bridge = iter->uport; port->host_bridge = iter->uport;
dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge)); dev_dbg(uport, "host-bridge: %s\n", dev_name(port->host_bridge));
...@@ -847,22 +847,22 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id) ...@@ -847,22 +847,22 @@ static struct cxl_dport *find_dport(struct cxl_port *port, int id)
return NULL; return NULL;
} }
static int add_dport(struct cxl_port *port, struct cxl_dport *new) static int add_dport(struct cxl_port *port, struct cxl_dport *dport)
{ {
struct cxl_dport *dup; struct cxl_dport *dup;
int rc; int rc;
device_lock_assert(&port->dev); device_lock_assert(&port->dev);
dup = find_dport(port, new->port_id); dup = find_dport(port, dport->port_id);
if (dup) { if (dup) {
dev_err(&port->dev, dev_err(&port->dev,
"unable to add dport%d-%s non-unique port id (%s)\n", "unable to add dport%d-%s non-unique port id (%s)\n",
new->port_id, dev_name(new->dport), dport->port_id, dev_name(dport->dport_dev),
dev_name(dup->dport)); dev_name(dup->dport_dev));
return -EBUSY; return -EBUSY;
} }
rc = xa_insert(&port->dports, (unsigned long)new->dport, new, rc = xa_insert(&port->dports, (unsigned long)dport->dport_dev, dport,
GFP_KERNEL); GFP_KERNEL);
if (rc) if (rc)
return rc; return rc;
...@@ -895,8 +895,8 @@ static void cxl_dport_remove(void *data) ...@@ -895,8 +895,8 @@ static void cxl_dport_remove(void *data)
struct cxl_dport *dport = data; struct cxl_dport *dport = data;
struct cxl_port *port = dport->port; struct cxl_port *port = dport->port;
xa_erase(&port->dports, (unsigned long) dport->dport); xa_erase(&port->dports, (unsigned long) dport->dport_dev);
put_device(dport->dport); put_device(dport->dport_dev);
} }
static void cxl_dport_unlink(void *data) static void cxl_dport_unlink(void *data)
...@@ -954,7 +954,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev, ...@@ -954,7 +954,7 @@ __devm_cxl_add_dport(struct cxl_port *port, struct device *dport_dev,
dev_dbg(dport_dev, "Component Registers found for dport: %pa\n", dev_dbg(dport_dev, "Component Registers found for dport: %pa\n",
&component_reg_phys); &component_reg_phys);
dport->dport = dport_dev; dport->dport_dev = dport_dev;
dport->port_id = port_id; dport->port_id = port_id;
dport->component_reg_phys = component_reg_phys; dport->component_reg_phys = component_reg_phys;
dport->port = port; dport->port = port;
......
...@@ -1162,7 +1162,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, ...@@ -1162,7 +1162,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n", dev_dbg(&cxlr->dev, "%s:%s: %s expected %s at %d\n",
dev_name(port->uport), dev_name(&port->dev), dev_name(port->uport), dev_name(&port->dev),
dev_name(&cxlsd->cxld.dev), dev_name(&cxlsd->cxld.dev),
dev_name(ep->dport->dport), dev_name(ep->dport->dport_dev),
cxl_rr->nr_targets_set); cxl_rr->nr_targets_set);
return -ENXIO; return -ENXIO;
} }
...@@ -1173,7 +1173,7 @@ static int cxl_port_setup_targets(struct cxl_port *port, ...@@ -1173,7 +1173,7 @@ static int cxl_port_setup_targets(struct cxl_port *port,
cxl_rr->nr_targets_set += inc; cxl_rr->nr_targets_set += inc;
dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n", dev_dbg(&cxlr->dev, "%s:%s target[%d] = %s for %s:%s @ %d\n",
dev_name(port->uport), dev_name(&port->dev), dev_name(port->uport), dev_name(&port->dev),
cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport), cxl_rr->nr_targets_set - 1, dev_name(ep->dport->dport_dev),
dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos); dev_name(&cxlmd->dev), dev_name(&cxled->cxld.dev), pos);
return 0; return 0;
......
...@@ -589,7 +589,7 @@ struct cxl_rcrb_info { ...@@ -589,7 +589,7 @@ struct cxl_rcrb_info {
/** /**
* struct cxl_dport - CXL downstream port * struct cxl_dport - CXL downstream port
* @dport: PCI bridge or firmware device representing the downstream link * @dport_dev: PCI bridge or firmware device representing the downstream link
* @port_id: unique hardware identifier for dport in decoder target list * @port_id: unique hardware identifier for dport in decoder target list
* @component_reg_phys: downstream port component registers * @component_reg_phys: downstream port component registers
* @rcrb: Data about the Root Complex Register Block layout * @rcrb: Data about the Root Complex Register Block layout
...@@ -597,7 +597,7 @@ struct cxl_rcrb_info { ...@@ -597,7 +597,7 @@ struct cxl_rcrb_info {
* @port: reference to cxl_port that contains this downstream port * @port: reference to cxl_port that contains this downstream port
*/ */
struct cxl_dport { struct cxl_dport {
struct device *dport; struct device *dport_dev;
int port_id; int port_id;
resource_size_t component_reg_phys; resource_size_t component_reg_phys;
struct cxl_rcrb_info rcrb; struct cxl_rcrb_info rcrb;
......
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