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Commit 22c45f0b authored by Greg Kroah-Hartman's avatar Greg Kroah-Hartman
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staging: csr: remove sdioemb/ 

Nothing in the subdirectory is being used, so remove it, and the
sdio_emb.c file which also isn't being built.

Cc: Mikko Virkkilä <mikko.virkkila@bluegiga.com>
Cc: Lauri Hintsala <Lauri.Hintsala@bluegiga.com>
Cc: Riku Mettälä <riku.mettala@bluegiga.com>
Cc: Veli-Pekka Peltola <veli-pekka.peltola@bluegiga.com>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent db03f1d2
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drivers/staging/csr/sdio_emb.c deleted 100644 → 0
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drivers/staging/csr/sdioemb/cspi.h deleted 100644 → 0
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/*
* CSPI definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_CSPI_H
#define SDIOEMB_CSPI_H
/**
* @addtogroup sdriver
*@{*/
#define CSPI_FUNC(f) (f)
#define CSPI_READ 0x10
#define CSPI_WRITE 0x20
#define CSPI_BURST 0x40
#define CSPI_TYPE_MASK 0x70
/**
* CSPI_MODE function 0 register.
*
* Various CSPI mode settings.
*
* @see CSPI specification (CS-110124-SP)
*/
#define CSPI_MODE 0xf7
# define CSPI_MODE_PADDED_WRITE_HDRS (1 << 7)
# define CSPI_MODE_PADDED_READ_HDRS (1 << 6)
/**
* BigEndianRegisters bit of \ref CSPI_MODE -- enable big-endian CSPI
* register reads and writes.
*
* @warning This bit should never be set as it's not possible to use
* this mode without knowledge of which registers are 8 bit and which
* are 16 bit.
*/
# define CSPI_MODE_BE_REG (1 << 5)
# define CSPI_MODE_BE_BURST (1 << 4)
# define CSPI_MODE_INT_ACTIVE_HIGH (1 << 3)
# define CSPI_MODE_INT_ON_ERR (1 << 2)
# define CSPI_MODE_LEN_FIELD_PRESENT (1 << 1)
# define CSPI_MODE_DRV_MISO_ON_RISING_CLK (1 << 0)
#define CSPI_STATUS 0xf8
#define CSPI_PADDING 0xf9
# define CSPI_PADDING_REG(p) ((p) << 0)
# define CSPI_PADDING_BURST(p) ((p) << 4)
#define CSPI_PADDING_MAX 15
#define CSPI_PADDING_REG_DFLT 0
#define CSPI_PADDING_BURST_DFLT 2
/* cmd byte, 3 byte addr, padding, error byte, data word */
#define CSPI_REG_TRANSFER_LEN (1 + 3 + CSPI_PADDING_MAX + 1 + 2)
/*@}*/
#endif /* #ifndef SDIOEMB_CSPI_H */
drivers/staging/csr/sdioemb/csr_result.h deleted 100644 → 0
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/*
* Synergy compatible API -- common result codes.
*
* Copyright (C) 2010 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef CSR_RESULT_H__
#define CSR_RESULT_H__
typedef CsrUint16 CsrResult;
#define CSR_RESULT_SUCCESS ((CsrResult) 0x0000)
#define CSR_RESULT_FAILURE ((CsrResult) 0xffff)
#endif
drivers/staging/csr/sdioemb/csr_sdio.h deleted 100644 → 0
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drivers/staging/csr/sdioemb/csr_sdio_lib.h deleted 100644 → 0
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/*
* Synergy compatible API -- SDIO utility library.
*
* Copyright (C) 2010 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef CSR_SDIO_LIB_H__
#define CSR_SDIO_LIB_H__
#include <csr_sdio.h>
#ifdef __cplusplus
extern "C" {
#endif
CsrResult CsrSdioFunctionReenable(CsrSdioFunction *function);
typedef int CsrStatus; /* platform specific */
#define CSR_STATUS_FAILURE(status) ((status) < 0) /* platform specific */
CsrResult CsrSdioStatusToResult(CsrStatus status);
CsrStatus CsrSdioResultToStatus(CsrResult result);
#ifdef __cplusplus
} /* extern "C" */
#endif
#endif /* #ifndef CSR_SDIO_LIB_H__ */
drivers/staging/csr/sdioemb/csr_sdio_wdf.h deleted 100644 → 0
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/*
* Synergy compatible API -- helpers for Windows Driver Framework drivers.
*
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef CSR_SDIO_WDF_H__
#define CSR_SDIO_WDF_H__
#include <wdf.h>
NTSTATUS CsrSdioWdfDeviceInit(WDFDEVICE device);
void CsrSdioWdfDeviceCleanup(WDFDEVICE device);
NTSTATUS CsrSdioWdfDeviceAdd(WDFDEVICE device);
void CsrSdioWdfDeviceDel(WDFDEVICE device);
NTSTATUS CsrSdioWdfDeviceSuspend(WDFDEVICE device);
NTSTATUS CsrSdioWdfDeviceResume(WDFDEVICE device);
#endif /* #ifndef CSR_SDIO_WDF_H__ */
drivers/staging/csr/sdioemb/csr_types.h deleted 100644 → 0
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/*
* Synergy compatible API -- basic types.
*
* Copyright (C) 2010 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef CSR_TYPES_H__
#define CSR_TYPES_H__
#include <oska/types.h>
#ifndef FALSE
#define FALSE false
#endif
#ifndef TRUE
#define TRUE true
#endif
/* Data types */
typedef size_t CsrSize;
typedef uint8_t CsrUint8;
typedef uint16_t CsrUint16;
typedef uint32_t CsrUint32;
typedef int8_t CsrInt8;
typedef int16_t CsrInt16;
typedef int32_t CsrInt32;
typedef bool CsrBool;
typedef char CsrCharString;
typedef unsigned char CsrUtf8String;
typedef CsrUint16 CsrUtf16String; /* 16-bit UTF16 strings */
typedef CsrUint32 CsrUint24;
/*
* 64-bit integers
*
* Note: If a given compiler does not support 64-bit types, it is
* OK to omit these definitions; 32-bit versions of the code using
* these types may be available. Consult the relevant documentation
* or the customer support group for information on this.
*/
#define CSR_HAVE_64_BIT_INTEGERS
typedef uint64_t CsrUint64;
typedef int64_t CsrInt64;
#endif
drivers/staging/csr/sdioemb/libsdio.h deleted 100644 → 0
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drivers/staging/csr/sdioemb/linux.h deleted 100644 → 0
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/*
* Linux helpers for slot drivers.
*
* Copyright (C) 2009 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_LINUX_H
#define SDIOEMB_LINUX_H
#include <sdioemb/slot_api.h>
int sdioemb_linux_slot_register(struct sdioemb_slot *slot);
#endif /* #ifndef SDIOEMB_LINUX_H */
drivers/staging/csr/sdioemb/sdio.h deleted 100644 → 0
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/*
* Standard SDIO definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_SDIO_H
#define SDIOEMB_SDIO_H
/* Maximum time for VDD to rise to VDD min. */
#define SDIO_POWER_UP_TIME_MS 250
/* Minimum SD bus clock a card must support (Hz). */
#define SDIO_CLOCK_FREQ_MIN 400000
/* Maximum clock frequency for normal mode (Hz).
*
* Although high speed mode should be suitable for all speeds not all
* controller/card combinations are capable of meeting the higher
* tolerances for (e.g.) clock rise/fall times. Therefore, default
* mode is used where possible for improved compatibility. */
#define SDIO_CLOCK_FREQ_NORMAL_SPD 25000000
/* Maximum clock frequency for high speed mode (Hz). */
#define SDIO_CLOCK_FREQ_HIGH_SPD 50000000
#define SDIO_MAX_FUNCTIONS 8 /* incl. F0 */
/* Command argument format. */
#define SDIO_CMD52_ARG_WRITE 0x80000000
#define SDIO_CMD52_ARG_FUNC(f) ((f) << 28)
#define SDIO_CMD52_ARG_ADDR(a) ((a) << 9)
#define SDIO_CMD52_ARG_DATA(d) ((d) << 0)
#define SDIO_CMD53_ARG_WRITE 0x80000000
#define SDIO_CMD53_ARG_FUNC(f) ((f) << 28)
#define SDIO_CMD53_ARG_BLK_MODE 0x08000000
#define SDIO_CMD53_ARG_ADDR(a) ((a) << 9)
#define SDIO_CMD53_ARG_CNT(c) ((c) << 0)
/* Response format. */
#define SDIO_R5_DATA(r) (((r) >> 0) & 0xff)
#define SDIO_R5_OUT_OF_RANGE (1 << 8)
#define SDIO_R5_FUNCTION_NUMBER (1 << 9)
#define SDIO_R5_ERROR (1 << 11)
/* Register offsets and bits. */
#define SDIO_OCR_CARD_READY 0x80000000
#define SDIO_OCR_NUM_FUNCS_MASK 0x70000000
#define SDIO_OCR_NUM_FUNCS_OFFSET 28
#define SDIO_OCR_VOLTAGE_3V3 0x00300000 /* 3.2-3.3V & 3.3-3.4V */
#define SDIO_CCCR_SDIO_REV 0x00
#define SDIO_CCCR_SD_REV 0x01
#define SDIO_CCCR_IO_EN 0x02
#define SDIO_CCCR_IO_READY 0x03
#define SDIO_CCCR_INT_EN 0x04
# define SDIO_CCCR_INT_EN_MIE 0x01
#define SDIO_CCCR_INT_PENDING 0x05
#define SDIO_CCCR_IO_ABORT 0x06
#define SDIO_CCCR_BUS_IFACE_CNTL 0x07
# define SDIO_CCCR_BUS_IFACE_CNTL_CD_R_DISABLE 0x80
# define SDIO_CCCR_BUS_IFACE_CNTL_ECSI 0x20
# define SDIO_CCCR_BUS_IFACE_CNTL_4BIT_BUS 0x02
#define SDIO_CCCR_CARD_CAPS 0x08
# define SDIO_CCCR_CARD_CAPS_LSC 0x40
# define SDIO_CCCR_CARD_CAPS_4BLS 0x80
#define SDIO_CCCR_CIS_PTR 0x09
#define SDIO_CCCR_BUS_SUSPEND 0x0c
#define SDIO_CCCR_FUNC_SEL 0x0d
#define SDIO_CCCR_EXEC_FLAGS 0x0e
#define SDIO_CCCR_READY_FLAGS 0x0f
#define SDIO_CCCR_F0_BLK_SIZE 0x10
#define SDIO_CCCR_PWR_CNTL 0x12
#define SDIO_CCCR_HIGH_SPEED 0x13
# define SDIO_CCCR_HIGH_SPEED_SHS 0x01
# define SDIO_CCCR_HIGH_SPEED_EHS 0x02
#define SDIO_FBR_REG(f, r) (0x100*(f) + (r))
#define SDIO_FBR_STD_IFACE(f) SDIO_FBR_REG(f, 0x00)
#define SDIO_FBR_STD_IFACE_EXT(f) SDIO_FBR_REG(f, 0x01)
#define SDIO_FBR_CIS_PTR(f) SDIO_FBR_REG(f, 0x09)
#define SDIO_FBR_CSA_PTR(f) SDIO_FBR_REG(f, 0x0c)
#define SDIO_FBR_CSA_DATA(f) SDIO_FBR_REG(f, 0x0f)
#define SDIO_FBR_BLK_SIZE(f) SDIO_FBR_REG(f, 0x10)
#define SDIO_STD_IFACE_UART 0x01
#define SDIO_STD_IFACE_BT_TYPE_A 0x02
#define SDIO_STD_IFACE_BT_TYPE_B 0x03
#define SDIO_STD_IFACE_GPS 0x04
#define SDIO_STD_IFACE_CAMERA 0x05
#define SDIO_STD_IFACE_PHS 0x06
#define SDIO_STD_IFACE_WLAN 0x07
#define SDIO_STD_IFACE_BT_TYPE_A_AMP 0x09
/*
* Manufacturer and card IDs.
*/
#define SDIO_MANF_ID_CSR 0x032a
#define SDIO_CARD_ID_CSR_UNIFI_1 0x0001
#define SDIO_CARD_ID_CSR_UNIFI_2 0x0002
#define SDIO_CARD_ID_CSR_BC6 0x0004
#define SDIO_CARD_ID_CSR_DASH_D00 0x0005
#define SDIO_CARD_ID_CSR_BC7 0x0006
#define SDIO_CARD_ID_CSR_CINDERELLA 0x0007
#define SDIO_CARD_ID_CSR_UNIFI_3 0x0007
#define SDIO_CARD_ID_CSR_UNIFI_4 0x0008
#define SDIO_CARD_ID_CSR_DASH 0x0010
#endif /* #ifndef SDIOEMB_SDIO_H */
drivers/staging/csr/sdioemb/sdio_api.h deleted 100644 → 0
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drivers/staging/csr/sdioemb/sdio_bt_a.h deleted 100644 → 0
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/*
* SDIO Bluetooth Type-A interface definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_SDIO_BT_A_H
#define SDIOEMB_SDIO_BT_A_H
#include <sdioemb/sdio_csr.h>
#include <csr_sdio.h>
/*
* Standard SDIO function registers for a Bluetooth Type-A interface.
*/
#define SDIO_BT_A_RD 0x00
#define SDIO_BT_A_TD 0x00
#define SDIO_BT_A_RX_PKT_CTRL 0x10
# define PC_RRT 0x01
#define SDIO_BT_A_TX_PKT_CTRL 0x11
# define PC_WRT 0x01
#define SDIO_BT_A_RETRY_CTRL 0x12
# define RTC_STAT 0x01
# define RTC_SET 0x01
#define SDIO_BT_A_INTRD 0x13
# define INTRD 0x01
# define CL_INTRD 0x01
#define SDIO_BT_A_INT_EN 0x14
# define EN_INTRD 0x01
#define SDIO_BT_A_BT_MODE 0x20
# define MD_STAT 0x01
/*
* Length of the Type-A header.
*
* Packet length (3 octets) plus Service ID (1 octet).
*/
#define SDIO_BT_A_HEADER_LEN 4
/*
* Maximum length of a Type-A transport packet.
*
* Type-A header length and maximum length of a HCI packet (65535
* octets).
*/
#define SDIO_BT_A_PACKET_LEN_MAX 65543
enum sdioemb_bt_a_service_id {
SDIO_BT_A_SID_CMD = 0x01,
SDIO_BT_A_SID_ACL = 0x02,
SDIO_BT_A_SID_SCO = 0x03,
SDIO_BT_A_SID_EVT = 0x04,
SDIO_BT_A_SID_VENDOR = 0xfe,
};
static __inline int sdioemb_bt_a_packet_len(const char *p)
{
return (p[0] & 0xff) | ((p[1] & 0xff) << 8) | ((p[2] & 0xff) << 16);
}
static __inline int sdioemb_bt_a_service_id(const char *p)
{
return p[3];
}
/*
* Minimum amount to read (including the Type-A header). This allows
* short packets (e.g., flow control packets) to be read with a single
* command.
*/
#define SDIO_BT_A_MIN_READ 32
#define SDIO_BT_A_NAME_LEN 16
struct sdioemb_bt_a_dev {
CsrSdioFunction *func;
char name[SDIO_BT_A_NAME_LEN];
void *drv_data;
/**
* Get a buffer to receive a packet into.
*
* @param bt the BT device.
* @param header a buffer of length #SDIO_BT_A_MIN_READ containing
* (part of) the packet the buffer is for. It will contain
* the Type-A header and as much of the payload that will
* fit.
* @param buffer_min_len the minimum length of buffer required to
* receive the whole packet. This includes space for padding
* the read to a whole number of blocks (if more than 512
* octets is still to be read).
* @param buffer returns the buffer. The packet (including the
* Type-A header will be placed at the beginning of this
* buffer.
* @param buffer_handle returns a buffer handle passed to the
* subsequent call of the receive() callback.
*
* @return 0 if a buffer was provided.
* @return -ENOMEM if no buffer could be provided.
*/
int (*get_rx_buffer)(struct sdioemb_bt_a_dev *bt, const uint8_t *header,
size_t buffer_min_len, uint8_t **buffer, void **buffer_handle);
void (*receive)(struct sdioemb_bt_a_dev *bt, void *buffer_handle, int status);
void (*sleep_state_changed)(struct sdioemb_bt_a_dev *bt);
enum sdio_sleep_state sleep_state;
uint8_t max_tx_retries;
uint8_t max_rx_retries;
unsigned needs_read_ack:1;
unsigned wait_for_firmware:1;
unsigned rx_off:1;
/**
* A buffer to read the packet header into before the real buffer
* is requested with the get_rx_buffer() callback.
*
* @internal
*/
uint8_t *header;
};
int sdioemb_bt_a_setup(struct sdioemb_bt_a_dev *bt, CsrSdioFunction *func);
void sdioemb_bt_a_cleanup(struct sdioemb_bt_a_dev *bt);
int sdioemb_bt_a_send(struct sdioemb_bt_a_dev *bt, const uint8_t *packet, size_t len);
void sdioemb_bt_a_handle_interrupt(struct sdioemb_bt_a_dev *bt);
void sdioemb_bt_a_set_sleep_state(struct sdioemb_bt_a_dev *bt, enum sdio_sleep_state state);
int sdioemb_bt_a_check_for_reset(struct sdioemb_bt_a_dev *bt);
void sdioemb_bt_a_start(struct sdioemb_bt_a_dev *bt);
void sdioemb_bt_a_stop(struct sdioemb_bt_a_dev *bt);
void sdioemb_bt_a_rx_on(struct sdioemb_bt_a_dev *bt);
void sdioemb_bt_a_rx_off(struct sdioemb_bt_a_dev *bt);
#endif /* #ifndef SDIOEMB_SDIO_BT_A_H */
drivers/staging/csr/sdioemb/sdio_cis.h deleted 100644 → 0
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/*
* SDIO CIS definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SDIO_CIS_H
#define _SDIO_CIS_H
#define CISTPL_NULL 0x00
#define CISTPL_CHECKSUM 0x10
#define CISTPL_VERS_1 0x15
#define CISTPL_ALTSTR 0x16
#define CISTPL_MANFID 0x20
# define CISTPL_MANFID_SIZE 0x04
#define CISTPL_FUNCID 0x21
#define CISTPL_FUNCE 0x22
#define CISTPL_SDIO_STD 0x91
#define CISTPL_SDIO_EXT 0x92
#define CISTPL_END 0xff
#define CISTPL_FUNCE 0x22
# define CISTPL_FUNCE_00_SIZE 0x04
# define CISTPL_FUNCE_01_SIZE 0x2a
#endif /* #ifndef _SDIO_CIS_H */
drivers/staging/csr/sdioemb/sdio_csr.h deleted 100644 → 0
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/*
* CSR specific SDIO registers.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_SDIO_CSR_H
#define SDIOEMB_SDIO_CSR_H
/**
* @defgroup registers CSR specific SDIO registers
*
* Registers at 0xF0 - 0xFF in the CCCR are reserved for vendor
* specific registers. The registers documented here are specific to
* following CSR chips:
*
* - BlueCore (6 and later)
* - UltraCore
*@{
*/
/**
* Interrupt status/host wakeup register.
*
* This controls a function's deep sleep state.
*
* @see enum sdio_sleep_state
*/
#define SDIO_CSR_SLEEP_STATE 0xf0
# define SDIO_CSR_SLEEP_STATE_FUNC(f) ((f) << 4)
# define SDIO_CSR_SLEEP_STATE_RDY_INT_EN 0x02
# define SDIO_CSR_SLEEP_STATE_WAKE_REQ 0x01
/**
* Host interrupt clear register.
*
* Writing a 1 to bit 0 clears an SDIO interrupt raised by a generic
* function.
*/
#define SDIO_CSR_HOST_INT 0xf1
# define SDIO_CSR_HOST_INT_CL 0x01
/**
* From host scratch register 0.
*
* A read/write register that can be used for signalling between the
* host and the chip.
*
* The usage of this register depends on the version of the chip or
* firmware.
*/
#define SDIO_CSR_FROM_HOST_SCRATCH0 0xf2
/**
* From host scratch register 1.
*
* @see SDIO_CSR_FROM_HOST_SCRATCH0
*/
#define SDIO_CSR_FROM_HOST_SCRATCH1 0xf3
/**
* To host scratch register 0.
*
* A read only register that may be used for signalling between the
* chip and the host.
*
* The usage of this register depends on the version of the chip or
* firmware.
*/
#define SDIO_CSR_TO_HOST_SCRATCH0 0xf4
/**
* To host scratch register 1.
*
* @see SDIO_CSR_TO_HOST_SCRATCH0
*/
#define SDIO_CSR_TO_HOST_SCRATCH1 0xf5
/**
* Extended I/O enable.
*
* Similar to the standard CCCR I/O Enable register, this is used to
* detect if an internal reset of a function has occured and
* (optionally) reenable it.
*
* An internal reset is detected by CCCR I/O Enable bit being set and
* the corresponding EXT_IO_EN bit being clear.
*/
#define SDIO_CSR_EXT_IO_EN 0xf6
/**
* Deep sleep states as set via the sleep state register.
*
* These states are used to control when the chip may go into a deep
* sleep (a low power mode).
*
* Since a chip in deep sleep may not respond to SDIO commands, the
* host should ensure that the chip is not in deep sleep before
* attempting SDIO commands to functions 1 to 7.
*
* The available states are:
*
* AWAKE - chip must not enter deep sleep and should exit deep sleep
* if it's currently sleeping.
*
* TORPID - chip may enter deep sleep.
*
* DROWSY - a transition state between TORPID and AWAKE. This is
* AWAKE plus the chip asserts an interrupt when the chip is awake.
*
* @see SDIO_CSR_SLEEP_STATE
*/
enum sdio_sleep_state {
SLEEP_STATE_AWAKE = SDIO_CSR_SLEEP_STATE_WAKE_REQ,
SLEEP_STATE_DROWSY = SDIO_CSR_SLEEP_STATE_WAKE_REQ | SDIO_CSR_SLEEP_STATE_RDY_INT_EN,
SLEEP_STATE_TORPID = 0x00,
};
/*@}*/
/*
* Generic function registers (with byte addresses).
*/
/*
* SDIO_MODE is chip dependant, see the sdio_mode table in sdio_cspi.c
* to add support for new chips.
*/
#define SDIO_MODE /* chip dependant */
# define SDIO_MODE_CSPI_EN 0x40
#endif /* SDIOEMB_SDIO_CSR_H */
drivers/staging/csr/sdioemb/slot_api.h deleted 100644 → 0
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drivers/staging/csr/sdioemb/slot_imx27.h deleted 100644 → 0
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/*
* i.MX27 SDHC definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SLOT_IMX27_H
#define _SLOT_IMX27_H
/*
* i.MX27 SDHC registers.
*/
#define SDHC_STR_STP_CLK 0x00
# define STR_STP_CLK_MMCSD_RESET 0x0008
# define STR_STP_CLK_START_CLK 0x0002
# define STR_STP_CLK_STOP_CLK 0x0001
#define SDHC_STATUS 0x04
# define STATUS_CARD_PRESENCE 0x8000
# define STATUS_SDIO_INT_ACTIVE 0x4000
# define STATUS_END_CMD_RESP 0x2000
# define STATUS_WRITE_OP_DONE 0x1000
# define STATUS_READ_OP_DONE 0x0800
# define STATUS_CARD_BUS_CLK_RUN 0x0100
# define STATUS_APPL_BUFF_FF 0x0080
# define STATUS_APPL_BUFF_FE 0x0040
# define STATUS_RESP_CRC_ERR 0x0020
# define STATUS_CRC_READ_ERR 0x0008
# define STATUS_CRC_WRITE_ERR 0x0004
# define STATUS_TIME_OUT_RESP 0x0002
# define STATUS_TIME_OUT_READ 0x0001
# define STATUS_ERR_CMD_MASK (STATUS_RESP_CRC_ERR | STATUS_TIME_OUT_RESP)
# define STATUS_ERR_DATA_MASK (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR | STATUS_TIME_OUT_READ)
# define STATUS_ERR_MASK (STATUS_ERR_CMD_MASK | STATUS_ERR_DATA_MASK)
#define SDHC_CLK_RATE 0x08
#define SDHC_CMD_DAT_CTRL 0x0c /* CMD_DAT_CONT */
# define CMD_DAT_CTRL_CMD_RESUME 0x8000
# define CMD_DAT_CTRL_CMD_RESP_LONG_OFF 0x1000
# define CMD_DAT_CTRL_STOP_READ_WAIT 0x0800
# define CMD_DAT_CTRL_START_READ_WAIT 0x0400
# define CMD_DAT_CTRL_BUS_WIDTH_4 0x0200
# define CMD_DAT_CTRL_INIT 0x0080
# define CMD_DAT_CTRL_WRITE 0x0010
# define CMD_DAT_CTRL_DATA_ENABLE 0x0008
# define CMD_DAT_CTRL_RESP_NONE 0x0000
# define CMD_DAT_CTRL_RESP_R1_R5_R6 0x0001
# define CMD_DAT_CTRL_RESP_R2 0x0002
# define CMD_DAT_CTRL_RESP_R3_R4 0x0003
#define SDHC_RES_TO 0x10
#define SDHC_READ_TO 0x14
# define READ_TO_RECOMMENDED 0x2db4
#define SDHC_BLK_LEN 0x18
#define SDHC_NOB 0x1c
#define SDHC_REV_NO 0x20
#define SDHC_INT_CTRL 0x24 /* INT_CNTR */
# define INT_CTRL_CARD_INSERTION_EN 0x8000
# define INT_CTRL_SDIO_REMOVAL_EN 0x4000
# define INT_CTRL_SDIO_IRQ_EN 0x2000
# define INT_CTRL_DAT0_EN 0x1000
# define INT_CTRL_BUF_READ_EN 0x0010
# define INT_CTRL_BUF_WRITE_EN 0x0008
# define INT_CTRL_END_CMD_RES 0x0004
# define INT_CTRL_WRITE_OP_DONE 0x0002
# define INT_CTRL_READ_OP_DONE 0x0001
# define INT_CTRL_INT_EN_MASK 0xe01f
#define SDHC_CMD 0x28
#define SDHC_ARG 0x2c
#define SDHC_RES_FIFO 0x34
#define SDHC_BUFFER_ACCESS 0x38
#endif /* #ifndef _SLOT_IMX27_H */
drivers/staging/csr/sdioemb/slot_imx31.h deleted 100644 → 0
View file @ db03f1d2
/*
* i.MX31 SDHC definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SLOT_IMX31_H
#define _SLOT_IMX31_H
/*
* i.MX31 SDHC registers.
*/
#define SDHC_STR_STP_CLK 0x00
# define STR_STP_CLK_MMCSD_RESET 0x0008
# define STR_STP_CLK_START_CLK 0x0002
# define STR_STP_CLK_STOP_CLK 0x0001
#define SDHC_STATUS 0x04
# define STATUS_CARD_PRESENCE 0x8000
# define STATUS_SDIO_INT_ACTIVE 0x4000
# define STATUS_END_CMD_RESP 0x2000
# define STATUS_WRITE_OP_DONE 0x1000
# define STATUS_READ_OP_DONE 0x0800
# define STATUS_CARD_BUS_CLK_RUN 0x0100
# define STATUS_APPL_BUFF_FF 0x0080
# define STATUS_APPL_BUFF_FE 0x0040
# define STATUS_RESP_CRC_ERR 0x0020
# define STATUS_CRC_READ_ERR 0x0008
# define STATUS_CRC_WRITE_ERR 0x0004
# define STATUS_TIME_OUT_RESP 0x0002
# define STATUS_TIME_OUT_READ 0x0001
# define STATUS_ERR_CMD_MASK (STATUS_RESP_CRC_ERR | STATUS_TIME_OUT_RESP)
# define STATUS_ERR_DATA_MASK (STATUS_CRC_READ_ERR | STATUS_CRC_WRITE_ERR | STATUS_TIME_OUT_READ)
# define STATUS_ERR_MASK (STATUS_ERR_CMD_MASK | STATUS_ERR_DATA_MASK)
#define SDHC_CLK_RATE 0x08
#define SDHC_CMD_DAT_CTRL 0x0c /* CMD_DAT_CONT */
# define CMD_DAT_CTRL_CMD_RESUME 0x8000
# define CMD_DAT_CTRL_CMD_RESP_LONG_OFF 0x1000
# define CMD_DAT_CTRL_STOP_READ_WAIT 0x0800
# define CMD_DAT_CTRL_START_READ_WAIT 0x0400
# define CMD_DAT_CTRL_BUS_WIDTH_4 0x0200
# define CMD_DAT_CTRL_INIT 0x0080
# define CMD_DAT_CTRL_WRITE 0x0010
# define CMD_DAT_CTRL_DATA_ENABLE 0x0008
# define CMD_DAT_CTRL_RESP_NONE 0x0000
# define CMD_DAT_CTRL_RESP_R1_R5_R6 0x0001
# define CMD_DAT_CTRL_RESP_R2 0x0002
# define CMD_DAT_CTRL_RESP_R3_R4 0x0003
#define SDHC_RES_TO 0x10
#define SDHC_READ_TO 0x14
# define READ_TO_RECOMMENDED 0x2db4
#define SDHC_BLK_LEN 0x18
#define SDHC_NOB 0x1c
#define SDHC_REV_NO 0x20
#define SDHC_INT_CTRL 0x24 /* INT_CNTR */
# define INT_CTRL_CARD_INSERTION_EN 0x8000
# define INT_CTRL_SDIO_REMOVAL_EN 0x4000
# define INT_CTRL_SDIO_IRQ_EN 0x2000
# define INT_CTRL_DAT0_EN 0x1000
# define INT_CTRL_BUF_READ_EN 0x0010
# define INT_CTRL_BUF_WRITE_EN 0x0008
# define INT_CTRL_END_CMD_RES 0x0004
# define INT_CTRL_WRITE_OP_DONE 0x0002
# define INT_CTRL_READ_OP_DONE 0x0001
# define INT_CTRL_INT_EN_MASK 0xe01f
#define SDHC_CMD 0x28
#define SDHC_ARG 0x2c
#define SDHC_RES_FIFO 0x34
#define SDHC_BUFFER_ACCESS 0x38
#endif /* #ifndef _SLOT_IMX31_H */
drivers/staging/csr/sdioemb/slot_pxa27x.h deleted 100644 → 0
View file @ db03f1d2
/*
* PXA27x MMC/SD controller definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SLOT_PXA27X_H
#define _SLOT_PXA27X_H
#define PXA27X_MMC_MMCLK_BASE_FREQ 19500000
#define PXA27X_MMC_FIFO_SIZE 32
#define STOP_CLOCK (1 << 0)
#define START_CLOCK (2 << 0)
#define STAT_END_CMD_RES (1 << 13)
#define STAT_PRG_DONE (1 << 12)
#define STAT_DATA_TRAN_DONE (1 << 11)
#define STAT_CLK_EN (1 << 8)
#define STAT_RECV_FIFO_FULL (1 << 7)
#define STAT_XMIT_FIFO_EMPTY (1 << 6)
#define STAT_RES_CRC_ERR (1 << 5)
#define STAT_SPI_READ_ERROR_TOKEN (1 << 4)
#define STAT_CRC_READ_ERROR (1 << 3)
#define STAT_CRC_WRITE_ERROR (1 << 2)
#define STAT_TIME_OUT_RESPONSE (1 << 1)
#define STAT_READ_TIME_OUT (1 << 0)
#define SPI_CS_ADDRESS (1 << 3)
#define SPI_CS_EN (1 << 2)
#define CRC_ON (1 << 1)
#define SPI_EN (1 << 0)
#define CMDAT_SDIO_INT_EN (1 << 11)
#define CMDAT_STOP_TRAN (1 << 10)
#define CMDAT_SD_4DAT (1 << 8)
#define CMDAT_DMAEN (1 << 7)
#define CMDAT_INIT (1 << 6)
#define CMDAT_BUSY (1 << 5)
#define CMDAT_STREAM (1 << 4) /* 1 = stream */
#define CMDAT_WRITE (1 << 3) /* 1 = write */
#define CMDAT_DATAEN (1 << 2)
#define CMDAT_RESP_NONE (0 << 0)
#define CMDAT_RESP_SHORT (1 << 0)
#define CMDAT_RESP_R2 (2 << 0)
#define CMDAT_RESP_R3 (3 << 0)
#define RDTO_MAX 0xffff
#define BUF_PART_FULL (1 << 0)
#define SDIO_SUSPEND_ACK (1 << 12)
#define SDIO_INT (1 << 11)
#define RD_STALLED (1 << 10)
#define RES_ERR (1 << 9)
#define DAT_ERR (1 << 8)
#define TINT (1 << 7)
#define TXFIFO_WR_REQ (1 << 6)
#define RXFIFO_RD_REQ (1 << 5)
#define CLK_IS_OFF (1 << 4)
#define STOP_CMD (1 << 3)
#define END_CMD_RES (1 << 2)
#define PRG_DONE (1 << 1)
#define DATA_TRAN_DONE (1 << 0)
#define MMC_I_MASK_ALL 0x00001fff
#endif /* #ifndef _SLOT_PXA27X_H */
drivers/staging/csr/sdioemb/slot_shc.h deleted 100644 → 0
View file @ db03f1d2
/*
* Standard Host Controller definitions.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SLOT_SHC_H
#define _SLOT_SHC_H
#include <oska/io.h>
/* SHC registers */
#define SHC_SYSTEM_ADDRESS 0x00
#define SHC_BLOCK_SIZE 0x04
# define SHC_BLOCK_SIZE_DMA_BOUNDARY_4K (0x0 << 12)
# define SHC_BLOCK_SIZE_DMA_BOUNDARY_512K (0x7 << 12)
#define SHC_BLOCK_COUNT 0x06
#define SHC_ARG 0x08
#define SHC_TRANSFER_MODE 0x0c
# define SHC_TRANSFER_MODE_DMA_EN 0x0001
# define SHC_TRANSFER_MODE_BLK_CNT_EN 0x0002
# define SHC_TRANSFER_MODE_AUTO_CMD12_EN 0x0004
# define SHC_TRANSFER_MODE_DATA_READ 0x0010
# define SHC_TRANSFER_MODE_MULTI_BLK 0x0020
#define SHC_CMD 0x0e
# define SHC_CMD_RESP_NONE 0x0000
# define SHC_CMD_RESP_136 0x0001
# define SHC_CMD_RESP_48 0x0002
# define SHC_CMD_RESP_48B 0x0003
# define SHC_CMD_RESP_CRC_CHK 0x0008
# define SHC_CMD_RESP_IDX_CHK 0x0010
# define SHC_CMD_DATA_PRESENT 0x0020
# define SHC_CMD_TYPE_ABORT (0x3 << 6)
# define SHC_CMD_IDX(c) ((c) << 8)
#define SHC_RESPONSE_0_31 0x10
#define SHC_BUFFER_DATA_PORT 0x20
#define SHC_PRESENT_STATE 0x24
# define SHC_PRESENT_STATE_CMD_INHIBIT 0x00000001
# define SHC_PRESENT_STATE_DAT_INHIBIT 0x00000002
# define SHC_PRESENT_STATE_CARD_PRESENT 0x00010000
#define SHC_HOST_CTRL 0x28
# define SHC_HOST_CTRL_LED_ON 0x01
# define SHC_HOST_CTRL_4BIT 0x02
# define SHC_HOST_CTRL_HIGH_SPD_EN 0x04
#define SHC_PWR_CTRL 0x29
# define SHC_PWR_CTRL_3V3 0x0e
# define SHC_PWR_CTRL_ON 0x01
#define SHC_BLOCK_GAP_CTRL 0x2a
#define SHC_WAKEUP_CTRL 0x2b
#define SHC_CLOCK_CTRL 0x2c
# define SHC_CLOCK_CTRL_INT_CLK_EN 0x01
# define SHC_CLOCK_CTRL_INT_CLK_STABLE 0x02
# define SHC_CLOCK_CTRL_SD_CLK_EN 0x04
# define SHC_CLOCK_CTRL_DIV(d) (((d) >> 1) << 8) /* divisor must be power of 2 */
#define SHC_TIMEOUT_CTRL 0x2e
# define SHC_TIMEOUT_CTRL_MAX 0x0e
#define SHC_SOFTWARE_RST 0x2f
# define SHC_SOFTWARE_RST_ALL 0x01
# define SHC_SOFTWARE_RST_CMD 0x02
# define SHC_SOFTWARE_RST_DAT 0x04
#define SHC_INT_STATUS 0x30
#define SHC_INT_STATUS_EN 0x34
#define SHC_INT_SIGNAL_EN 0x38
# define SHC_INT_CMD_COMPLETE 0x00000001
# define SHC_INT_TRANSFER_COMPLETE 0x00000002
# define SHC_INT_BLOCK_GAP 0x00000004
# define SHC_INT_DMA 0x00000008
# define SHC_INT_WR_BUF_RDY 0x00000010
# define SHC_INT_RD_BUF_RDY 0x00000020
# define SHC_INT_CARD_INSERTED 0x00000040
# define SHC_INT_CARD_REMOVED 0x00000080
# define SHC_INT_CARD_INT 0x00000100
# define SHC_INT_ERR_ANY 0x00008000
# define SHC_INT_ERR_CMD_TIMEOUT 0x00010000
# define SHC_INT_ERR_CMD_CRC 0x00020000
# define SHC_INT_ERR_CMD_ENDBIT 0x00040000
# define SHC_INT_ERR_CMD_INDEX 0x00080000
# define SHC_INT_ERR_CMD_ALL 0x000f0000
# define SHC_INT_ERR_DAT_TIMEOUT 0x00100000
# define SHC_INT_ERR_DAT_CRC 0x00200000
# define SHC_INT_ERR_DAT_ENDBIT 0x00400000
# define SHC_INT_ERR_DAT_ALL 0x00700000
# define SHC_INT_ERR_CURRENT_LIMIT 0x00800000
# define SHC_INT_ERR_AUTO_CMD12 0x01000000
# define SHC_INT_ERR_ALL 0x01ff0000
# define SHC_INT_ALL 0x01ff81ff
#define SHC_AUTO_CMD12_STATUS 0x3c
#define SHC_CAPS 0x40
# define SHC_CAPS_TO_BASE_CLK_FREQ(c) (((c) & 0x00003f00) >> 8)
# define SHC_CAPS_PWR_3V3 (1 << 24)
#define SHC_MAX_CURRENT_CAPS 0x4c
/* PCI configuration registers. */
#define PCI_SHC_SLOT_INFO 0x40
/* Maximum time to wait for a software reset. */
#define SHC_RESET_TIMEOUT_MS 100 /* ms */
/* Maximum time to wait for internal clock to stabilize */
#define SHC_INT_CLK_STABLE_TIMEOUT_MS 100
/*
* No supported voltages in the capabilities register.
*
* Workaround: Assume 3.3V is supported.
*/
#define SLOT_SHC_QUIRK_NO_VOLTAGE_CAPS (1 << 0)
/*
* Commands with an R5B (busy) response do not complete.
*
* Workaround: Use R5 instead. This will only work if the busy signal
* is cleared sufficiently quickly before the next command is started.
*/
#define SLOT_SHC_QUIRK_R5B_BROKEN (1 << 1)
/*
* High speed mode doesn't work.
*
* Workaround: limit maximum bus frequency to 25 MHz.
*/
#define SLOT_SHC_QUIRK_HIGH_SPD_BROKEN (1 << 2)
/*
* Data timeout (TIMEOUT_CTRL) uses SDCLK and not TMCLK.
*
* Workaround: set TIMEOUT_CTRL using SDCLK.
*/
#define SLOT_SHC_QUIRK_DATA_TIMEOUT_USES_SDCLK (1 << 3)
/*
* Controller can only start DMA on dword (32 bit) aligned addresses.
*
* Workaround: PIO is used on data transfers with a non-dword aligned
* address.
*/
#define SHC_QUIRK_DMA_NEEDS_DWORD_ALIGNED_ADDR (1 << 4)
/*
* Controller is unreliable following multiple transfers
*
* Workaround: The controller is reset following every command, not just
* erroneous ones
*/
#define SHC_QUIRK_RESET_EVERY_CMD_COMPLETE (1 << 5)
/*
* JMicron JMB381 to JMB385 controllers require some non-standard PCI
* config space writes.
*/
#define SHC_QUIRK_JMICRON_JMB38X (1 << 6)
/*
* Controller can only do DMA if the length is a whole number of
* dwords.
*
* Controller with this quirk probably also need
* SHC_QUIRK_DMA_NEEDS_DWORD_ALIGNED_ADDR.
*
* Workaround: PIO is used on data transfers that don't end on an
* aligned address.
*/
#define SHC_QUIRK_DMA_NEEDS_DWORD_ALIGNED_LEN (1 << 7)
struct sdioemb_shc {
struct sdioemb_slot *slot;
void (*enable_int)(struct sdioemb_slot *slot, uint32_t ints);
void (*disable_int)(struct sdioemb_slot *slot, uint32_t ints);
void (*cmd_complete)(struct sdioemb_slot *slot, struct sdioemb_cmd *cmd);
uint32_t quirks;
os_io_mem_t addr;
os_spinlock_t lock;
os_timer_t lockup_timer;
uint32_t base_clk;
struct sdioemb_cmd *current_cmd;
uint8_t *data;
size_t remaining;
size_t block_size;
};
void sdioemb_shc_init(struct sdioemb_shc *shc);
void sdioemb_shc_clean_up(struct sdioemb_shc *shc);
int sdioemb_shc_start(struct sdioemb_shc *shc);
void sdioemb_shc_stop(struct sdioemb_shc *shc);
bool sdioemb_shc_isr(struct sdioemb_shc *shc, uint32_t *int_stat);
void sdioemb_shc_dsr(struct sdioemb_shc *shc, uint32_t int_stat);
int sdioemb_shc_set_bus_freq(struct sdioemb_shc *shc, int clk);
int sdioemb_shc_set_bus_width(struct sdioemb_shc *shc, int bus_width);
int sdioemb_shc_start_cmd(struct sdioemb_shc *shc, struct sdioemb_cmd *cmd,
bool use_dma, uint64_t dma_addr);
int sdioemb_shc_card_present(struct sdioemb_shc *shc);
int sdioemb_shc_card_power(struct sdioemb_shc *shc, enum sdioemb_power power);
void sdioemb_shc_enable_card_int(struct sdioemb_shc *shc);
void sdioemb_shc_disable_card_int(struct sdioemb_shc *shc);
int sdioemb_shc_hard_reset(struct sdioemb_shc *shc);
void sdioemb_shc_show_quirks(struct sdioemb_shc *shc);
#endif /* #ifndef _SLOT_SHC_H */
drivers/staging/csr/sdioemb/slot_ushc.h deleted 100644 → 0
View file @ db03f1d2
/*
* USB Standard Host Controller definitions.
*
* Copyright (C) 2010 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef _SLOT_USHC_H
#define _SLOT_USHC_H
#include <oska/io.h>
enum ushc_request
{
USHC_GET_CAPS = 0x00,
USHC_HOST_CTRL = 0x01,
USHC_PWR_CTRL = 0x02,
USHC_CLK_FREQ = 0x03,
USHC_EXEC_CMD = 0x04,
USHC_READ_RESP = 0x05,
USHC_RESET = 0x06
};
enum ushc_request_recipient
{
USHC_RECIPIENT_DEVICE = 0x00,
USHC_RECIPIENT_INTERFACE = 0x01,
USHC_RECIPIENT_ENDPOINT = 0x02,
USHC_RECIPIENT_OTHER = 0x03
};
enum ushc_request_direction
{
USHC_HOST_TO_DEVICE = 0x00,
USHC_DEVICE_TO_HOST = 0x01
};
struct sdioemb_ushc
{
struct sdioemb_slot *slot;
void (*enable_int)(struct sdioemb_slot *slot, uint32_t ints);
void (*disable_int)(struct sdioemb_slot *slot, uint32_t ints);
void (*cmd_complete)(struct sdioemb_slot *slot, struct sdioemb_cmd *cmd);
int (*set_host_ctrl)(struct sdioemb_slot *slot, uint16_t controler_state);
int (*submit_vendor_request)(struct sdioemb_slot *slot,
enum ushc_request request,
enum ushc_request_direction direction,
enum ushc_request_recipient recipient,
uint16_t value,
uint16_t index,
void* io_buffer,
uint32_t io_buffer_length);
int (*submit_cbw_request)(struct sdioemb_slot *slot, uint8_t cmd_index, uint16_t block_size, uint32_t cmd_arg);
int (*submit_data_request)(struct sdioemb_slot *slot,
enum ushc_request_direction direction,
void* request_buffer,
uint32_t request_buffer_length);
int (*submit_csw_request)(struct sdioemb_slot *slot);
os_spinlock_t lock;
uint32_t base_clock;
uint32_t controler_capabilities;
uint16_t controler_state;
struct sdioemb_cmd* current_cmd;
#define DISCONNECTED 0
#define INT_EN 1
#define IGNORE_NEXT_INT 2
#define STOP 4
uint32_t flags;
#define USHC_INT_STATUS_SDIO_INT (1 << 1)
#define USHC_INT_STATUS_CARD_PRESENT (1 << 0)
uint8_t interrupt_status;
size_t block_size;
};
#define USHC_GET_CAPS_VERSION_MASK 0xff
#define USHC_GET_CAPS_3V3 (1 << 8)
#define USHC_GET_CAPS_3V0 (1 << 9)
#define USHC_GET_CAPS_1V8 (1 << 10)
#define USHC_GET_CAPS_HIGH_SPD (1 << 16)
#define USHC_PWR_CTRL_OFF 0x00
#define USHC_PWR_CTRL_3V3 0x01
#define USHC_PWR_CTRL_3V0 0x02
#define USHC_PWR_CTRL_1V8 0x03
#define USHC_HOST_CTRL_4BIT (1 << 1)
#define USHC_HOST_CTRL_HIGH_SPD (1 << 0)
#define USHC_READ_RESP_BUSY (1 << 4)
#define USHC_READ_RESP_ERR_TIMEOUT (1 << 3)
#define USHC_READ_RESP_ERR_CRC (1 << 2)
#define USHC_READ_RESP_ERR_DAT (1 << 1)
#define USHC_READ_RESP_ERR_CMD (1 << 0)
#define USHC_READ_RESP_ERR_MASK 0x0f
void sdioemb_ushc_init(struct sdioemb_ushc* ushc);
void sdioemb_ushc_clean_up(struct sdioemb_ushc* ushc);
int sdioemb_ushc_start(struct sdioemb_ushc* ushc);
void sdioemb_ushc_stop(struct sdioemb_ushc* ushc);
bool sdioemb_ushc_isr(struct sdioemb_ushc* ushc, uint8_t int_stat);
int sdioemb_ushc_set_bus_freq(struct sdioemb_ushc* ushc, int clk);
int sdioemb_ushc_set_bus_width(struct sdioemb_ushc* ushc, int bus_width);
int sdioemb_ushc_start_cmd(struct sdioemb_ushc* ushc, struct sdioemb_cmd *cmd);
int sdioemb_ushc_card_present(struct sdioemb_ushc* ushc);
int sdioemb_ushc_card_power(struct sdioemb_ushc* ushc, enum sdioemb_power power);
void sdioemb_ushc_enable_card_int(struct sdioemb_ushc* ushc);
void sdioemb_ushc_disable_card_int(struct sdioemb_ushc* ushc);
int sdioemb_ushc_hard_reset(struct sdioemb_ushc* ushc);
void sdioemb_ushc_command_complete(struct sdioemb_ushc* ushc, uint8_t status, uint32_t respones);
int ushc_hw_get_caps(struct sdioemb_ushc* ushc);
static int ushc_hw_set_host_ctrl(struct sdioemb_ushc* ushc, uint16_t mask, uint16_t val);
static int ushc_hw_submit_vendor_request(struct sdioemb_ushc* ushc,
enum ushc_request request,
enum ushc_request_recipient recipient,
enum ushc_request_direction direction,
uint16_t value,
uint16_t index,
void* io_buffer,
uint32_t io_buffer_length);
#endif
drivers/staging/csr/sdioemb/trace.h deleted 100644 → 0
View file @ db03f1d2
/*
* Sdioemb trace messages.
*
* Copyright (C) 2009 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef SDIOEMB_TRACE_H
#define SDIOEMB_TRACE_H
#if defined(__linux__)
# define OS_TRACE_PREFIX "sdioemb: "
#endif
#include <oska/trace.h>
#endif /* #ifndef SDIOEMB_TRACE_H */
drivers/staging/csr/sdioemb/uif.h deleted 100644 → 0
View file @ db03f1d2
/*
* Userspace interface to the SDIO Userspace Interface driver.
*
* Copyright (C) 2007 Cambridge Silicon Radio Ltd.
*
* Refer to LICENSE.txt included with this source code for details on
* the license terms.
*/
#ifndef LINUX_SDIOEMB_UIF_H
#define LINUX_SDIOEMB_UIF_H
enum sdioemb_uif_cmd_type {
SDIOEMB_UIF_CMD52_READ, SDIOEMB_UIF_CMD52_WRITE,
SDIOEMB_UIF_CMD53_READ, SDIOEMB_UIF_CMD53_WRITE,
};
struct sdioemb_uif_cmd {
enum sdioemb_uif_cmd_type type;
int function;
uint32_t address;
uint8_t * data;
size_t len;
int block_size;
};
#define SDIOEMB_UIF_IOC_MAGIC 's'
#define SDIOEMB_UIF_IOCQNUMFUNCS _IO(SDIOEMB_UIF_IOC_MAGIC, 0)
#define SDIOEMB_UIF_IOCCMD _IOWR(SDIOEMB_UIF_IOC_MAGIC, 1, struct sdioemb_uif_cmd)
#define SDIOEMB_UIF_IOCWAITFORINT _IO(SDIOEMB_UIF_IOC_MAGIC, 2)
#define SDIOEMB_UIF_IOCTBUSWIDTH _IO(SDIOEMB_UIF_IOC_MAGIC, 3)
#define SDIOEMB_UIF_IOCREINSERT _IO(SDIOEMB_UIF_IOC_MAGIC, 4)
#define SDIOEMB_UIF_IOCTBUSFREQ _IO(SDIOEMB_UIF_IOC_MAGIC, 5)
#define SDIOEMB_UIF_IOCQMANFID _IO(SDIOEMB_UIF_IOC_MAGIC, 6)
#define SDIOEMB_UIF_IOCQCARDID _IO(SDIOEMB_UIF_IOC_MAGIC, 7)
#define SDIOEMB_UIF_IOCQSTDIF _IO(SDIOEMB_UIF_IOC_MAGIC, 8)
#define SDIOEMB_UIF_IOCQMAXBLKSZ _IO(SDIOEMB_UIF_IOC_MAGIC, 9)
#define SDIOEMB_UIF_IOCQBLKSZ _IO(SDIOEMB_UIF_IOC_MAGIC, 10)
#define SDIOEMB_UIF_IOCTBLKSZ _IO(SDIOEMB_UIF_IOC_MAGIC, 11)
#endif /* #ifndef LINUX_SDIOEMB_UIF_H */
drivers/staging/csr/sdioemb/version.h deleted 100644 → 0
View file @ db03f1d2
/* Autogenerated by the sdioemb release procedure. */
#ifndef SDIOEMB_VERSION_H
#define SDIOEMB_VERSION_H
#define SDIOEMB_RELEASE 31
#ifndef SDIOEMB_RELEASE_EXTRA
#define SDIOEMB_RELEASE_EXTRA ""
#endif
#endif /* #ifndef SDIOEMB_VERSION_H */
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