clk: rockchip: Optimize PLL table memory usage

Before the change: The sizeof rk3568_pll_rates = 2544
Use union: The sizeof rk3568_pll_rates = 1696

In future Soc, more PLL types will be added, and the
rockchip_pll_rate_table will add more members,
and the space savings will be even more pronounced
by using union.
Signed-off-by: Elaine Zhang <zhangqing@rock-chips.com>
Link: https://lore.kernel.org/r/20210511090726.15146-1-zhangqing@rock-chips.comSigned-off-by: Heiko Stuebner <heiko@sntech.de>

drivers/clk/rockchip/clk.h

@@ -271,10 +271,15 @@ struct rockchip_clk_provider {
 
 struct rockchip_pll_rate_table {
 	unsigned long rate;
+	union {
+		struct {
+			/* for RK3066 */
 			unsigned int nr;
 			unsigned int nf;
 			unsigned int no;
 			unsigned int nb;
+		};
+		struct {
 			/* for RK3036/RK3399 */
 			unsigned int fbdiv;
 			unsigned int postdiv1;
@@ -282,6 +287,8 @@ struct rockchip_pll_rate_table {
 			unsigned int postdiv2;
 			unsigned int dsmpd;
 			unsigned int frac;
+		};
+	};
 };
 
 /**