Commit 24a70cf2 authored by Steven Miao's avatar Steven Miao

blackfin: scb: Add system crossbar init code.

If SCB exists in select blackfin cpu, developer can change the SCB
priority in kernel configuration.
Signed-off-by: default avatarSonic Zhang <sonic.zhang@analog.com>
Signed-off-by: default avatarSteven Miao <realmz6@gmail.com>
parent 6e466452
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#define SCB_SLOT_OFFSET 24
#define SCB_MI_MAX_SLOT 32
struct scb_mi_prio {
unsigned long scb_mi_arbr;
unsigned long scb_mi_arbw;
unsigned char scb_mi_slots;
unsigned char scb_mi_prio[SCB_MI_MAX_SLOT];
};
extern struct scb_mi_prio scb_data[];
extern void init_scb(void);
...@@ -35,6 +35,9 @@ ...@@ -35,6 +35,9 @@
#ifdef CONFIG_BF60x #ifdef CONFIG_BF60x
#include <mach/pm.h> #include <mach/pm.h>
#endif #endif
#ifdef CONFIG_SCB_PRIORITY
#include <asm/scb.h>
#endif
u16 _bfin_swrst; u16 _bfin_swrst;
EXPORT_SYMBOL(_bfin_swrst); EXPORT_SYMBOL(_bfin_swrst);
...@@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p) ...@@ -1101,6 +1104,9 @@ void __init setup_arch(char **cmdline_p)
#endif #endif
init_exception_vectors(); init_exception_vectors();
bfin_cache_init(); /* Initialize caches for the boot CPU */ bfin_cache_init(); /* Initialize caches for the boot CPU */
#ifdef CONFIG_SCB_PRIORITY
init_scb();
#endif
} }
static int __init topology_init(void) static int __init topology_init(void)
......
...@@ -59,6 +59,1023 @@ config SEC_IRQ_PRIORITY_LEVELS ...@@ -59,6 +59,1023 @@ config SEC_IRQ_PRIORITY_LEVELS
Divide the total number of interrupt priority levels into sub-levels. Divide the total number of interrupt priority levels into sub-levels.
There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels. There is 2 ^ (SEC_IRQ_PRIORITY_LEVELS + 1) different levels.
comment "System Cross Bar Priority Assignment"
config SCB_PRIORITY
bool "Init System Cross Bar Priority"
default n
menuconfig SCB0_MI0
bool "SCB0 Master Interface 0 (DDR)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI0
config SCB0_MI0_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT1
int "Slot 1 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT2
int "Slot 2 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT3
int "Slot 3 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT4
int "Slot 4 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT5
int "Slot 5 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT6
int "Slot 6 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT7
int "Slot 7 slave interface id"
default 9
range 0 13
config SCB0_MI0_SLOT8
int "Slot 8 slave interface id"
default 10
range 0 13
config SCB0_MI0_SLOT9
int "Slot 9 slave interface id"
default 11
range 0 13
config SCB0_MI0_SLOT10
int "Slot 10 slave interface id"
default 13
range 0 13
config SCB0_MI0_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI0_SLOT12
int "Slot 12 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT13
int "Slot 13 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT14
int "Slot 14 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT15
int "Slot 15 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT16
int "Slot 16 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT17
int "Slot 17 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT18
int "Slot 18 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT19
int "Slot 19 slave interface id"
default 9
range 0 13
config SCB0_MI0_SLOT20
int "Slot 20 slave interface id"
default 10
range 0 13
config SCB0_MI0_SLOT21
int "Slot 21 slave interface id"
default 11
range 0 13
config SCB0_MI0_SLOT22
int "Slot 22 slave interface id"
default 13
range 0 13
config SCB0_MI0_SLOT23
int "Slot 23 slave interface id"
default 12
range 0 13
config SCB0_MI0_SLOT24
int "Slot 24 slave interface id"
default 0
range 0 13
config SCB0_MI0_SLOT25
int "Slot 25 slave interface id"
default 2
range 0 13
config SCB0_MI0_SLOT26
int "Slot 26 slave interface id"
default 4
range 0 13
config SCB0_MI0_SLOT27
int "Slot 27 slave interface id"
default 5
range 0 13
config SCB0_MI0_SLOT28
int "Slot 28 slave interface id"
default 6
range 0 13
config SCB0_MI0_SLOT29
int "Slot 29 slave interface id"
default 7
range 0 13
config SCB0_MI0_SLOT30
int "Slot 30 slave interface id"
default 8
range 0 13
config SCB0_MI0_SLOT31
int "Slot 31 slave interface id"
default 13
range 0 13
endif # SCB0_MI0
menuconfig SCB0_MI1
bool "SCB0 Master Interface 1 (SMC)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI1
config SCB0_MI1_SLOT0
int "Slot 0 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT1
int "Slot 1 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT2
int "Slot 2 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT3
int "Slot 3 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT4
int "Slot 4 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT5
int "Slot 5 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT6
int "Slot 6 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT7
int "Slot 7 slave interface id"
default 9
range 0 13
config SCB0_MI1_SLOT8
int "Slot 8 slave interface id"
default 10
range 0 13
config SCB0_MI1_SLOT9
int "Slot 9 slave interface id"
default 11
range 0 13
config SCB0_MI1_SLOT10
int "Slot 10 slave interface id"
default 13
range 0 13
config SCB0_MI1_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI1_SLOT12
int "Slot 12 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT13
int "Slot 13 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT14
int "Slot 14 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT15
int "Slot 15 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT16
int "Slot 16 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT17
int "Slot 17 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT18
int "Slot 18 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT19
int "Slot 19 slave interface id"
default 9
range 0 13
config SCB0_MI1_SLOT20
int "Slot 20 slave interface id"
default 10
range 0 13
config SCB0_MI1_SLOT21
int "Slot 21 slave interface id"
default 11
range 0 13
config SCB0_MI1_SLOT22
int "Slot 22 slave interface id"
default 13
range 0 13
config SCB0_MI1_SLOT23
int "Slot 23 slave interface id"
default 12
range 0 13
config SCB0_MI1_SLOT24
int "Slot 24 slave interface id"
default 0
range 0 13
config SCB0_MI1_SLOT25
int "Slot 25 slave interface id"
default 2
range 0 13
config SCB0_MI1_SLOT26
int "Slot 26 slave interface id"
default 4
range 0 13
config SCB0_MI1_SLOT27
int "Slot 27 slave interface id"
default 5
range 0 13
config SCB0_MI1_SLOT28
int "Slot 28 slave interface id"
default 6
range 0 13
config SCB0_MI1_SLOT29
int "Slot 29 slave interface id"
default 7
range 0 13
config SCB0_MI1_SLOT30
int "Slot 30 slave interface id"
default 8
range 0 13
config SCB0_MI1_SLOT31
int "Slot 31 slave interface id"
default 13
range 0 13
endif # SCB0_MI1
menuconfig SCB0_MI2
bool "SCB0 Master Interface 2 (Data L2)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI2
config SCB0_MI2_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI2_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI2_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI2_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI2_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI2_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI2_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI2_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI2_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI2_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI2_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI2
menuconfig SCB0_MI3
bool "SCB0 Master Interface 3 (L1A)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI3
config SCB0_MI3_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI3_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI3_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI3_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI3_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI3_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI3_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI3_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI3_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI3_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI3_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI3
menuconfig SCB0_MI4
bool "SCB0 Master Interface 4 (L1B)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
Core 0 -- 0
Core 1 -- 2
SCB1 -- 9
SCB2 -- 10
SCB3 -- 11
SCB4 -- 12
SCB5 -- 5
SCB6 -- 6
SCB7 -- 8
SCB8 -- 7
SCB9 -- 4
USB -- 13
if SCB0_MI4
config SCB0_MI4_SLOT0
int "Slot 0 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT1
int "Slot 1 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT2
int "Slot 2 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT3
int "Slot 3 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT4
int "Slot 4 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT5
int "Slot 5 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT7
int "Slot 7 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT8
int "Slot 8 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT9
int "Slot 9 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT10
int "Slot 10 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT11
int "Slot 11 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT12
int "Slot 12 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT13
int "Slot 13 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT14
int "Slot 14 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT15
int "Slot 15 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT16
int "Slot 16 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT17
int "Slot 17 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT18
int "Slot 18 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT19
int "Slot 19 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT20
int "Slot 20 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT21
int "Slot 21 slave interface id"
default 5
range 0 13
config SCB0_MI4_SLOT22
int "Slot 22 slave interface id"
default 6
range 0 13
config SCB0_MI4_SLOT23
int "Slot 23 slave interface id"
default 7
range 0 13
config SCB0_MI4_SLOT24
int "Slot 24 slave interface id"
default 8
range 0 13
config SCB0_MI4_SLOT25
int "Slot 25 slave interface id"
default 9
range 0 13
config SCB0_MI4_SLOT26
int "Slot 26 slave interface id"
default 10
range 0 13
config SCB0_MI4_SLOT27
int "Slot 27 slave interface id"
default 11
range 0 13
config SCB0_MI4_SLOT28
int "Slot 28 slave interface id"
default 13
range 0 13
config SCB0_MI4_SLOT29
int "Slot 29 slave interface id"
default 12
range 0 13
config SCB0_MI4_SLOT30
int "Slot 30 slave interface id"
default 4
range 0 13
config SCB0_MI4_SLOT31
int "Slot 31 slave interface id"
default 7
range 0 13
endif # SCB0_MI4
menuconfig SCB0_MI5
bool "SCB0 Master Interface 5 (SMMR)"
default n
depends on SCB_PRIORITY
help
The slave interface id of each slot should be set according following table.
MMR0 -- 1
MMR1 -- 3
SCB2 -- 10
SCB4 -- 12
if SCB0_MI5
config SCB0_MI5_SLOT0
int "Slot 0 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT1
int "Slot 1 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT2
int "Slot 2 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT3
int "Slot 3 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT4
int "Slot 4 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT5
int "Slot 5 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT6
int "Slot 6 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT7
int "Slot 7 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT8
int "Slot 8 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT9
int "Slot 9 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT10
int "Slot 10 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT11
int "Slot 11 slave interface id"
default 12
range 0 13
config SCB0_MI5_SLOT12
int "Slot 12 slave interface id"
default 1
range 0 13
config SCB0_MI5_SLOT13
int "Slot 13 slave interface id"
default 3
range 0 13
config SCB0_MI5_SLOT14
int "Slot 14 slave interface id"
default 10
range 0 13
config SCB0_MI5_SLOT15
int "Slot 15 slave interface id"
default 12
range 0 13
endif # SCB0_MI5
endmenu endmenu
endif endif
...@@ -4,3 +4,4 @@ ...@@ -4,3 +4,4 @@
obj-y := dma.o clock.o ints-priority.o obj-y := dma.o clock.o ints-priority.o
obj-$(CONFIG_PM) += pm.o dpm.o obj-$(CONFIG_PM) += pm.o dpm.o
obj-$(CONFIG_SCB_PRIORITY) += scb.o
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <asm/blackfin.h>
#include <asm/scb.h>
struct scb_mi_prio scb_data[] = {
#ifdef CONFIG_SCB0_MI0
{ REG_SCB0_ARBR0, REG_SCB0_ARBW0, 32, {
CONFIG_SCB0_MI0_SLOT0,
CONFIG_SCB0_MI0_SLOT1,
CONFIG_SCB0_MI0_SLOT2,
CONFIG_SCB0_MI0_SLOT3,
CONFIG_SCB0_MI0_SLOT4,
CONFIG_SCB0_MI0_SLOT5,
CONFIG_SCB0_MI0_SLOT6,
CONFIG_SCB0_MI0_SLOT7,
CONFIG_SCB0_MI0_SLOT8,
CONFIG_SCB0_MI0_SLOT9,
CONFIG_SCB0_MI0_SLOT10,
CONFIG_SCB0_MI0_SLOT11,
CONFIG_SCB0_MI0_SLOT12,
CONFIG_SCB0_MI0_SLOT13,
CONFIG_SCB0_MI0_SLOT14,
CONFIG_SCB0_MI0_SLOT15,
CONFIG_SCB0_MI0_SLOT16,
CONFIG_SCB0_MI0_SLOT17,
CONFIG_SCB0_MI0_SLOT18,
CONFIG_SCB0_MI0_SLOT19,
CONFIG_SCB0_MI0_SLOT20,
CONFIG_SCB0_MI0_SLOT21,
CONFIG_SCB0_MI0_SLOT22,
CONFIG_SCB0_MI0_SLOT23,
CONFIG_SCB0_MI0_SLOT24,
CONFIG_SCB0_MI0_SLOT25,
CONFIG_SCB0_MI0_SLOT26,
CONFIG_SCB0_MI0_SLOT27,
CONFIG_SCB0_MI0_SLOT28,
CONFIG_SCB0_MI0_SLOT29,
CONFIG_SCB0_MI0_SLOT30,
CONFIG_SCB0_MI0_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI1
{ REG_SCB0_ARBR1, REG_SCB0_ARBW1, 32, {
CONFIG_SCB0_MI1_SLOT0,
CONFIG_SCB0_MI1_SLOT1,
CONFIG_SCB0_MI1_SLOT2,
CONFIG_SCB0_MI1_SLOT3,
CONFIG_SCB0_MI1_SLOT4,
CONFIG_SCB0_MI1_SLOT5,
CONFIG_SCB0_MI1_SLOT6,
CONFIG_SCB0_MI1_SLOT7,
CONFIG_SCB0_MI1_SLOT8,
CONFIG_SCB0_MI1_SLOT9,
CONFIG_SCB0_MI1_SLOT10,
CONFIG_SCB0_MI1_SLOT11,
CONFIG_SCB0_MI1_SLOT12,
CONFIG_SCB0_MI1_SLOT13,
CONFIG_SCB0_MI1_SLOT14,
CONFIG_SCB0_MI1_SLOT15,
CONFIG_SCB0_MI1_SLOT16,
CONFIG_SCB0_MI1_SLOT17,
CONFIG_SCB0_MI1_SLOT18,
CONFIG_SCB0_MI1_SLOT19,
CONFIG_SCB0_MI1_SLOT20,
CONFIG_SCB0_MI1_SLOT21,
CONFIG_SCB0_MI1_SLOT22,
CONFIG_SCB0_MI1_SLOT23,
CONFIG_SCB0_MI1_SLOT24,
CONFIG_SCB0_MI1_SLOT25,
CONFIG_SCB0_MI1_SLOT26,
CONFIG_SCB0_MI1_SLOT27,
CONFIG_SCB0_MI1_SLOT28,
CONFIG_SCB0_MI1_SLOT29,
CONFIG_SCB0_MI1_SLOT30,
CONFIG_SCB0_MI1_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI2
{ REG_SCB0_ARBR2, REG_SCB0_ARBW2, 32, {
CONFIG_SCB0_MI2_SLOT0,
CONFIG_SCB0_MI2_SLOT1,
CONFIG_SCB0_MI2_SLOT2,
CONFIG_SCB0_MI2_SLOT3,
CONFIG_SCB0_MI2_SLOT4,
CONFIG_SCB0_MI2_SLOT5,
CONFIG_SCB0_MI2_SLOT6,
CONFIG_SCB0_MI2_SLOT7,
CONFIG_SCB0_MI2_SLOT8,
CONFIG_SCB0_MI2_SLOT9,
CONFIG_SCB0_MI2_SLOT10,
CONFIG_SCB0_MI2_SLOT11,
CONFIG_SCB0_MI2_SLOT12,
CONFIG_SCB0_MI2_SLOT13,
CONFIG_SCB0_MI2_SLOT14,
CONFIG_SCB0_MI2_SLOT15,
CONFIG_SCB0_MI2_SLOT16,
CONFIG_SCB0_MI2_SLOT17,
CONFIG_SCB0_MI2_SLOT18,
CONFIG_SCB0_MI2_SLOT19,
CONFIG_SCB0_MI2_SLOT20,
CONFIG_SCB0_MI2_SLOT21,
CONFIG_SCB0_MI2_SLOT22,
CONFIG_SCB0_MI2_SLOT23,
CONFIG_SCB0_MI2_SLOT24,
CONFIG_SCB0_MI2_SLOT25,
CONFIG_SCB0_MI2_SLOT26,
CONFIG_SCB0_MI2_SLOT27,
CONFIG_SCB0_MI2_SLOT28,
CONFIG_SCB0_MI2_SLOT29,
CONFIG_SCB0_MI2_SLOT30,
CONFIG_SCB0_MI2_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI3
{ REG_SCB0_ARBR3, REG_SCB0_ARBW3, 32, {
CONFIG_SCB0_MI3_SLOT0,
CONFIG_SCB0_MI3_SLOT1,
CONFIG_SCB0_MI3_SLOT2,
CONFIG_SCB0_MI3_SLOT3,
CONFIG_SCB0_MI3_SLOT4,
CONFIG_SCB0_MI3_SLOT5,
CONFIG_SCB0_MI3_SLOT6,
CONFIG_SCB0_MI3_SLOT7,
CONFIG_SCB0_MI3_SLOT8,
CONFIG_SCB0_MI3_SLOT9,
CONFIG_SCB0_MI3_SLOT10,
CONFIG_SCB0_MI3_SLOT11,
CONFIG_SCB0_MI3_SLOT12,
CONFIG_SCB0_MI3_SLOT13,
CONFIG_SCB0_MI3_SLOT14,
CONFIG_SCB0_MI3_SLOT15,
CONFIG_SCB0_MI3_SLOT16,
CONFIG_SCB0_MI3_SLOT17,
CONFIG_SCB0_MI3_SLOT18,
CONFIG_SCB0_MI3_SLOT19,
CONFIG_SCB0_MI3_SLOT20,
CONFIG_SCB0_MI3_SLOT21,
CONFIG_SCB0_MI3_SLOT22,
CONFIG_SCB0_MI3_SLOT23,
CONFIG_SCB0_MI3_SLOT24,
CONFIG_SCB0_MI3_SLOT25,
CONFIG_SCB0_MI3_SLOT26,
CONFIG_SCB0_MI3_SLOT27,
CONFIG_SCB0_MI3_SLOT28,
CONFIG_SCB0_MI3_SLOT29,
CONFIG_SCB0_MI3_SLOT30,
CONFIG_SCB0_MI3_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI4
{ REG_SCB0_ARBR4, REG_SCB4_ARBW0, 32, {
CONFIG_SCB0_MI4_SLOT0,
CONFIG_SCB0_MI4_SLOT1,
CONFIG_SCB0_MI4_SLOT2,
CONFIG_SCB0_MI4_SLOT3,
CONFIG_SCB0_MI4_SLOT4,
CONFIG_SCB0_MI4_SLOT5,
CONFIG_SCB0_MI4_SLOT6,
CONFIG_SCB0_MI4_SLOT7,
CONFIG_SCB0_MI4_SLOT8,
CONFIG_SCB0_MI4_SLOT9,
CONFIG_SCB0_MI4_SLOT10,
CONFIG_SCB0_MI4_SLOT11,
CONFIG_SCB0_MI4_SLOT12,
CONFIG_SCB0_MI4_SLOT13,
CONFIG_SCB0_MI4_SLOT14,
CONFIG_SCB0_MI4_SLOT15,
CONFIG_SCB0_MI4_SLOT16,
CONFIG_SCB0_MI4_SLOT17,
CONFIG_SCB0_MI4_SLOT18,
CONFIG_SCB0_MI4_SLOT19,
CONFIG_SCB0_MI4_SLOT20,
CONFIG_SCB0_MI4_SLOT21,
CONFIG_SCB0_MI4_SLOT22,
CONFIG_SCB0_MI4_SLOT23,
CONFIG_SCB0_MI4_SLOT24,
CONFIG_SCB0_MI4_SLOT25,
CONFIG_SCB0_MI4_SLOT26,
CONFIG_SCB0_MI4_SLOT27,
CONFIG_SCB0_MI4_SLOT28,
CONFIG_SCB0_MI4_SLOT29,
CONFIG_SCB0_MI4_SLOT30,
CONFIG_SCB0_MI4_SLOT31
},
},
#endif
#ifdef CONFIG_SCB0_MI5
{ REG_SCB0_ARBR5, REG_SCB0_ARBW5, 16, {
CONFIG_SCB0_MI5_SLOT0,
CONFIG_SCB0_MI5_SLOT1,
CONFIG_SCB0_MI5_SLOT2,
CONFIG_SCB0_MI5_SLOT3,
CONFIG_SCB0_MI5_SLOT4,
CONFIG_SCB0_MI5_SLOT5,
CONFIG_SCB0_MI5_SLOT6,
CONFIG_SCB0_MI5_SLOT7,
CONFIG_SCB0_MI5_SLOT8,
CONFIG_SCB0_MI5_SLOT9,
CONFIG_SCB0_MI5_SLOT10,
CONFIG_SCB0_MI5_SLOT11,
CONFIG_SCB0_MI5_SLOT12,
CONFIG_SCB0_MI5_SLOT13,
CONFIG_SCB0_MI5_SLOT14,
CONFIG_SCB0_MI5_SLOT15,
},
},
#endif
/*
{ REG_SCB1_ARBR0, REG_SCB1_ARBW0, scb1_mi0, 20 },
{ REG_SCB2_ARBR0, REG_SCB2_ARBW0, scb2_mi0, 10 },
{ REG_SCB3_ARBR0, REG_SCB3_ARBW0, scb3_mi0, 16 },
{ REG_SCB4_ARBR0, REG_SCB4_ARBW0, scb4_mi0, 16 },
{ REG_SCB5_ARBR0, REG_SCB5_ARBW0, scb5_mi0, 8 },
{ REG_SCB6_ARBR0, REG_SCB6_ARBW0, scb6_mi0, 4 },
{ REG_SCB7_ARBR0, REG_SCB7_ARBW0, scb7_mi0, 6 },
{ REG_SCB8_ARBR0, REG_SCB8_ARBW0, scb8_mi0, 8 },
{ REG_SCB9_ARBR0, REG_SCB9_ARBW0, scb9_mi0, 10 },
{ REG_SCB10_ARBR0, REG_SCB10_ARBW0, scb20_mi0, 16 },
*/
{ 0, }
};
...@@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o ...@@ -10,6 +10,7 @@ obj-$(CONFIG_PM) += pm.o
ifneq ($(CONFIG_BF60x),y) ifneq ($(CONFIG_BF60x),y)
obj-$(CONFIG_PM) += dpmc_modes.o obj-$(CONFIG_PM) += dpmc_modes.o
endif endif
obj-$(CONFIG_SCB_PRIORITY) += scb-init.o
obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o obj-$(CONFIG_CPU_VOLTAGE) += dpmc.o
obj-$(CONFIG_SMP) += smp.o obj-$(CONFIG_SMP) += smp.o
obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o obj-$(CONFIG_BFIN_KERNEL_CLOCK) += clocks-init.o
/*
* arch/blackfin/mach-common/scb-init.c - reprogram system cross bar priority
*
* Copyright 2012 Analog Devices Inc.
*
* Licensed under the GPL-2 or later.
*/
#include <linux/init.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <asm/scb.h>
__attribute__((l1_text))
inline void scb_mi_write(unsigned long scb_mi_arbw, unsigned int slots,
unsigned char *scb_mi_prio)
{
unsigned int i;
for (i = 0; i < slots; ++i)
bfin_write32(scb_mi_arbw, (i << SCB_SLOT_OFFSET) | scb_mi_prio[i]);
}
__attribute__((l1_text))
inline void scb_mi_read(unsigned long scb_mi_arbw, unsigned int slots,
unsigned char *scb_mi_prio)
{
unsigned int i;
for (i = 0; i < slots; ++i) {
bfin_write32(scb_mi_arbw, (0xFF << SCB_SLOT_OFFSET) | i);
scb_mi_prio[i] = bfin_read32(scb_mi_arbw);
}
}
__attribute__((l1_text))
void init_scb(void)
{
unsigned int i, j;
unsigned char scb_tmp_prio[32];
pr_info("Init System Crossbar\n");
for (i = 0; scb_data[i].scb_mi_arbr > 0; ++i) {
scb_mi_write(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_data[i].scb_mi_prio);
pr_debug("scb priority at 0x%lx:\n", scb_data[i].scb_mi_arbr);
scb_mi_read(scb_data[i].scb_mi_arbw, scb_data[i].scb_mi_slots, scb_tmp_prio);
for (j = 0; j < scb_data[i].scb_mi_slots; ++j)
pr_debug("slot %d = %d\n", j, scb_tmp_prio[j]);
}
}
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