Commit 24ed45aa authored by Tony Lindgren's avatar Tony Lindgren

Merge branch 'for_2_6_33' of git://git.pwsan.com/linux-2.6 into omap-for-linus

parents aa2cf420 911bd739
...@@ -3,7 +3,8 @@ ...@@ -3,7 +3,8 @@
# #
# Common support # Common support
obj-y := io.o id.o sram.o clock.o irq.o mux.o serial.o devices.o obj-y := io.o id.o sram.o irq.o mux.o serial.o devices.o
obj-y += clock.o clock_data.o opp_data.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
......
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...@@ -18,7 +18,8 @@ ...@@ -18,7 +18,8 @@
#include <plat/mux.h> #include <plat/mux.h>
#include <plat/tc.h> #include <plat/tc.h>
extern int omap1_clk_init(void); #include "clock.h"
extern void omap_check_revision(void); extern void omap_check_revision(void);
extern void omap_sram_init(void); extern void omap_sram_init(void);
extern void omapfb_reserve_sdram(void); extern void omapfb_reserve_sdram(void);
......
/*
* linux/arch/arm/mach-omap1/opp.h
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ARCH_ARM_MACH_OMAP1_OPP_H
#define __ARCH_ARM_MACH_OMAP1_OPP_H
#include <linux/types.h>
struct mpu_rate {
unsigned long rate;
unsigned long xtal;
unsigned long pll_rate;
__u16 ckctl_val;
__u16 dpllctl_val;
};
extern struct mpu_rate omap1_rate_table[];
#endif
/*
* linux/arch/arm/mach-omap1/opp_data.c
*
* Copyright (C) 2004 - 2005 Nokia corporation
* Written by Tuukka Tikkanen <tuukka.tikkanen@elektrobit.com>
* Based on clocks.h by Tony Lindgren, Gordon McNutt and RidgeRun, Inc
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include "opp.h"
/*-------------------------------------------------------------------------
* Omap1 MPU rate table
*-------------------------------------------------------------------------*/
struct mpu_rate omap1_rate_table[] = {
/* MPU MHz, xtal MHz, dpll1 MHz, CKCTL, DPLL_CTL
* NOTE: Comment order here is different from bits in CKCTL value:
* armdiv, dspdiv, dspmmu, tcdiv, perdiv, lcddiv
*/
#if defined(CONFIG_OMAP_ARM_216MHZ)
{ 216000000, 12000000, 216000000, 0x050d, 0x2910 }, /* 1/1/2/2/2/8 */
#endif
#if defined(CONFIG_OMAP_ARM_195MHZ)
{ 195000000, 13000000, 195000000, 0x050e, 0x2790 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_192MHZ)
{ 192000000, 19200000, 192000000, 0x050f, 0x2510 }, /* 1/1/2/2/8/8 */
{ 192000000, 12000000, 192000000, 0x050f, 0x2810 }, /* 1/1/2/2/8/8 */
{ 96000000, 12000000, 192000000, 0x055f, 0x2810 }, /* 2/2/2/2/8/8 */
{ 48000000, 12000000, 192000000, 0x0baf, 0x2810 }, /* 4/4/4/8/8/8 */
{ 24000000, 12000000, 192000000, 0x0fff, 0x2810 }, /* 8/8/8/8/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_182MHZ)
{ 182000000, 13000000, 182000000, 0x050e, 0x2710 }, /* 1/1/2/2/4/8 */
#endif
#if defined(CONFIG_OMAP_ARM_168MHZ)
{ 168000000, 12000000, 168000000, 0x010f, 0x2710 }, /* 1/1/1/2/8/8 */
#endif
#if defined(CONFIG_OMAP_ARM_150MHZ)
{ 150000000, 12000000, 150000000, 0x010a, 0x2cb0 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_120MHZ)
{ 120000000, 12000000, 120000000, 0x010a, 0x2510 }, /* 1/1/1/2/4/4 */
#endif
#if defined(CONFIG_OMAP_ARM_96MHZ)
{ 96000000, 12000000, 96000000, 0x0005, 0x2410 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_60MHZ)
{ 60000000, 12000000, 60000000, 0x0005, 0x2290 }, /* 1/1/1/1/2/2 */
#endif
#if defined(CONFIG_OMAP_ARM_30MHZ)
{ 30000000, 12000000, 60000000, 0x0555, 0x2290 }, /* 2/2/2/2/2/2 */
#endif
{ 0, 0, 0, 0, 0 },
};
...@@ -128,3 +128,15 @@ config OMAP3_EMU ...@@ -128,3 +128,15 @@ config OMAP3_EMU
help help
Say Y here to enable debugging hardware of omap3 Say Y here to enable debugging hardware of omap3
config OMAP3_SDRC_AC_TIMING
bool "Enable SDRC AC timing register changes"
depends on ARCH_OMAP3 && ARCH_OMAP34XX
default n
help
If you know that none of your system initiators will attempt to
access SDRAM during CORE DVFS, select Y here. This should boost
SDRAM performance at lower CORE OPPs. There are relatively few
users who will wish to say yes at this point - almost everyone will
wish to say no. Selecting yes without understanding what is
going on could result in system crashes;
...@@ -6,11 +6,14 @@ ...@@ -6,11 +6,14 @@
obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o obj-y := id.o io.o control.o mux.o devices.o serial.o gpmc.o timer-gp.o
omap-2-3-common = irq.o sdrc.o omap_hwmod.o omap-2-3-common = irq.o sdrc.o omap_hwmod.o
omap-3-4-common = dpll.o
prcm-common = prcm.o powerdomain.o prcm-common = prcm.o powerdomain.o
clock-common = clock.o clockdomain.o clock-common = clock.o clock_common_data.o clockdomain.o
obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common) obj-$(CONFIG_ARCH_OMAP2) += $(omap-2-3-common) $(prcm-common) $(clock-common)
obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) obj-$(CONFIG_ARCH_OMAP3) += $(omap-2-3-common) $(prcm-common) $(clock-common) \
$(omap-3-4-common)
obj-$(CONFIG_ARCH_OMAP4) += $(omap-3-4-common) prcm.o clock.o
obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o obj-$(CONFIG_OMAP_MCBSP) += mcbsp.o
...@@ -41,8 +44,11 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o ...@@ -41,8 +44,11 @@ obj-$(CONFIG_ARCH_OMAP3) += cm.o
obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o obj-$(CONFIG_ARCH_OMAP4) += cm4xxx.o
# Clock framework # Clock framework
obj-$(CONFIG_ARCH_OMAP2) += clock24xx.o obj-$(CONFIG_ARCH_OMAP2) += clock2xxx.o clock2xxx_data.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o obj-$(CONFIG_ARCH_OMAP2420) += opp2420_data.o
obj-$(CONFIG_ARCH_OMAP3) += clock34xx.o clock34xx_data.o
obj-$(CONFIG_ARCH_OMAP2430) += opp2430_data.o
obj-$(CONFIG_ARCH_OMAP4) += clock44xx.o clock44xx_data.o
# EMU peripherals # EMU peripherals
obj-$(CONFIG_OMAP3_EMU) += emu.o obj-$(CONFIG_OMAP3_EMU) += emu.o
......
...@@ -70,9 +70,41 @@ ...@@ -70,9 +70,41 @@
u8 cpu_mask; u8 cpu_mask;
/*------------------------------------------------------------------------- /*-------------------------------------------------------------------------
* OMAP2/3 specific clock functions * OMAP2/3/4 specific clock functions
*-------------------------------------------------------------------------*/ *-------------------------------------------------------------------------*/
void omap2_init_dpll_parent(struct clk *clk)
{
u32 v;
struct dpll_data *dd;
dd = clk->dpll_data;
if (!dd)
return;
/* Return bypass rate if DPLL is bypassed */
v = __raw_readl(dd->control_reg);
v &= dd->enable_mask;
v >>= __ffs(dd->enable_mask);
/* Reparent in case the dpll is in bypass */
if (cpu_is_omap24xx()) {
if (v == OMAP2XXX_EN_DPLL_LPBYPASS ||
v == OMAP2XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
} else if (cpu_is_omap34xx()) {
if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS)
clk_reparent(clk, dd->clk_bypass);
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
clk_reparent(clk, dd->clk_bypass);
}
return;
}
/** /**
* _omap2xxx_clk_commit - commit clock parent/rate changes in hardware * _omap2xxx_clk_commit - commit clock parent/rate changes in hardware
* @clk: struct clk * * @clk: struct clk *
...@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n) ...@@ -149,6 +181,7 @@ static int _dpll_test_fint(struct clk *clk, u8 n)
* clockdomain pointer, and save it into the struct clk. Intended to be * clockdomain pointer, and save it into the struct clk. Intended to be
* called during clk_register(). No return value. * called during clk_register(). No return value.
*/ */
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
void omap2_init_clk_clkdm(struct clk *clk) void omap2_init_clk_clkdm(struct clk *clk)
{ {
struct clockdomain *clkdm; struct clockdomain *clkdm;
...@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk) ...@@ -166,6 +199,7 @@ void omap2_init_clk_clkdm(struct clk *clk)
"clkdm %s\n", clk->name, clk->clkdm_name); "clkdm %s\n", clk->name, clk->clkdm_name);
} }
} }
#endif
/** /**
* omap2_init_clksel_parent - set a clksel clk's parent field from the hardware * omap2_init_clksel_parent - set a clksel clk's parent field from the hardware
...@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk) ...@@ -247,6 +281,11 @@ u32 omap2_get_dpll_rate(struct clk *clk)
if (v == OMAP3XXX_EN_DPLL_LPBYPASS || if (v == OMAP3XXX_EN_DPLL_LPBYPASS ||
v == OMAP3XXX_EN_DPLL_FRBYPASS) v == OMAP3XXX_EN_DPLL_FRBYPASS)
return dd->clk_bypass->rate; return dd->clk_bypass->rate;
} else if (cpu_is_omap44xx()) {
if (v == OMAP4XXX_EN_DPLL_LPBYPASS ||
v == OMAP4XXX_EN_DPLL_FRBYPASS ||
v == OMAP4XXX_EN_DPLL_MNBYPASS)
return dd->clk_bypass->rate;
} }
v = __raw_readl(dd->mult_div1_reg); v = __raw_readl(dd->mult_div1_reg);
...@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk) ...@@ -437,8 +476,10 @@ void omap2_clk_disable(struct clk *clk)
_omap2_clk_disable(clk); _omap2_clk_disable(clk);
if (clk->parent) if (clk->parent)
omap2_clk_disable(clk->parent); omap2_clk_disable(clk->parent);
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm) if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk); omap2_clkdm_clk_disable(clk->clkdm, clk);
#endif
} }
} }
...@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk) ...@@ -448,8 +489,10 @@ int omap2_clk_enable(struct clk *clk)
int ret = 0; int ret = 0;
if (clk->usecount++ == 0) { if (clk->usecount++ == 0) {
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm) if (clk->clkdm)
omap2_clkdm_clk_enable(clk->clkdm, clk); omap2_clkdm_clk_enable(clk->clkdm, clk);
#endif
if (clk->parent) { if (clk->parent) {
ret = omap2_clk_enable(clk->parent); ret = omap2_clk_enable(clk->parent);
...@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk) ...@@ -468,8 +511,10 @@ int omap2_clk_enable(struct clk *clk)
return ret; return ret;
err: err:
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdm f/w is in place */
if (clk->clkdm) if (clk->clkdm)
omap2_clkdm_clk_disable(clk->clkdm, clk); omap2_clkdm_clk_disable(clk->clkdm, clk);
#endif
clk->usecount--; clk->usecount--;
return ret; return ret;
} }
......
/* /*
* linux/arch/arm/mach-omap2/clock.h * linux/arch/arm/mach-omap2/clock.h
* *
* Copyright (C) 2005-2008 Texas Instruments, Inc. * Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2008 Nokia Corporation * Copyright (C) 2004-2009 Nokia Corporation
* *
* Contacts: * Contacts:
* Richard Woodruff <r-woodruff2@ti.com> * Richard Woodruff <r-woodruff2@ti.com>
...@@ -36,6 +36,17 @@ ...@@ -36,6 +36,17 @@
#define OMAP3XXX_EN_DPLL_FRBYPASS 0x6 #define OMAP3XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP3XXX_EN_DPLL_LOCKED 0x7 #define OMAP3XXX_EN_DPLL_LOCKED 0x7
/* OMAP4xxx CM_CLKMODE_DPLL*.EN_*_DPLL bits - for omap2_get_dpll_rate() */
#define OMAP4XXX_EN_DPLL_MNBYPASS 0x4
#define OMAP4XXX_EN_DPLL_LPBYPASS 0x5
#define OMAP4XXX_EN_DPLL_FRBYPASS 0x6
#define OMAP4XXX_EN_DPLL_LOCKED 0x7
/* CM_CLKEN_PLL*.EN* bit values - not all are available for every DPLL */
#define DPLL_LOW_POWER_STOP 0x1
#define DPLL_LOW_POWER_BYPASS 0x5
#define DPLL_LOCKED 0x7
int omap2_clk_init(void); int omap2_clk_init(void);
int omap2_clk_enable(struct clk *clk); int omap2_clk_enable(struct clk *clk);
void omap2_clk_disable(struct clk *clk); void omap2_clk_disable(struct clk *clk);
...@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate); ...@@ -44,6 +55,14 @@ int omap2_clk_set_rate(struct clk *clk, unsigned long rate);
int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent); int omap2_clk_set_parent(struct clk *clk, struct clk *new_parent);
int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance); int omap2_dpll_set_rate_tolerance(struct clk *clk, unsigned int tolerance);
long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate); long omap2_dpll_round_rate(struct clk *clk, unsigned long target_rate);
unsigned long omap3_dpll_recalc(struct clk *clk);
unsigned long omap3_clkoutx2_recalc(struct clk *clk);
void omap3_dpll_allow_idle(struct clk *clk);
void omap3_dpll_deny_idle(struct clk *clk);
u32 omap3_dpll_autoidle_read(struct clk *clk);
int omap3_noncore_dpll_set_rate(struct clk *clk, unsigned long rate);
int omap3_noncore_dpll_enable(struct clk *clk);
void omap3_noncore_dpll_disable(struct clk *clk);
#ifdef CONFIG_OMAP_RESET_CLOCKS #ifdef CONFIG_OMAP_RESET_CLOCKS
void omap2_clk_disable_unused(struct clk *clk); void omap2_clk_disable_unused(struct clk *clk);
...@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk); ...@@ -63,6 +82,7 @@ unsigned long omap2_fixed_divisor_recalc(struct clk *clk);
long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate); long omap2_clksel_round_rate(struct clk *clk, unsigned long target_rate);
int omap2_clksel_set_rate(struct clk *clk, unsigned long rate); int omap2_clksel_set_rate(struct clk *clk, unsigned long rate);
u32 omap2_get_dpll_rate(struct clk *clk); u32 omap2_get_dpll_rate(struct clk *clk);
void omap2_init_dpll_parent(struct clk *clk);
int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name); int omap2_wait_clock_ready(void __iomem *reg, u32 cval, const char *name);
void omap2_clk_prepare_for_reboot(void); void omap2_clk_prepare_for_reboot(void);
int omap2_dflt_clk_enable(struct clk *clk); int omap2_dflt_clk_enable(struct clk *clk);
...@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg, ...@@ -72,29 +92,17 @@ void omap2_clk_dflt_find_companion(struct clk *clk, void __iomem **other_reg,
void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg, void omap2_clk_dflt_find_idlest(struct clk *clk, void __iomem **idlest_reg,
u8 *idlest_bit); u8 *idlest_bit);
extern u8 cpu_mask;
extern const struct clkops clkops_omap2_dflt_wait; extern const struct clkops clkops_omap2_dflt_wait;
extern const struct clkops clkops_omap2_dflt; extern const struct clkops clkops_omap2_dflt;
extern u8 cpu_mask; extern struct clk_functions omap2_clk_functions;
extern struct clk *vclk, *sclk;
/* clksel_rate data common to 24xx/343x */ extern const struct clksel_rate gpt_32k_rates[];
static const struct clksel_rate gpt_32k_rates[] = { extern const struct clksel_rate gpt_sys_rates[];
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE }, extern const struct clksel_rate gfx_l3_rates[];
{ .div = 0 }
};
static const struct clksel_rate gpt_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
static const struct clksel_rate gfx_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 0 }
};
#endif #endif
/*
* OMAP2 clock function prototypes and macros
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_24XX_H
unsigned long omap2_table_mpu_recalc(struct clk *clk);
int omap2_select_table_rate(struct clk *clk, unsigned long rate);
long omap2_round_to_table_rate(struct clk *clk, unsigned long rate);
unsigned long omap2_sys_clk_recalc(struct clk *clk);
unsigned long omap2_osc_clk_recalc(struct clk *clk);
unsigned long omap2_sys_clk_recalc(struct clk *clk);
unsigned long omap2_dpllcore_recalc(struct clk *clk);
int omap2_reprogram_dpllcore(struct clk *clk, unsigned long rate);
unsigned long omap2xxx_clk_get_core_rate(struct clk *clk);
/* REVISIT: These should be set dynamically for CONFIG_MULTI_OMAP2 */
#ifdef CONFIG_ARCH_OMAP2420
#define OMAP_CM_REGADDR OMAP2420_CM_REGADDR
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2420_PRCM_CLKOUT_CTRL
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2420_PRCM_CLKEMUL_CTRL
#else
#define OMAP_CM_REGADDR OMAP2430_CM_REGADDR
#define OMAP24XX_PRCM_CLKOUT_CTRL OMAP2430_PRCM_CLKOUT_CTRL
#define OMAP24XX_PRCM_CLKEMUL_CTRL OMAP2430_PRCM_CLKEMUL_CTRL
#endif
extern void __iomem *prcm_clksrc_ctrl;
extern struct clk *dclk;
extern const struct clkops clkops_omap2430_i2chs_wait;
extern const struct clkops clkops_oscck;
extern const struct clkops clkops_apll96;
extern const struct clkops clkops_apll54;
#endif
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/*
* OMAP4-specific clock framework functions
*
* Copyright (C) 2009 Texas Instruments, Inc.
*
* Rajendra Nayak (rnayak@ti.com)
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/errno.h>
#include "clock.h"
struct clk_functions omap2_clk_functions = {
.clk_enable = omap2_clk_enable,
.clk_disable = omap2_clk_disable,
.clk_round_rate = omap2_clk_round_rate,
.clk_set_rate = omap2_clk_set_rate,
.clk_set_parent = omap2_clk_set_parent,
.clk_disable_unused = omap2_clk_disable_unused,
};
const struct clkops clkops_noncore_dpll_ops = {
.enable = &omap3_noncore_dpll_enable,
.disable = &omap3_noncore_dpll_disable,
};
void omap2_clk_prepare_for_reboot(void)
{
return;
}
/*
* OMAP4 clock function prototypes and macros
*
* Copyright (C) 2009 Texas Instruments, Inc.
*/
#ifndef __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
#define __ARCH_ARM_MACH_OMAP2_CLOCK_44XX_H
#define OMAP4430_MAX_DPLL_MULT 2048
#define OMAP4430_MAX_DPLL_DIV 128
extern const struct clkops clkops_noncore_dpll_ops;
#endif
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/*
* linux/arch/arm/mach-omap2/clock_common_data.c
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Contacts:
* Richard Woodruff <r-woodruff2@ti.com>
* Paul Walmsley
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This file contains clock data that is common to both the OMAP2xxx and
* OMAP3xxx clock definition files.
*/
#include "clock.h"
/* clksel_rate data common to 24xx/343x */
const struct clksel_rate gpt_32k_rates[] = {
{ .div = 1, .val = 0, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
const struct clksel_rate gpt_sys_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 0 }
};
const struct clksel_rate gfx_l3_rates[] = {
{ .div = 1, .val = 1, .flags = RATE_IN_24XX | RATE_IN_343X },
{ .div = 2, .val = 2, .flags = RATE_IN_24XX | RATE_IN_343X | DEFAULT_RATE },
{ .div = 3, .val = 3, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 4, .val = 4, .flags = RATE_IN_243X | RATE_IN_343X },
{ .div = 0 }
};
...@@ -2,7 +2,7 @@ ...@@ -2,7 +2,7 @@
* OMAP2/3 clockdomain framework functions * OMAP2/3 clockdomain framework functions
* *
* Copyright (C) 2008 Texas Instruments, Inc. * Copyright (C) 2008 Texas Instruments, Inc.
* Copyright (C) 2008 Nokia Corporation * Copyright (C) 2008-2009 Nokia Corporation
* *
* Written by Paul Walmsley and Jouni Högander * Written by Paul Walmsley and Jouni Högander
* *
...@@ -10,9 +10,7 @@ ...@@ -10,9 +10,7 @@
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifdef CONFIG_OMAP_DEBUG_CLOCKDOMAIN #undef DEBUG
# define DEBUG
#endif
#include <linux/module.h> #include <linux/module.h>
#include <linux/kernel.h> #include <linux/kernel.h>
......
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...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
#include <asm/atomic.h> #include <asm/atomic.h>
#include <plat/common.h>
#include "cm.h" #include "cm.h"
#include "cm-regbits-24xx.h" #include "cm-regbits-24xx.h"
#include "cm-regbits-34xx.h" #include "cm-regbits-34xx.h"
...@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift) ...@@ -61,9 +63,8 @@ int omap2_cm_wait_module_ready(s16 prcm_mod, u8 idlest_id, u8 idlest_shift)
mask = 1 << idlest_shift; mask = 1 << idlest_shift;
/* XXX should be OMAP2 CM */ /* XXX should be OMAP2 CM */
while (((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) != ena) && omap_test_timeout(((cm_read_mod_reg(prcm_mod, cm_idlest_reg) & mask) == ena),
(i++ < MAX_MODULE_READY_TIME)) MAX_MODULE_READY_TIME, i);
udelay(1);
return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY; return (i < MAX_MODULE_READY_TIME) ? 0 : -EBUSY;
} }
......
...@@ -4,8 +4,8 @@ ...@@ -4,8 +4,8 @@
/* /*
* OMAP2/3 Clock Management (CM) register definitions * OMAP2/3 Clock Management (CM) register definitions
* *
* Copyright (C) 2007-2008 Texas Instruments, Inc. * Copyright (C) 2007-2009 Texas Instruments, Inc.
* Copyright (C) 2007-2008 Nokia Corporation * Copyright (C) 2007-2009 Nokia Corporation
* *
* Written by Paul Walmsley * Written by Paul Walmsley
* *
...@@ -22,6 +22,12 @@ ...@@ -22,6 +22,12 @@
OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg)) OMAP2_L4_IO_ADDRESS(OMAP2430_CM_BASE + (module) + (reg))
#define OMAP34XX_CM_REGADDR(module, reg) \ #define OMAP34XX_CM_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg)) OMAP2_L4_IO_ADDRESS(OMAP3430_CM_BASE + (module) + (reg))
#define OMAP44XX_CM1_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_CM1_BASE + (module) + (reg))
#define OMAP44XX_CM2_REGADDR(module, reg) \
OMAP2_L4_IO_ADDRESS(OMAP4430_CM2_BASE + (module) + (reg))
#include "cm44xx.h"
/* /*
* Architecture-specific global CM registers * Architecture-specific global CM registers
...@@ -89,6 +95,11 @@ ...@@ -89,6 +95,11 @@
#define OMAP3430_CM_CLKSEL2_EMU 0x0050 #define OMAP3430_CM_CLKSEL2_EMU 0x0050
#define OMAP3430_CM_CLKSEL3_EMU 0x0054 #define OMAP3430_CM_CLKSEL3_EMU 0x0054
/* CM2.CEFUSE_CM2 register offsets */
/* OMAP4 modulemode control */
#define OMAP4430_MODULEMODE_HWCTRL 0
#define OMAP4430_MODULEMODE_SWCTRL 1
/* Clock management domain register get/set */ /* Clock management domain register get/set */
......
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...@@ -517,7 +517,7 @@ void __init gpmc_init(void) ...@@ -517,7 +517,7 @@ void __init gpmc_init(void)
ck = "gpmc_fck"; ck = "gpmc_fck";
l = OMAP34XX_GPMC_BASE; l = OMAP34XX_GPMC_BASE;
} else if (cpu_is_omap44xx()) { } else if (cpu_is_omap44xx()) {
ck = "gpmc_fck"; ck = "gpmc_ck";
l = OMAP44XX_GPMC_BASE; l = OMAP44XX_GPMC_BASE;
} }
......
...@@ -35,7 +35,6 @@ ...@@ -35,7 +35,6 @@
#include <plat/serial.h> #include <plat/serial.h>
#include <plat/vram.h> #include <plat/vram.h>
#ifndef CONFIG_ARCH_OMAP4 /* FIXME: Remove this once clkdev is ready */
#include "clock.h" #include "clock.h"
#include <plat/omap-pm.h> #include <plat/omap-pm.h>
...@@ -44,7 +43,6 @@ ...@@ -44,7 +43,6 @@
#include <plat/clockdomain.h> #include <plat/clockdomain.h>
#include "clockdomains.h" #include "clockdomains.h"
#endif
#include <plat/omap_hwmod.h> #include <plat/omap_hwmod.h>
#include "omap_hwmod_2420.h" #include "omap_hwmod_2420.h"
#include "omap_hwmod_2430.h" #include "omap_hwmod_2430.h"
...@@ -321,8 +319,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0, ...@@ -321,8 +319,8 @@ void __init omap2_init_common_hw(struct omap_sdrc_params *sdrc_cs0,
omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps); omap_pm_if_early_init(mpu_opps, dsp_opps, l3_opps);
pwrdm_init(powerdomains_omap); pwrdm_init(powerdomains_omap);
clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps); clkdm_init(clockdomains_omap, clkdm_pwrdm_autodeps);
omap2_clk_init();
#endif #endif
omap2_clk_init();
omap_serial_early_init(); omap_serial_early_init();
#ifndef CONFIG_ARCH_OMAP4 #ifndef CONFIG_ARCH_OMAP4
omap_hwmod_late_init(); omap_hwmod_late_init();
......
...@@ -45,6 +45,7 @@ ...@@ -45,6 +45,7 @@
#include <linux/mutex.h> #include <linux/mutex.h>
#include <linux/bootmem.h> #include <linux/bootmem.h>
#include <plat/common.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/clockdomain.h> #include <plat/clockdomain.h>
#include <plat/powerdomain.h> #include <plat/powerdomain.h>
...@@ -209,6 +210,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v) ...@@ -209,6 +210,32 @@ static int _set_softreset(struct omap_hwmod *oh, u32 *v)
return 0; return 0;
} }
/**
* _set_module_autoidle: set the OCP_SYSCONFIG AUTOIDLE field in @v
* @oh: struct omap_hwmod *
* @autoidle: desired AUTOIDLE bitfield value (0 or 1)
* @v: pointer to register contents to modify
*
* Update the module autoidle bit in @v to be @autoidle for the @oh
* hwmod. The autoidle bit controls whether the module can gate
* internal clocks automatically when it isn't doing anything; the
* exact function of this bit varies on a per-module basis. This
* function does not write to the hardware. Returns -EINVAL upon
* error or 0 upon success.
*/
static int _set_module_autoidle(struct omap_hwmod *oh, u8 autoidle,
u32 *v)
{
if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE))
return -EINVAL;
*v &= ~SYSC_AUTOIDLE_MASK;
*v |= autoidle << SYSC_AUTOIDLE_SHIFT;
return 0;
}
/** /**
* _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware * _enable_wakeup: set OCP_SYSCONFIG.ENAWAKEUP bit in the hardware
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
...@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh) ...@@ -326,6 +353,9 @@ static int _init_main_clk(struct omap_hwmod *oh)
ret = -EINVAL; ret = -EINVAL;
oh->_clk = c; oh->_clk = c;
WARN(!c->clkdm, "omap_hwmod: %s: missing clockdomain for %s.\n",
oh->clkdev_con_id, c->name);
return ret; return ret;
} }
...@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh) ...@@ -557,8 +587,19 @@ static void _sysc_enable(struct omap_hwmod *oh)
_set_master_standbymode(oh, idlemode, &v); _set_master_standbymode(oh, idlemode, &v);
} }
/* XXX OCP AUTOIDLE bit? */ if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE) {
idlemode = (oh->flags & HWMOD_NO_OCP_AUTOIDLE) ?
0 : 1;
_set_module_autoidle(oh, idlemode, &v);
}
/* XXX OCP ENAWAKEUP bit? */
/*
* XXX The clock framework should handle this, by
* calling into this code. But this must wait until the
* clock structures are tagged with omap_hwmod entries
*/
if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT && if (oh->flags & HWMOD_SET_DEFAULT_CLOCKACT &&
oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY) oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY)
_set_clockactivity(oh, oh->sysconfig->clockact, &v); _set_clockactivity(oh, oh->sysconfig->clockact, &v);
...@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh) ...@@ -622,7 +663,8 @@ static void _sysc_shutdown(struct omap_hwmod *oh)
if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE) if (oh->sysconfig->sysc_flags & SYSC_HAS_MIDLEMODE)
_set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v); _set_master_standbymode(oh, HWMOD_IDLEMODE_FORCE, &v);
/* XXX clear OCP AUTOIDLE bit? */ if (oh->sysconfig->sysc_flags & SYSC_HAS_AUTOIDLE)
_set_module_autoidle(oh, 1, &v);
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
} }
...@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh) ...@@ -736,7 +778,7 @@ static int _wait_target_ready(struct omap_hwmod *oh)
static int _reset(struct omap_hwmod *oh) static int _reset(struct omap_hwmod *oh)
{ {
u32 r, v; u32 r, v;
int c; int c = 0;
if (!oh->sysconfig || if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) || !(oh->sysconfig->sysc_flags & SYSC_HAS_SOFTRESET) ||
...@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh) ...@@ -758,13 +800,9 @@ static int _reset(struct omap_hwmod *oh)
return r; return r;
_write_sysconfig(v, oh); _write_sysconfig(v, oh);
c = 0; omap_test_timeout((omap_hwmod_readl(oh, oh->sysconfig->syss_offs) &
while (c < MAX_MODULE_RESET_WAIT && SYSS_RESETDONE_MASK),
!(omap_hwmod_readl(oh, oh->sysconfig->syss_offs) & MAX_MODULE_RESET_WAIT, c);
SYSS_RESETDONE_MASK)) {
udelay(1);
c++;
}
if (c == MAX_MODULE_RESET_WAIT) if (c == MAX_MODULE_RESET_WAIT)
WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n", WARN(1, "omap_hwmod: %s: failed to reset in %d usec\n",
...@@ -883,33 +921,6 @@ static int _shutdown(struct omap_hwmod *oh) ...@@ -883,33 +921,6 @@ static int _shutdown(struct omap_hwmod *oh)
return 0; return 0;
} }
/**
* _write_clockact_lock - set the module's clockactivity bits
* @oh: struct omap_hwmod *
* @clockact: CLOCKACTIVITY field bits
*
* Writes the CLOCKACTIVITY bits @clockact to the hwmod @oh
* OCP_SYSCONFIG register. Returns -EINVAL if the hwmod is in the
* wrong state or returns 0.
*/
static int _write_clockact_lock(struct omap_hwmod *oh, u8 clockact)
{
u32 v;
if (!oh->sysconfig ||
!(oh->sysconfig->sysc_flags & SYSC_HAS_CLOCKACTIVITY))
return -EINVAL;
mutex_lock(&omap_hwmod_mutex);
v = oh->_sysc_cache;
_set_clockactivity(oh, clockact, &v);
_write_sysconfig(v, oh);
mutex_unlock(&omap_hwmod_mutex);
return 0;
}
/** /**
* _setup - do initial configuration of omap_hwmod * _setup - do initial configuration of omap_hwmod
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
...@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh) ...@@ -948,11 +959,19 @@ static int _setup(struct omap_hwmod *oh)
_enable(oh); _enable(oh);
if (!(oh->flags & HWMOD_INIT_NO_RESET)) if (!(oh->flags & HWMOD_INIT_NO_RESET)) {
_reset(oh); /*
* XXX Do the OCP_SYSCONFIG bits need to be
/* XXX OCP AUTOIDLE bit? */ * reprogrammed after a reset? If not, then this can
/* XXX OCP ENAWAKEUP bit? */ * be removed. If they do, then probably the
* _enable() function should be split to avoid the
* rewrite of the OCP_SYSCONFIG register.
*/
if (oh->sysconfig) {
_update_sysc_cache(oh);
_sysc_enable(oh);
}
}
if (!(oh->flags & HWMOD_INIT_NO_IDLE)) if (!(oh->flags & HWMOD_INIT_NO_IDLE))
_idle(oh); _idle(oh);
...@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res) ...@@ -1348,8 +1367,9 @@ int omap_hwmod_fill_resources(struct omap_hwmod *oh, struct resource *res)
/* For each IRQ, DMA, memory area, fill in array.*/ /* For each IRQ, DMA, memory area, fill in array.*/
for (i = 0; i < oh->mpu_irqs_cnt; i++) { for (i = 0; i < oh->mpu_irqs_cnt; i++) {
(res + r)->start = *(oh->mpu_irqs + i); (res + r)->name = (oh->mpu_irqs + i)->name;
(res + r)->end = *(oh->mpu_irqs + i); (res + r)->start = (oh->mpu_irqs + i)->irq;
(res + r)->end = (oh->mpu_irqs + i)->irq;
(res + r)->flags = IORESOURCE_IRQ; (res + r)->flags = IORESOURCE_IRQ;
r++; r++;
} }
...@@ -1453,62 +1473,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh, ...@@ -1453,62 +1473,6 @@ int omap_hwmod_del_initiator_dep(struct omap_hwmod *oh,
return _del_initiator_dep(oh, init_oh); return _del_initiator_dep(oh, init_oh);
} }
/**
* omap_hwmod_set_clockact_none - set clockactivity test to BOTH
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_both(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_BOTH);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to MAIN
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_main(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_MAIN);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to ICLK
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_iclk(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_ICLK);
}
/**
* omap_hwmod_set_clockact_none - set clockactivity test to NONE
* @oh: struct omap_hwmod *
*
* On some modules, this function can affect the wakeup latency vs.
* power consumption balance. Intended to be called by the
* omap_device layer. Passes along the return value from
* _write_clockact_lock().
*/
int omap_hwmod_set_clockact_none(struct omap_hwmod *oh)
{
return _write_clockact_lock(oh, CLOCKACT_TEST_NONE);
}
/** /**
* omap_hwmod_enable_wakeup - allow device to wake up the system * omap_hwmod_enable_wakeup - allow device to wake up the system
* @oh: struct omap_hwmod * * @oh: struct omap_hwmod *
......
/*
* opp2420_data.c - old-style "OPP" table for OMAP2420
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Richard Woodruff <r-woodruff2@ti.com>
*
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
* These configurations are characterized by voltage and speed for clocks.
* The device is only validated for certain combinations. One way to express
* these combinations is via the 'ratio's' which the clocks operate with
* respect to each other. These ratio sets are for a given voltage/DPLL
* setting. All configurations can be described by a DPLL setting and a ratio
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
*
* 2430 differs from 2420 in that there are no more phase synchronizers used.
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
* 2430 (iva2.1, NOdsp, mdm)
*
* XXX Missing voltage data.
*
* THe format described in this file is deprecated. Once a reasonable
* OPP API exists, the data in this file should be converted to use it.
*
* This is technically part of the OMAP2xxx clock code.
*/
#include "opp2xxx.h"
#include "sdrc.h"
#include "clock.h"
/*-------------------------------------------------------------------------
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
*
* Filling in table based on H4 boards and 2430-SDPs variants available.
* There are quite a few more rates combinations which could be defined.
*
* When multiple values are defined the start up will try and choose the
* fastest one. If a 'fast' value is defined, then automatically, the /2
* one should be included as it can be used. Generally having more that
* one fast set does not make sense, as static timings need to be changed
* to change the set. The exception is the bypass setting which is
* availble for low power bypass.
*
* Note: This table needs to be sorted, fastest to slowest.
*-------------------------------------------------------------------------*/
const struct prcm_config omap2420_rate_table[] = {
/* PRCM I - FAST */
{S12M, S660M, S330M, RI_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
RI_CM_CLKSEL_DSP_VAL, RI_CM_CLKSEL_GFX_VAL,
RI_CM_CLKSEL1_CORE_VAL, MI_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_165MHz,
RATE_IN_242X},
/* PRCM II - FAST */
{S12M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
{S13M, S600M, S300M, RII_CM_CLKSEL_MPU_VAL, /* 300MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
/* PRCM III - FAST */
{S12M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
{S13M, S532M, S266M, RIII_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
/* PRCM II - SLOW */
{S12M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
{S13M, S300M, S150M, RII_CM_CLKSEL_MPU_VAL, /* 150MHz ARM */
RII_CM_CLKSEL_DSP_VAL, RII_CM_CLKSEL_GFX_VAL,
RII_CM_CLKSEL1_CORE_VAL, MII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_100MHz,
RATE_IN_242X},
/* PRCM III - SLOW */
{S12M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
{S13M, S266M, S133M, RIII_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
RIII_CM_CLKSEL_DSP_VAL, RIII_CM_CLKSEL_GFX_VAL,
RIII_CM_CLKSEL1_CORE_VAL, MIII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_133MHz,
RATE_IN_242X},
/* PRCM-VII (boot-bypass) */
{S12M, S12M, S12M, RVII_CM_CLKSEL_MPU_VAL, /* 12MHz ARM*/
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
RATE_IN_242X},
/* PRCM-VII (boot-bypass) */
{S13M, S13M, S13M, RVII_CM_CLKSEL_MPU_VAL, /* 13MHz ARM */
RVII_CM_CLKSEL_DSP_VAL, RVII_CM_CLKSEL_GFX_VAL,
RVII_CM_CLKSEL1_CORE_VAL, MVII_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, 0, SDRC_RFR_CTRL_BYPASS,
RATE_IN_242X},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
/*
* opp2420_data.c - old-style "OPP" table for OMAP2420
*
* Copyright (C) 2005-2009 Texas Instruments, Inc.
* Copyright (C) 2004-2009 Nokia Corporation
*
* Richard Woodruff <r-woodruff2@ti.com>
*
* The OMAP2 processor can be run at several discrete 'PRCM configurations'.
* These configurations are characterized by voltage and speed for clocks.
* The device is only validated for certain combinations. One way to express
* these combinations is via the 'ratio's' which the clocks operate with
* respect to each other. These ratio sets are for a given voltage/DPLL
* setting. All configurations can be described by a DPLL setting and a ratio
* There are 3 ratio sets for the 2430 and X ratio sets for 2420.
*
* 2430 differs from 2420 in that there are no more phase synchronizers used.
* They both have a slightly different clock domain setup. 2420(iva1,dsp) vs
* 2430 (iva2.1, NOdsp, mdm)
*
* XXX Missing voltage data.
*
* THe format described in this file is deprecated. Once a reasonable
* OPP API exists, the data in this file should be converted to use it.
*
* This is technically part of the OMAP2xxx clock code.
*/
#include "opp2xxx.h"
#include "sdrc.h"
#include "clock.h"
/*-------------------------------------------------------------------------
* Key dividers which make up a PRCM set. Ratio's for a PRCM are mandated.
* xtal_speed, dpll_speed, mpu_speed, CM_CLKSEL_MPU,
* CM_CLKSEL_DSP, CM_CLKSEL_GFX, CM_CLKSEL1_CORE, CM_CLKSEL1_PLL,
* CM_CLKSEL2_PLL, CM_CLKSEL_MDM
*
* Filling in table based on H4 boards and 2430-SDPs variants available.
* There are quite a few more rates combinations which could be defined.
*
* When multiple values are defined the start up will try and choose the
* fastest one. If a 'fast' value is defined, then automatically, the /2
* one should be included as it can be used. Generally having more that
* one fast set does not make sense, as static timings need to be changed
* to change the set. The exception is the bypass setting which is
* availble for low power bypass.
*
* Note: This table needs to be sorted, fastest to slowest.
*-------------------------------------------------------------------------*/
const struct prcm_config omap2430_rate_table[] = {
/* PRCM #4 - ratio2 (ES2.1) - FAST */
{S13M, S798M, S399M, R2_CM_CLKSEL_MPU_VAL, /* 399MHz ARM */
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, R2_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_133MHz,
RATE_IN_243X},
/* PRCM #2 - ratio1 (ES2) - FAST */
{S13M, S658M, S329M, R1_CM_CLKSEL_MPU_VAL, /* 330MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_165MHz,
RATE_IN_243X},
/* PRCM #5a - ratio1 - FAST */
{S13M, S532M, S266M, R1_CM_CLKSEL_MPU_VAL, /* 266MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_133MHz,
RATE_IN_243X},
/* PRCM #5b - ratio1 - FAST */
{S13M, S400M, S200M, R1_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_100MHz,
RATE_IN_243X},
/* PRCM #4 - ratio1 (ES2.1) - SLOW */
{S13M, S399M, S199M, R2_CM_CLKSEL_MPU_VAL, /* 200MHz ARM */
R2_CM_CLKSEL_DSP_VAL, R2_CM_CLKSEL_GFX_VAL,
R2_CM_CLKSEL1_CORE_VAL, M4_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_1x_VAL, R2_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_133MHz,
RATE_IN_243X},
/* PRCM #2 - ratio1 (ES2) - SLOW */
{S13M, S329M, S164M, R1_CM_CLKSEL_MPU_VAL, /* 165MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M2_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_165MHz,
RATE_IN_243X},
/* PRCM #5a - ratio1 - SLOW */
{S13M, S266M, S133M, R1_CM_CLKSEL_MPU_VAL, /* 133MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M5A_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_133MHz,
RATE_IN_243X},
/* PRCM #5b - ratio1 - SLOW*/
{S13M, S200M, S100M, R1_CM_CLKSEL_MPU_VAL, /* 100MHz ARM */
R1_CM_CLKSEL_DSP_VAL, R1_CM_CLKSEL_GFX_VAL,
R1_CM_CLKSEL1_CORE_VAL, M5B_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_1x_VAL, R1_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_100MHz,
RATE_IN_243X},
/* PRCM-boot/bypass */
{S13M, S13M, S13M, RB_CM_CLKSEL_MPU_VAL, /* 13Mhz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_13_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_BYPASS,
RATE_IN_243X},
/* PRCM-boot/bypass */
{S12M, S12M, S12M, RB_CM_CLKSEL_MPU_VAL, /* 12Mhz */
RB_CM_CLKSEL_DSP_VAL, RB_CM_CLKSEL_GFX_VAL,
RB_CM_CLKSEL1_CORE_VAL, MB_CM_CLKSEL1_PLL_12_VAL,
MX_CLKSEL2_PLL_2x_VAL, RB_CM_CLKSEL_MDM_VAL,
SDRC_RFR_CTRL_BYPASS,
RATE_IN_243X},
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0},
};
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