Commit 2563afa9 authored by Florian Tobias Schandinat's avatar Florian Tobias Schandinat

Merge branch 'viafb-pll' into viafb-next

parents bf5ea02d e4fcaeff
...@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp, ...@@ -195,7 +195,9 @@ void viafb_dvi_set_mode(struct VideoModeTable *mode, int mode_bpp,
struct crt_mode_table *pDviTiming; struct crt_mode_table *pDviTiming;
unsigned long desirePixelClock, maxPixelClock; unsigned long desirePixelClock, maxPixelClock;
pDviTiming = mode->crtc; pDviTiming = mode->crtc;
desirePixelClock = pDviTiming->clk / 1000000; desirePixelClock = pDviTiming->refresh_rate
* pDviTiming->crtc.hor_total * pDviTiming->crtc.ver_total
/ 1000000;
maxPixelClock = (unsigned long)viaparinfo-> maxPixelClock = (unsigned long)viaparinfo->
tmds_setting_info->max_pixel_clock; tmds_setting_info->max_pixel_clock;
......
This diff is collapsed.
...@@ -893,8 +893,6 @@ struct iga2_crtc_timing { ...@@ -893,8 +893,6 @@ struct iga2_crtc_timing {
/* VT3410 chipset*/ /* VT3410 chipset*/
#define VX900_FUNCTION3 0x3410 #define VX900_FUNCTION3 0x3410
#define NUM_TOTAL_PLL_TABLE ARRAY_SIZE(pll_value)
struct IODATA { struct IODATA {
u8 Index; u8 Index;
u8 Mask; u8 Mask;
......
...@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -562,7 +562,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
int set_vres = plvds_setting_info->v_active; int set_vres = plvds_setting_info->v_active;
int panel_hres = plvds_setting_info->lcd_panel_hres; int panel_hres = plvds_setting_info->lcd_panel_hres;
int panel_vres = plvds_setting_info->lcd_panel_vres; int panel_vres = plvds_setting_info->lcd_panel_vres;
u32 pll_D_N; u32 pll_D_N, clock;
struct display_timing mode_crt_reg, panel_crt_reg; struct display_timing mode_crt_reg, panel_crt_reg;
struct crt_mode_table *panel_crt_table = NULL; struct crt_mode_table *panel_crt_table = NULL;
struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres, struct VideoModeTable *vmode_tbl = viafb_get_mode(panel_hres,
...@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -577,7 +577,9 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n"); DEBUG_MSG(KERN_INFO "bellow viafb_lcd_set_mode!!\n");
if (VT1636_LVDS == plvds_chip_info->lvds_chip_name) if (VT1636_LVDS == plvds_chip_info->lvds_chip_name)
viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info); viafb_init_lvds_vt1636(plvds_setting_info, plvds_chip_info);
plvds_setting_info->vclk = panel_crt_table->clk; clock = panel_crt_reg.hor_total * panel_crt_reg.ver_total
* panel_crt_table->refresh_rate;
plvds_setting_info->vclk = clock;
if (set_iga == IGA1) { if (set_iga == IGA1) {
/* IGA1 doesn't have LCD scaling, so set it as centering. */ /* IGA1 doesn't have LCD scaling, so set it as centering. */
viafb_load_crtc_timing(lcd_centering_timging viafb_load_crtc_timing(lcd_centering_timging
...@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table, ...@@ -612,7 +614,7 @@ void viafb_lcd_set_mode(struct crt_mode_table *mode_crt_table,
fill_lcd_format(); fill_lcd_format();
pll_D_N = viafb_get_clk_value(panel_crt_table[0].clk); pll_D_N = viafb_get_clk_value(clock);
DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N); DEBUG_MSG(KERN_INFO "PLL=0x%x", pll_D_N);
viafb_set_vclock(pll_D_N, set_iga); viafb_set_vclock(pll_D_N, set_iga);
lcd_patch_skew(plvds_setting_info, plvds_chip_info); lcd_patch_skew(plvds_setting_info, plvds_chip_info);
......
...@@ -627,77 +627,6 @@ ...@@ -627,77 +627,6 @@
#define M2048x1536_R60_HSP NEGATIVE #define M2048x1536_R60_HSP NEGATIVE
#define M2048x1536_R60_VSP POSITIVE #define M2048x1536_R60_VSP POSITIVE
/* define PLL index: */
#define CLK_25_175M 25175000
#define CLK_26_880M 26880000
#define CLK_29_581M 29581000
#define CLK_31_500M 31500000
#define CLK_31_728M 31728000
#define CLK_32_668M 32688000
#define CLK_36_000M 36000000
#define CLK_40_000M 40000000
#define CLK_41_291M 41291000
#define CLK_43_163M 43163000
#define CLK_45_250M 45250000 /* 45.46MHz */
#define CLK_46_000M 46000000
#define CLK_46_996M 46996000
#define CLK_48_000M 48000000
#define CLK_48_875M 48875000
#define CLK_49_500M 49500000
#define CLK_52_406M 52406000
#define CLK_52_977M 52977000
#define CLK_56_250M 56250000
#define CLK_57_275M 57275000
#define CLK_60_466M 60466000
#define CLK_61_500M 61500000
#define CLK_65_000M 65000000
#define CLK_65_178M 65178000
#define CLK_66_750M 66750000 /* 67.116MHz */
#define CLK_68_179M 68179000
#define CLK_69_924M 69924000
#define CLK_70_159M 70159000
#define CLK_72_000M 72000000
#define CLK_74_270M 74270000
#define CLK_78_750M 78750000
#define CLK_80_136M 80136000
#define CLK_83_375M 83375000
#define CLK_83_950M 83950000
#define CLK_84_750M 84750000 /* 84.537Mhz */
#define CLK_85_860M 85860000
#define CLK_88_750M 88750000
#define CLK_94_500M 94500000
#define CLK_97_750M 97750000
#define CLK_101_000M 101000000
#define CLK_106_500M 106500000
#define CLK_108_000M 108000000
#define CLK_113_309M 113309000
#define CLK_118_840M 118840000
#define CLK_119_000M 119000000
#define CLK_121_750M 121750000 /* 121.704MHz */
#define CLK_125_104M 125104000
#define CLK_135_000M 135000000
#define CLK_136_700M 136700000
#define CLK_138_400M 138400000
#define CLK_146_760M 146760000
#define CLK_148_500M 148500000
#define CLK_153_920M 153920000
#define CLK_156_000M 156000000
#define CLK_157_500M 157500000
#define CLK_162_000M 162000000
#define CLK_187_000M 187000000
#define CLK_193_295M 193295000
#define CLK_202_500M 202500000
#define CLK_204_000M 204000000
#define CLK_218_500M 218500000
#define CLK_234_000M 234000000
#define CLK_267_250M 267250000
#define CLK_297_500M 297500000
#define CLK_74_481M 74481000
#define CLK_172_798M 172798000
#define CLK_122_614M 122614000
/* Definition CRTC Timing Index */ /* Definition CRTC Timing Index */
#define H_TOTAL_INDEX 0 #define H_TOTAL_INDEX 0
#define H_ADDR_INDEX 1 #define H_ADDR_INDEX 1
...@@ -722,76 +651,7 @@ ...@@ -722,76 +651,7 @@
/* Definition Video Mode Pixel Clock (picoseconds) /* Definition Video Mode Pixel Clock (picoseconds)
*/ */
#define RES_480X640_60HZ_PIXCLOCK 39722
#define RES_640X480_60HZ_PIXCLOCK 39722 #define RES_640X480_60HZ_PIXCLOCK 39722
#define RES_640X480_75HZ_PIXCLOCK 31747
#define RES_640X480_85HZ_PIXCLOCK 27777
#define RES_640X480_100HZ_PIXCLOCK 23168
#define RES_640X480_120HZ_PIXCLOCK 19081
#define RES_720X480_60HZ_PIXCLOCK 37020
#define RES_720X576_60HZ_PIXCLOCK 30611
#define RES_800X600_60HZ_PIXCLOCK 25000
#define RES_800X600_75HZ_PIXCLOCK 20203
#define RES_800X600_85HZ_PIXCLOCK 17777
#define RES_800X600_100HZ_PIXCLOCK 14667
#define RES_800X600_120HZ_PIXCLOCK 11912
#define RES_800X480_60HZ_PIXCLOCK 33805
#define RES_848X480_60HZ_PIXCLOCK 31756
#define RES_856X480_60HZ_PIXCLOCK 31518
#define RES_1024X512_60HZ_PIXCLOCK 24218
#define RES_1024X600_60HZ_PIXCLOCK 20460
#define RES_1024X768_60HZ_PIXCLOCK 15385
#define RES_1024X768_75HZ_PIXCLOCK 12699
#define RES_1024X768_85HZ_PIXCLOCK 10582
#define RES_1024X768_100HZ_PIXCLOCK 8825
#define RES_1152X864_75HZ_PIXCLOCK 9259
#define RES_1280X768_60HZ_PIXCLOCK 12480
#define RES_1280X800_60HZ_PIXCLOCK 11994
#define RES_1280X960_60HZ_PIXCLOCK 9259
#define RES_1280X1024_60HZ_PIXCLOCK 9260
#define RES_1280X1024_75HZ_PIXCLOCK 7408
#define RES_1280X768_85HZ_PIXCLOCK 6349
#define RES_1440X1050_60HZ_PIXCLOCK 7993
#define RES_1600X1200_60HZ_PIXCLOCK 6172
#define RES_1600X1200_75HZ_PIXCLOCK 4938
#define RES_1280X720_60HZ_PIXCLOCK 13426
#define RES_1200X900_60HZ_PIXCLOCK 17459
#define RES_1920X1080_60HZ_PIXCLOCK 5787
#define RES_1400X1050_60HZ_PIXCLOCK 8214
#define RES_1400X1050_75HZ_PIXCLOCK 6410
#define RES_1368X768_60HZ_PIXCLOCK 11647
#define RES_960X600_60HZ_PIXCLOCK 22099
#define RES_1000X600_60HZ_PIXCLOCK 20834
#define RES_1024X576_60HZ_PIXCLOCK 21278
#define RES_1088X612_60HZ_PIXCLOCK 18877
#define RES_1152X720_60HZ_PIXCLOCK 14981
#define RES_1200X720_60HZ_PIXCLOCK 14253
#define RES_1280X600_60HZ_PIXCLOCK 16260
#define RES_1280X720_50HZ_PIXCLOCK 16538
#define RES_1280X768_50HZ_PIXCLOCK 15342
#define RES_1366X768_50HZ_PIXCLOCK 14301
#define RES_1366X768_60HZ_PIXCLOCK 11646
#define RES_1360X768_60HZ_PIXCLOCK 11799
#define RES_1440X900_60HZ_PIXCLOCK 9390
#define RES_1440X900_75HZ_PIXCLOCK 7315
#define RES_1600X900_60HZ_PIXCLOCK 8415
#define RES_1600X1024_60HZ_PIXCLOCK 7315
#define RES_1680X1050_60HZ_PIXCLOCK 6814
#define RES_1680X1050_75HZ_PIXCLOCK 5348
#define RES_1792X1344_60HZ_PIXCLOCK 4902
#define RES_1856X1392_60HZ_PIXCLOCK 4577
#define RES_1920X1200_60HZ_PIXCLOCK 5173
#define RES_1920X1440_60HZ_PIXCLOCK 4274
#define RES_1920X1440_75HZ_PIXCLOCK 3367
#define RES_2048X1536_60HZ_PIXCLOCK 3742
#define RES_1360X768_RB_60HZ_PIXCLOCK 13889
#define RES_1400X1050_RB_60HZ_PIXCLOCK 9901
#define RES_1440X900_RB_60HZ_PIXCLOCK 11268
#define RES_1600X900_RB_60HZ_PIXCLOCK 10230
#define RES_1680X1050_RB_60HZ_PIXCLOCK 8403
#define RES_1920X1080_RB_60HZ_PIXCLOCK 7225
#define RES_1920X1200_RB_60HZ_PIXCLOCK 6497
/* LCD display method /* LCD display method
*/ */
...@@ -822,7 +682,6 @@ struct display_timing { ...@@ -822,7 +682,6 @@ struct display_timing {
struct crt_mode_table { struct crt_mode_table {
int refresh_rate; int refresh_rate;
unsigned long clk;
int h_sync_polarity; int h_sync_polarity;
int v_sync_polarity; int v_sync_polarity;
struct display_timing crtc; struct display_timing crtc;
......
This diff is collapsed.
...@@ -41,14 +41,6 @@ struct patch_table { ...@@ -41,14 +41,6 @@ struct patch_table {
struct io_reg *io_reg_table; struct io_reg *io_reg_table;
}; };
struct res_map_refresh {
int hres;
int vres;
int pixclock;
int vmode_refresh;
};
extern int NUM_TOTAL_RES_MAP_REFRESH;
extern int NUM_TOTAL_CEA_MODES; extern int NUM_TOTAL_CEA_MODES;
extern int NUM_TOTAL_CN400_ModeXregs; extern int NUM_TOTAL_CN400_ModeXregs;
extern int NUM_TOTAL_CN700_ModeXregs; extern int NUM_TOTAL_CN700_ModeXregs;
...@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[]; ...@@ -66,7 +58,6 @@ extern struct crt_mode_table CEAM1280x720[];
extern struct crt_mode_table CEAM1920x1080[]; extern struct crt_mode_table CEAM1920x1080[];
extern struct VideoModeTable CEA_HDMI_Modes[]; extern struct VideoModeTable CEA_HDMI_Modes[];
extern struct res_map_refresh res_map_refresh_tbl[];
extern struct io_reg CN400_ModeXregs[]; extern struct io_reg CN400_ModeXregs[];
extern struct io_reg CN700_ModeXregs[]; extern struct io_reg CN700_ModeXregs[];
extern struct io_reg KM400_ModeXregs[]; extern struct io_reg KM400_ModeXregs[];
......
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