Commit 25798d52 authored by Jun Nie's avatar Jun Nie Committed by Shawn Guo

arm64: dts: zte: add mmc devices for zx296718

Add three mmc devices for zx296718 SoC, and enable the SD and eMMMC on
zx296718-evb board.
Signed-off-by: default avatarJun Nie <jun.nie@linaro.org>
Signed-off-by: default avatarShawn Guo <shawn.guo@linaro.org>
parent 6d7e05ab
...@@ -59,6 +59,14 @@ memory@40000000 { ...@@ -59,6 +59,14 @@ memory@40000000 {
}; };
&emmc {
status = "okay";
};
&sd1 {
status = "okay";
};
&uart0 { &uart0 {
status = "okay"; status = "okay";
}; };
...@@ -298,6 +298,51 @@ uart0: uart@11f000 { ...@@ -298,6 +298,51 @@ uart0: uart@11f000 {
status = "disabled"; status = "disabled";
}; };
sd0: mmc@1110000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01110000 0x1000>;
interrupts = <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <50000000>;
clocks = <&topcrm SD0_AHB>, <&topcrm SD0_WCLK>;
clock-names = "biu", "ciu";
num-slots = <1>;
max-frequency = <50000000>;
cap-sdio-irq;
cap-sd-highspeed;
sd-uhs-sdr12;
sd-uhs-sdr25;
sd-uhs-sdr50;
sd-uhs-sdr104;
sd-uhs-ddr50;
status = "disabled";
};
sd1: mmc@1111000 {
compatible = "zte,zx296718-dw-mshc";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x01111000 0x1000>;
interrupts = <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>;
fifo-depth = <32>;
data-addr = <0x200>;
fifo-watermark-aligned;
bus-width = <4>;
clock-frequency = <167000000>;
clocks = <&topcrm SD1_AHB>, <&topcrm SD1_WCLK>;
clock-names = "biu", "ciu";
num-slots = <1>;
max-frequency = <167000000>;
cap-sdio-irq;
cap-sd-highspeed;
status = "disabled";
};
dma: dma-controller@1460000 { dma: dma-controller@1460000 {
compatible = "zte,zx296702-dma"; compatible = "zte,zx296702-dma";
reg = <0x01460000 0x1000>; reg = <0x01460000 0x1000>;
...@@ -332,6 +377,27 @@ sysctrl: sysctrl@1463000 { ...@@ -332,6 +377,27 @@ sysctrl: sysctrl@1463000 {
reg = <0x1463000 0x1000>; reg = <0x1463000 0x1000>;
}; };
emmc: mmc@1470000{
compatible = "zte,zx296718-dw-mshc";
reg = <0x01470000 0x1000>;
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
zte,aon-syscon = <&aon_sysctrl>;
bus-width = <8>;
fifo-depth = <128>;
data-addr = <0x200>;
fifo-watermark-aligned;
clock-frequency = <167000000>;
clocks = <&topcrm EMMC_NAND_AHB>, <&topcrm EMMC_WCLK>;
clock-names = "biu", "ciu";
max-frequency = <167000000>;
cap-mmc-highspeed;
mmc-ddr-1_8v;
mmc-hs200-1_8v;
non-removable;
disable-wp;
status = "disabled";
};
audiocrm: clock-controller@1480000 { audiocrm: clock-controller@1480000 {
compatible = "zte,zx296718-audiocrm"; compatible = "zte,zx296718-audiocrm";
reg = <0x01480000 0x1000>; reg = <0x01480000 0x1000>;
......
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