Commit 26045b53 authored by Dave Airlie's avatar Dave Airlie

Merge tag 'drm-intel-next-2014-11-21-fixed' of...

Merge tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel into drm-next

drm-intel-next-2014-11-21:
- infoframe tracking (for fastboot) from Jesse
- start of the dri1/ums support removal
- vlv forcewake timeout fixes (Imre)
- bunch of patches to polish the rps code (Imre) and improve it on bdw (Tom
  O'Rourke)
- on-demand pinning for execlist contexts
- vlv/chv backlight improvements (Ville)
- gen8+ render ctx w/a work from various people
- skl edp programming (Satheeshakrishna et al.)
- psr docbook (Rodrigo)
- piles of little fixes and improvements all over, as usual

* tag 'drm-intel-next-2014-11-21-fixed' of git://anongit.freedesktop.org/drm-intel: (117 commits)
  drm/i915: Don't pin LRC in GGTT when dumping in debugfs
  drm/i915: Update DRIVER_DATE to 20141121
  drm/i915/g4x: fix g4x infoframe readout
  drm/i915: Only call mod_timer() if not already pending
  drm/i915: Don't rely upon encoder->type for infoframe hw state readout
  drm/i915: remove the IRQs enabled WARN from intel_disable_gt_powersave
  drm/i915: Use ggtt error obj capture helper for gen8 semaphores
  drm/i915: vlv: increase timeout when setting idle GPU freq
  drm/i915: vlv: fix cdclk setting during modeset while suspended
  drm/i915: Dump hdmi pipe_config state
  drm/i915: Gen9 shadowed registers
  drm/i915/skl: Gen9 multi-engine forcewake
  drm/i915: Read power well status before other registers for drpc info
  drm/i915: Pin tiled objects for L-shaped configs
  drm/i915: Update ring freq for full gpu freq range
  drm/i915: change initial rps frequency for gen8
  drm/i915: Keep min freq above floor on HSW/BDW
  drm/i915: Use efficient frequency for HSW/BDW
  drm/i915: Can i915_gem_init_ioctl
  drm/i915: Sanitize ->lastclose
  ...
parents 1a92b7a2 064ca1d2
...@@ -3919,6 +3919,11 @@ int num_ioctls;</synopsis> ...@@ -3919,6 +3919,11 @@ int num_ioctls;</synopsis>
<title>High Definition Audio</title> <title>High Definition Audio</title>
!Pdrivers/gpu/drm/i915/intel_audio.c High Definition Audio over HDMI and Display Port !Pdrivers/gpu/drm/i915/intel_audio.c High Definition Audio over HDMI and Display Port
!Idrivers/gpu/drm/i915/intel_audio.c !Idrivers/gpu/drm/i915/intel_audio.c
</sect2>
<sect2>
<title>Panel Self Refresh PSR (PSR/SRD)</title>
!Pdrivers/gpu/drm/i915/intel_psr.c Panel Self Refresh (PSR/SRD)
!Idrivers/gpu/drm/i915/intel_psr.c
</sect2> </sect2>
<sect2> <sect2>
<title>DPIO</title> <title>DPIO</title>
...@@ -4029,6 +4034,27 @@ int num_ioctls;</synopsis> ...@@ -4029,6 +4034,27 @@ int num_ioctls;</synopsis>
!Idrivers/gpu/drm/i915/intel_lrc.c !Idrivers/gpu/drm/i915/intel_lrc.c
</sect2> </sect2>
</sect1> </sect1>
<sect1>
<title> Tracing </title>
<para>
This sections covers all things related to the tracepoints implemented in
the i915 driver.
</para>
<sect2>
<title> i915_ppgtt_create and i915_ppgtt_release </title>
!Pdrivers/gpu/drm/i915/i915_trace.h i915_ppgtt_create and i915_ppgtt_release tracepoints
</sect2>
<sect2>
<title> i915_context_create and i915_context_free </title>
!Pdrivers/gpu/drm/i915/i915_trace.h i915_context_create and i915_context_free tracepoints
</sect2>
<sect2>
<title> switch_mm </title>
!Pdrivers/gpu/drm/i915/i915_trace.h switch_mm tracepoint
</sect2>
</sect1>
</chapter> </chapter>
!Cdrivers/gpu/drm/i915/i915_irq.c !Cdrivers/gpu/drm/i915/i915_irq.c
</part> </part>
......
...@@ -3145,9 +3145,12 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid) ...@@ -3145,9 +3145,12 @@ void drm_edid_to_eld(struct drm_connector *connector, struct edid *edid)
} }
} }
eld[5] |= sad_count << 4; eld[5] |= sad_count << 4;
eld[2] = (20 + mnl + sad_count * 3 + 3) / 4;
DRM_DEBUG_KMS("ELD size %d, SAD count %d\n", (int)eld[2], sad_count); eld[DRM_ELD_BASELINE_ELD_LEN] =
DIV_ROUND_UP(drm_eld_calc_baseline_block_size(eld), 4);
DRM_DEBUG_KMS("ELD size %d, SAD count %d\n",
drm_eld_size(eld), sad_count);
} }
EXPORT_SYMBOL(drm_edid_to_eld); EXPORT_SYMBOL(drm_edid_to_eld);
......
...@@ -51,6 +51,7 @@ i915-y += intel_audio.o \ ...@@ -51,6 +51,7 @@ i915-y += intel_audio.o \
intel_frontbuffer.o \ intel_frontbuffer.o \
intel_modes.o \ intel_modes.o \
intel_overlay.o \ intel_overlay.o \
intel_psr.o \
intel_sideband.o \ intel_sideband.o \
intel_sprite.o intel_sprite.o
i915-$(CONFIG_ACPI) += intel_acpi.o intel_opregion.o i915-$(CONFIG_ACPI) += intel_acpi.o intel_opregion.o
......
...@@ -413,6 +413,8 @@ static const u32 gen7_render_regs[] = { ...@@ -413,6 +413,8 @@ static const u32 gen7_render_regs[] = {
REG64(PS_INVOCATION_COUNT), REG64(PS_INVOCATION_COUNT),
REG64(PS_DEPTH_COUNT), REG64(PS_DEPTH_COUNT),
OACONTROL, /* Only allowed for LRI and SRM. See below. */ OACONTROL, /* Only allowed for LRI and SRM. See below. */
REG64(MI_PREDICATE_SRC0),
REG64(MI_PREDICATE_SRC1),
GEN7_3DPRIM_END_OFFSET, GEN7_3DPRIM_END_OFFSET,
GEN7_3DPRIM_START_VERTEX, GEN7_3DPRIM_START_VERTEX,
GEN7_3DPRIM_VERTEX_COUNT, GEN7_3DPRIM_VERTEX_COUNT,
...@@ -1072,6 +1074,8 @@ int i915_cmd_parser_get_version(void) ...@@ -1072,6 +1074,8 @@ int i915_cmd_parser_get_version(void)
* *
* 1. Initial version. Checks batches and reports violations, but leaves * 1. Initial version. Checks batches and reports violations, but leaves
* hardware parsing enabled (so does not allow new use cases). * hardware parsing enabled (so does not allow new use cases).
* 2. Allow access to the MI_PREDICATE_SRC0 and
* MI_PREDICATE_SRC1 registers.
*/ */
return 1; return 2;
} }
...@@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m) ...@@ -1240,11 +1240,12 @@ static int vlv_drpc_info(struct seq_file *m)
struct drm_info_node *node = m->private; struct drm_info_node *node = m->private;
struct drm_device *dev = node->minor->dev; struct drm_device *dev = node->minor->dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
u32 rpmodectl1, rcctl1; u32 rpmodectl1, rcctl1, pw_status;
unsigned fw_rendercount = 0, fw_mediacount = 0; unsigned fw_rendercount = 0, fw_mediacount = 0;
intel_runtime_pm_get(dev_priv); intel_runtime_pm_get(dev_priv);
pw_status = I915_READ(VLV_GTLC_PW_STATUS);
rpmodectl1 = I915_READ(GEN6_RP_CONTROL); rpmodectl1 = I915_READ(GEN6_RP_CONTROL);
rcctl1 = I915_READ(GEN6_RC_CONTROL); rcctl1 = I915_READ(GEN6_RC_CONTROL);
...@@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m) ...@@ -1263,11 +1264,9 @@ static int vlv_drpc_info(struct seq_file *m)
yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE | yesno(rcctl1 & (GEN7_RC_CTL_TO_MODE |
GEN6_RC_CTL_EI_MODE(1)))); GEN6_RC_CTL_EI_MODE(1))));
seq_printf(m, "Render Power Well: %s\n", seq_printf(m, "Render Power Well: %s\n",
(I915_READ(VLV_GTLC_PW_STATUS) & (pw_status & VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
VLV_GTLC_PW_RENDER_STATUS_MASK) ? "Up" : "Down");
seq_printf(m, "Media Power Well: %s\n", seq_printf(m, "Media Power Well: %s\n",
(I915_READ(VLV_GTLC_PW_STATUS) & (pw_status & VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
VLV_GTLC_PW_MEDIA_STATUS_MASK) ? "Up" : "Down");
seq_printf(m, "Render RC6 residency since boot: %u\n", seq_printf(m, "Render RC6 residency since boot: %u\n",
I915_READ(VLV_GT_RENDER_RC6)); I915_READ(VLV_GT_RENDER_RC6));
...@@ -1773,6 +1772,50 @@ static int i915_context_status(struct seq_file *m, void *unused) ...@@ -1773,6 +1772,50 @@ static int i915_context_status(struct seq_file *m, void *unused)
return 0; return 0;
} }
static void i915_dump_lrc_obj(struct seq_file *m,
struct intel_engine_cs *ring,
struct drm_i915_gem_object *ctx_obj)
{
struct page *page;
uint32_t *reg_state;
int j;
unsigned long ggtt_offset = 0;
if (ctx_obj == NULL) {
seq_printf(m, "Context on %s with no gem object\n",
ring->name);
return;
}
seq_printf(m, "CONTEXT: %s %u\n", ring->name,
intel_execlists_ctx_id(ctx_obj));
if (!i915_gem_obj_ggtt_bound(ctx_obj))
seq_puts(m, "\tNot bound in GGTT\n");
else
ggtt_offset = i915_gem_obj_ggtt_offset(ctx_obj);
if (i915_gem_object_get_pages(ctx_obj)) {
seq_puts(m, "\tFailed to get pages for context object\n");
return;
}
page = i915_gem_object_get_page(ctx_obj, 1);
if (!WARN_ON(page == NULL)) {
reg_state = kmap_atomic(page);
for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
ggtt_offset + 4096 + (j * 4),
reg_state[j], reg_state[j + 1],
reg_state[j + 2], reg_state[j + 3]);
}
kunmap_atomic(reg_state);
}
seq_putc(m, '\n');
}
static int i915_dump_lrc(struct seq_file *m, void *unused) static int i915_dump_lrc(struct seq_file *m, void *unused)
{ {
struct drm_info_node *node = (struct drm_info_node *) m->private; struct drm_info_node *node = (struct drm_info_node *) m->private;
...@@ -1793,29 +1836,9 @@ static int i915_dump_lrc(struct seq_file *m, void *unused) ...@@ -1793,29 +1836,9 @@ static int i915_dump_lrc(struct seq_file *m, void *unused)
list_for_each_entry(ctx, &dev_priv->context_list, link) { list_for_each_entry(ctx, &dev_priv->context_list, link) {
for_each_ring(ring, dev_priv, i) { for_each_ring(ring, dev_priv, i) {
struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; if (ring->default_context != ctx)
i915_dump_lrc_obj(m, ring,
if (ring->default_context == ctx) ctx->engine[i].state);
continue;
if (ctx_obj) {
struct page *page = i915_gem_object_get_page(ctx_obj, 1);
uint32_t *reg_state = kmap_atomic(page);
int j;
seq_printf(m, "CONTEXT: %s %u\n", ring->name,
intel_execlists_ctx_id(ctx_obj));
for (j = 0; j < 0x600 / sizeof(u32) / 4; j += 4) {
seq_printf(m, "\t[0x%08lx] 0x%08x 0x%08x 0x%08x 0x%08x\n",
i915_gem_obj_ggtt_offset(ctx_obj) + 4096 + (j * 4),
reg_state[j], reg_state[j + 1],
reg_state[j + 2], reg_state[j + 3]);
}
kunmap_atomic(reg_state);
seq_putc(m, '\n');
}
} }
} }
...@@ -1975,6 +1998,8 @@ static int i915_swizzle_info(struct seq_file *m, void *data) ...@@ -1975,6 +1998,8 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
if (IS_GEN3(dev) || IS_GEN4(dev)) { if (IS_GEN3(dev) || IS_GEN4(dev)) {
seq_printf(m, "DDC = 0x%08x\n", seq_printf(m, "DDC = 0x%08x\n",
I915_READ(DCC)); I915_READ(DCC));
seq_printf(m, "DDC2 = 0x%08x\n",
I915_READ(DCC2));
seq_printf(m, "C0DRB3 = 0x%04x\n", seq_printf(m, "C0DRB3 = 0x%04x\n",
I915_READ16(C0DRB3)); I915_READ16(C0DRB3));
seq_printf(m, "C1DRB3 = 0x%04x\n", seq_printf(m, "C1DRB3 = 0x%04x\n",
...@@ -1997,6 +2022,10 @@ static int i915_swizzle_info(struct seq_file *m, void *data) ...@@ -1997,6 +2022,10 @@ static int i915_swizzle_info(struct seq_file *m, void *data)
seq_printf(m, "DISP_ARB_CTL = 0x%08x\n", seq_printf(m, "DISP_ARB_CTL = 0x%08x\n",
I915_READ(DISP_ARB_CTL)); I915_READ(DISP_ARB_CTL));
} }
if (dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES)
seq_puts(m, "L-shaped memory detected\n");
intel_runtime_pm_put(dev_priv); intel_runtime_pm_put(dev_priv);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
......
This diff is collapsed.
...@@ -584,6 +584,8 @@ static int i915_drm_suspend(struct drm_device *dev) ...@@ -584,6 +584,8 @@ static int i915_drm_suspend(struct drm_device *dev)
return error; return error;
} }
intel_suspend_gt_powersave(dev);
/* /*
* Disable CRTCs directly since we want to preserve sw state * Disable CRTCs directly since we want to preserve sw state
* for _thaw. Also, power gate the CRTC power wells. * for _thaw. Also, power gate the CRTC power wells.
...@@ -595,15 +597,11 @@ static int i915_drm_suspend(struct drm_device *dev) ...@@ -595,15 +597,11 @@ static int i915_drm_suspend(struct drm_device *dev)
intel_dp_mst_suspend(dev); intel_dp_mst_suspend(dev);
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
intel_runtime_pm_disable_interrupts(dev_priv); intel_runtime_pm_disable_interrupts(dev_priv);
intel_hpd_cancel_work(dev_priv); intel_hpd_cancel_work(dev_priv);
intel_suspend_encoders(dev_priv); intel_suspend_encoders(dev_priv);
intel_suspend_gt_powersave(dev);
intel_suspend_hw(dev); intel_suspend_hw(dev);
} }
...@@ -703,12 +701,10 @@ static int i915_drm_resume(struct drm_device *dev) ...@@ -703,12 +701,10 @@ static int i915_drm_resume(struct drm_device *dev)
intel_modeset_init_hw(dev); intel_modeset_init_hw(dev);
{
spin_lock_irq(&dev_priv->irq_lock); spin_lock_irq(&dev_priv->irq_lock);
if (dev_priv->display.hpd_irq_setup) if (dev_priv->display.hpd_irq_setup)
dev_priv->display.hpd_irq_setup(dev); dev_priv->display.hpd_irq_setup(dev);
spin_unlock_irq(&dev_priv->irq_lock); spin_unlock_irq(&dev_priv->irq_lock);
}
intel_dp_mst_resume(dev); intel_dp_mst_resume(dev);
drm_modeset_lock_all(dev); drm_modeset_lock_all(dev);
...@@ -856,10 +852,7 @@ int i915_reset(struct drm_device *dev) ...@@ -856,10 +852,7 @@ int i915_reset(struct drm_device *dev)
* was running at the time of the reset (i.e. we weren't VT * was running at the time of the reset (i.e. we weren't VT
* switched away). * switched away).
*/ */
if (drm_core_check_feature(dev, DRIVER_MODESET) || if (drm_core_check_feature(dev, DRIVER_MODESET)) {
!dev_priv->ums.mm_suspended) {
dev_priv->ums.mm_suspended = 0;
/* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */ /* Used to prevent gem_check_wedged returning -EAGAIN during gpu reset */
dev_priv->gpu_error.reload_in_reset = true; dev_priv->gpu_error.reload_in_reset = true;
...@@ -1395,9 +1388,8 @@ static int intel_runtime_suspend(struct device *device) ...@@ -1395,9 +1388,8 @@ static int intel_runtime_suspend(struct device *device)
i915_gem_release_all_mmaps(dev_priv); i915_gem_release_all_mmaps(dev_priv);
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
flush_delayed_work(&dev_priv->rps.delayed_resume_work);
intel_runtime_pm_disable_interrupts(dev_priv);
intel_suspend_gt_powersave(dev); intel_suspend_gt_powersave(dev);
intel_runtime_pm_disable_interrupts(dev_priv);
ret = intel_suspend_complete(dev_priv); ret = intel_suspend_complete(dev_priv);
if (ret) { if (ret) {
...@@ -1578,8 +1570,6 @@ static struct drm_driver driver = { ...@@ -1578,8 +1570,6 @@ static struct drm_driver driver = {
.resume = i915_resume_legacy, .resume = i915_resume_legacy,
.device_is_agp = i915_driver_device_is_agp, .device_is_agp = i915_driver_device_is_agp,
.master_create = i915_master_create,
.master_destroy = i915_master_destroy,
#if defined(CONFIG_DEBUG_FS) #if defined(CONFIG_DEBUG_FS)
.debugfs_init = i915_debugfs_init, .debugfs_init = i915_debugfs_init,
.debugfs_cleanup = i915_debugfs_cleanup, .debugfs_cleanup = i915_debugfs_cleanup,
......
...@@ -55,7 +55,7 @@ ...@@ -55,7 +55,7 @@
#define DRIVER_NAME "i915" #define DRIVER_NAME "i915"
#define DRIVER_DESC "Intel Graphics" #define DRIVER_DESC "Intel Graphics"
#define DRIVER_DATE "20141107" #define DRIVER_DATE "20141121"
#undef WARN_ON #undef WARN_ON
#define WARN_ON(x) WARN(x, "WARN_ON(" #x ")") #define WARN_ON(x) WARN(x, "WARN_ON(" #x ")")
...@@ -213,10 +213,15 @@ enum intel_dpll_id { ...@@ -213,10 +213,15 @@ enum intel_dpll_id {
/* real shared dpll ids must be >= 0 */ /* real shared dpll ids must be >= 0 */
DPLL_ID_PCH_PLL_A = 0, DPLL_ID_PCH_PLL_A = 0,
DPLL_ID_PCH_PLL_B = 1, DPLL_ID_PCH_PLL_B = 1,
/* hsw/bdw */
DPLL_ID_WRPLL1 = 0, DPLL_ID_WRPLL1 = 0,
DPLL_ID_WRPLL2 = 1, DPLL_ID_WRPLL2 = 1,
/* skl */
DPLL_ID_SKL_DPLL1 = 0,
DPLL_ID_SKL_DPLL2 = 1,
DPLL_ID_SKL_DPLL3 = 2,
}; };
#define I915_NUM_PLLS 2 #define I915_NUM_PLLS 3
struct intel_dpll_hw_state { struct intel_dpll_hw_state {
/* i9xx, pch plls */ /* i9xx, pch plls */
...@@ -227,6 +232,17 @@ struct intel_dpll_hw_state { ...@@ -227,6 +232,17 @@ struct intel_dpll_hw_state {
/* hsw, bdw */ /* hsw, bdw */
uint32_t wrpll; uint32_t wrpll;
/* skl */
/*
* DPLL_CTRL1 has 6 bits for each each this DPLL. We store those in
* lower part of crtl1 and they get shifted into position when writing
* the register. This allows us to easily compare the state to share
* the DPLL.
*/
uint32_t ctrl1;
/* HDMI only, 0 when used for DP */
uint32_t cfgcr1, cfgcr2;
}; };
struct intel_shared_dpll_config { struct intel_shared_dpll_config {
...@@ -256,6 +272,11 @@ struct intel_shared_dpll { ...@@ -256,6 +272,11 @@ struct intel_shared_dpll {
struct intel_dpll_hw_state *hw_state); struct intel_dpll_hw_state *hw_state);
}; };
#define SKL_DPLL0 0
#define SKL_DPLL1 1
#define SKL_DPLL2 2
#define SKL_DPLL3 3
/* Used by dp and fdi links */ /* Used by dp and fdi links */
struct intel_link_m_n { struct intel_link_m_n {
uint32_t tu; uint32_t tu;
...@@ -306,12 +327,6 @@ struct intel_opregion { ...@@ -306,12 +327,6 @@ struct intel_opregion {
struct intel_overlay; struct intel_overlay;
struct intel_overlay_error_state; struct intel_overlay_error_state;
struct drm_local_map;
struct drm_i915_master_private {
struct drm_local_map *sarea;
struct _drm_i915_sarea *sarea_priv;
};
#define I915_FENCE_REG_NONE -1 #define I915_FENCE_REG_NONE -1
#define I915_MAX_NUM_FENCES 32 #define I915_MAX_NUM_FENCES 32
/* 32 fences + sign bit for FENCE_REG_NONE */ /* 32 fences + sign bit for FENCE_REG_NONE */
...@@ -510,7 +525,7 @@ struct drm_i915_display_funcs { ...@@ -510,7 +525,7 @@ struct drm_i915_display_funcs {
/* display clock increase/decrease */ /* display clock increase/decrease */
/* pll clock increase/decrease */ /* pll clock increase/decrease */
int (*setup_backlight)(struct intel_connector *connector); int (*setup_backlight)(struct intel_connector *connector, enum pipe pipe);
uint32_t (*get_backlight)(struct intel_connector *connector); uint32_t (*get_backlight)(struct intel_connector *connector);
void (*set_backlight)(struct intel_connector *connector, void (*set_backlight)(struct intel_connector *connector,
uint32_t level); uint32_t level);
...@@ -664,6 +679,7 @@ struct intel_context { ...@@ -664,6 +679,7 @@ struct intel_context {
struct { struct {
struct drm_i915_gem_object *state; struct drm_i915_gem_object *state;
struct intel_ringbuffer *ringbuf; struct intel_ringbuffer *ringbuf;
int unpin_count;
} engine[I915_NUM_RINGS]; } engine[I915_NUM_RINGS];
struct list_head link; struct list_head link;
...@@ -748,6 +764,7 @@ enum intel_sbi_destination { ...@@ -748,6 +764,7 @@ enum intel_sbi_destination {
#define QUIRK_INVERT_BRIGHTNESS (1<<2) #define QUIRK_INVERT_BRIGHTNESS (1<<2)
#define QUIRK_BACKLIGHT_PRESENT (1<<3) #define QUIRK_BACKLIGHT_PRESENT (1<<3)
#define QUIRK_PIPEB_FORCE (1<<4) #define QUIRK_PIPEB_FORCE (1<<4)
#define QUIRK_PIN_SWIZZLED_PAGES (1<<5)
struct intel_fbdev; struct intel_fbdev;
struct intel_fbc_work; struct intel_fbc_work;
...@@ -799,7 +816,6 @@ struct i915_suspend_saved_registers { ...@@ -799,7 +816,6 @@ struct i915_suspend_saved_registers {
u32 saveBLC_HIST_CTL; u32 saveBLC_HIST_CTL;
u32 saveBLC_PWM_CTL; u32 saveBLC_PWM_CTL;
u32 saveBLC_PWM_CTL2; u32 saveBLC_PWM_CTL2;
u32 saveBLC_HIST_CTL_B;
u32 saveBLC_CPU_PWM_CTL; u32 saveBLC_CPU_PWM_CTL;
u32 saveBLC_CPU_PWM_CTL2; u32 saveBLC_CPU_PWM_CTL2;
u32 saveFPB0; u32 saveFPB0;
...@@ -978,8 +994,12 @@ struct intel_rps_ei { ...@@ -978,8 +994,12 @@ struct intel_rps_ei {
}; };
struct intel_gen6_power_mgmt { struct intel_gen6_power_mgmt {
/* work and pm_iir are protected by dev_priv->irq_lock */ /*
* work, interrupts_enabled and pm_iir are protected by
* dev_priv->irq_lock
*/
struct work_struct work; struct work_struct work;
bool interrupts_enabled;
u32 pm_iir; u32 pm_iir;
/* Frequencies are stored in potentially platform dependent multiples. /* Frequencies are stored in potentially platform dependent multiples.
...@@ -1102,31 +1122,6 @@ struct i915_power_domains { ...@@ -1102,31 +1122,6 @@ struct i915_power_domains {
struct i915_power_well *power_wells; struct i915_power_well *power_wells;
}; };
struct i915_dri1_state {
unsigned allow_batchbuffer : 1;
u32 __iomem *gfx_hws_cpu_addr;
unsigned int cpp;
int back_offset;
int front_offset;
int current_page;
int page_flipping;
uint32_t counter;
};
struct i915_ums_state {
/**
* Flag if the X Server, and thus DRM, is not currently in
* control of the device.
*
* This is set between LeaveVT and EnterVT. It needs to be
* replaced with a semaphore. It also needs to be
* transitioned away from for kernel modesetting.
*/
int mm_suspended;
};
#define MAX_L3_SLICES 2 #define MAX_L3_SLICES 2
struct intel_l3_parity { struct intel_l3_parity {
u32 *remap_info[MAX_L3_SLICES]; u32 *remap_info[MAX_L3_SLICES];
...@@ -1762,12 +1757,6 @@ struct drm_i915_private { ...@@ -1762,12 +1757,6 @@ struct drm_i915_private {
uint32_t bios_vgacntr; uint32_t bios_vgacntr;
/* Old dri1 support infrastructure, beware the dragons ya fools entering
* here! */
struct i915_dri1_state dri1;
/* Old ums support infrastructure, same warning applies. */
struct i915_ums_state ums;
/* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */
struct { struct {
int (*do_execbuf)(struct drm_device *dev, struct drm_file *file, int (*do_execbuf)(struct drm_device *dev, struct drm_file *file,
...@@ -1957,10 +1946,10 @@ struct drm_i915_gem_object { ...@@ -1957,10 +1946,10 @@ struct drm_i915_gem_object {
unsigned long user_pin_count; unsigned long user_pin_count;
struct drm_file *pin_filp; struct drm_file *pin_filp;
union {
/** for phy allocated objects */ /** for phy allocated objects */
struct drm_dma_handle *phys_handle; struct drm_dma_handle *phys_handle;
union {
struct i915_gem_userptr { struct i915_gem_userptr {
uintptr_t ptr; uintptr_t ptr;
unsigned read_only :1; unsigned read_only :1;
...@@ -2326,8 +2315,6 @@ struct i915_params { ...@@ -2326,8 +2315,6 @@ struct i915_params {
extern struct i915_params i915 __read_mostly; extern struct i915_params i915 __read_mostly;
/* i915_dma.c */ /* i915_dma.c */
void i915_update_dri1_breadcrumb(struct drm_device *dev);
extern void i915_kernel_lost_context(struct drm_device * dev);
extern int i915_driver_load(struct drm_device *, unsigned long flags); extern int i915_driver_load(struct drm_device *, unsigned long flags);
extern int i915_driver_unload(struct drm_device *); extern int i915_driver_unload(struct drm_device *);
extern int i915_driver_open(struct drm_device *dev, struct drm_file *file); extern int i915_driver_open(struct drm_device *dev, struct drm_file *file);
...@@ -2341,9 +2328,6 @@ extern int i915_driver_device_is_agp(struct drm_device * dev); ...@@ -2341,9 +2328,6 @@ extern int i915_driver_device_is_agp(struct drm_device * dev);
extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, extern long i915_compat_ioctl(struct file *filp, unsigned int cmd,
unsigned long arg); unsigned long arg);
#endif #endif
extern int i915_emit_box(struct drm_device *dev,
struct drm_clip_rect *box,
int DR1, int DR4);
extern int intel_gpu_reset(struct drm_device *dev); extern int intel_gpu_reset(struct drm_device *dev);
extern int i915_reset(struct drm_device *dev); extern int i915_reset(struct drm_device *dev);
extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv); extern unsigned long i915_chipset_val(struct drm_i915_private *dev_priv);
...@@ -2395,8 +2379,6 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv, ...@@ -2395,8 +2379,6 @@ void ibx_display_interrupt_update(struct drm_i915_private *dev_priv,
ibx_display_interrupt_update((dev_priv), (bits), 0) ibx_display_interrupt_update((dev_priv), (bits), 0)
/* i915_gem.c */ /* i915_gem.c */
int i915_gem_init_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_create_ioctl(struct drm_device *dev, void *data, int i915_gem_create_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
int i915_gem_pread_ioctl(struct drm_device *dev, void *data, int i915_gem_pread_ioctl(struct drm_device *dev, void *data,
...@@ -2443,10 +2425,6 @@ int i915_gem_throttle_ioctl(struct drm_device *dev, void *data, ...@@ -2443,10 +2425,6 @@ int i915_gem_throttle_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
int i915_gem_madvise_ioctl(struct drm_device *dev, void *data, int i915_gem_madvise_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
int i915_gem_entervt_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_leavevt_ioctl(struct drm_device *dev, void *data,
struct drm_file *file_priv);
int i915_gem_set_tiling(struct drm_device *dev, void *data, int i915_gem_set_tiling(struct drm_device *dev, void *data,
struct drm_file *file_priv); struct drm_file *file_priv);
int i915_gem_get_tiling(struct drm_device *dev, void *data, int i915_gem_get_tiling(struct drm_device *dev, void *data,
...@@ -2489,7 +2467,6 @@ int __must_check i915_vma_unbind(struct i915_vma *vma); ...@@ -2489,7 +2467,6 @@ int __must_check i915_vma_unbind(struct i915_vma *vma);
int i915_gem_object_put_pages(struct drm_i915_gem_object *obj); int i915_gem_object_put_pages(struct drm_i915_gem_object *obj);
void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv); void i915_gem_release_all_mmaps(struct drm_i915_private *dev_priv);
void i915_gem_release_mmap(struct drm_i915_gem_object *obj); void i915_gem_release_mmap(struct drm_i915_gem_object *obj);
void i915_gem_lastclose(struct drm_device *dev);
int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj, int i915_gem_obj_prepare_shmem_read(struct drm_i915_gem_object *obj,
int *needs_clflush); int *needs_clflush);
...@@ -2956,8 +2933,8 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine); ...@@ -2956,8 +2933,8 @@ void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv, int fw_engine);
void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine); void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv, int fw_engine);
void assert_force_wake_inactive(struct drm_i915_private *dev_priv); void assert_force_wake_inactive(struct drm_i915_private *dev_priv);
int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val); int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val);
int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val); int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val);
/* intel_sideband.c */ /* intel_sideband.c */
u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr); u32 vlv_punit_read(struct drm_i915_private *dev_priv, u8 addr);
......
This diff is collapsed.
...@@ -88,6 +88,7 @@ ...@@ -88,6 +88,7 @@
#include <drm/drmP.h> #include <drm/drmP.h>
#include <drm/i915_drm.h> #include <drm/i915_drm.h>
#include "i915_drv.h" #include "i915_drv.h"
#include "i915_trace.h"
/* This is a HW constraint. The value below is the largest known requirement /* This is a HW constraint. The value below is the largest known requirement
* I've seen in a spec to date, and that was a workaround for a non-shipping * I've seen in a spec to date, and that was a workaround for a non-shipping
...@@ -137,6 +138,8 @@ void i915_gem_context_free(struct kref *ctx_ref) ...@@ -137,6 +138,8 @@ void i915_gem_context_free(struct kref *ctx_ref)
struct intel_context *ctx = container_of(ctx_ref, struct intel_context *ctx = container_of(ctx_ref,
typeof(*ctx), ref); typeof(*ctx), ref);
trace_i915_context_free(ctx);
if (i915.enable_execlists) if (i915.enable_execlists)
intel_lr_context_free(ctx); intel_lr_context_free(ctx);
...@@ -274,6 +277,8 @@ i915_gem_create_context(struct drm_device *dev, ...@@ -274,6 +277,8 @@ i915_gem_create_context(struct drm_device *dev,
ctx->ppgtt = ppgtt; ctx->ppgtt = ppgtt;
} }
trace_i915_context_create(ctx);
return ctx; return ctx;
err_unpin: err_unpin:
...@@ -549,6 +554,7 @@ static int do_switch(struct intel_engine_cs *ring, ...@@ -549,6 +554,7 @@ static int do_switch(struct intel_engine_cs *ring,
from = ring->last_context; from = ring->last_context;
if (to->ppgtt) { if (to->ppgtt) {
trace_switch_mm(ring, to);
ret = to->ppgtt->switch_mm(to->ppgtt, ring); ret = to->ppgtt->switch_mm(to->ppgtt, ring);
if (ret) if (ret)
goto unpin_out; goto unpin_out;
...@@ -629,7 +635,7 @@ static int do_switch(struct intel_engine_cs *ring, ...@@ -629,7 +635,7 @@ static int do_switch(struct intel_engine_cs *ring,
if (uninitialized) { if (uninitialized) {
if (ring->init_context) { if (ring->init_context) {
ret = ring->init_context(ring); ret = ring->init_context(ring, to);
if (ret) if (ret)
DRM_ERROR("ring init context: %d\n", ret); DRM_ERROR("ring init context: %d\n", ret);
} }
......
...@@ -1023,6 +1023,47 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev, ...@@ -1023,6 +1023,47 @@ i915_reset_gen7_sol_offsets(struct drm_device *dev,
return 0; return 0;
} }
static int
i915_emit_box(struct intel_engine_cs *ring,
struct drm_clip_rect *box,
int DR1, int DR4)
{
int ret;
if (box->y2 <= box->y1 || box->x2 <= box->x1 ||
box->y2 <= 0 || box->x2 <= 0) {
DRM_ERROR("Bad box %d,%d..%d,%d\n",
box->x1, box->y1, box->x2, box->y2);
return -EINVAL;
}
if (INTEL_INFO(ring->dev)->gen >= 4) {
ret = intel_ring_begin(ring, 4);
if (ret)
return ret;
intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO_I965);
intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
intel_ring_emit(ring, DR4);
} else {
ret = intel_ring_begin(ring, 6);
if (ret)
return ret;
intel_ring_emit(ring, GFX_OP_DRAWRECT_INFO);
intel_ring_emit(ring, DR1);
intel_ring_emit(ring, (box->x1 & 0xffff) | box->y1 << 16);
intel_ring_emit(ring, ((box->x2 - 1) & 0xffff) | (box->y2 - 1) << 16);
intel_ring_emit(ring, DR4);
intel_ring_emit(ring, 0);
}
intel_ring_advance(ring);
return 0;
}
int int
i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
struct intel_engine_cs *ring, struct intel_engine_cs *ring,
...@@ -1151,7 +1192,7 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file, ...@@ -1151,7 +1192,7 @@ i915_gem_ringbuffer_submission(struct drm_device *dev, struct drm_file *file,
exec_len = args->batch_len; exec_len = args->batch_len;
if (cliprects) { if (cliprects) {
for (i = 0; i < args->num_cliprects; i++) { for (i = 0; i < args->num_cliprects; i++) {
ret = i915_emit_box(dev, &cliprects[i], ret = i915_emit_box(ring, &cliprects[i],
args->DR1, args->DR4); args->DR1, args->DR4);
if (ret) if (ret)
goto error; goto error;
...@@ -1300,12 +1341,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data, ...@@ -1300,12 +1341,6 @@ i915_gem_do_execbuffer(struct drm_device *dev, void *data,
if (ret) if (ret)
goto pre_mutex_err; goto pre_mutex_err;
if (dev_priv->ums.mm_suspended) {
mutex_unlock(&dev->struct_mutex);
ret = -EBUSY;
goto pre_mutex_err;
}
ctx = i915_gem_validate_context(dev, file, ring, ctx_id); ctx = i915_gem_validate_context(dev, file, ring, ctx_id);
if (IS_ERR(ctx)) { if (IS_ERR(ctx)) {
mutex_unlock(&dev->struct_mutex); mutex_unlock(&dev->struct_mutex);
......
...@@ -43,7 +43,12 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt) ...@@ -43,7 +43,12 @@ static int sanitize_enable_ppgtt(struct drm_device *dev, int enable_ppgtt)
if (IS_GEN8(dev)) if (IS_GEN8(dev))
has_full_ppgtt = false; /* XXX why? */ has_full_ppgtt = false; /* XXX why? */
if (enable_ppgtt == 0 || !has_aliasing_ppgtt) /*
* We don't allow disabling PPGTT for gen9+ as it's a requirement for
* execlists, the sole mechanism available to submit work.
*/
if (INTEL_INFO(dev)->gen < 9 &&
(enable_ppgtt == 0 || !has_aliasing_ppgtt))
return 0; return 0;
if (enable_ppgtt == 1) if (enable_ppgtt == 1)
...@@ -164,9 +169,6 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr, ...@@ -164,9 +169,6 @@ static gen6_gtt_pte_t byt_pte_encode(dma_addr_t addr,
gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0; gen6_gtt_pte_t pte = valid ? GEN6_PTE_VALID : 0;
pte |= GEN6_PTE_ADDR_ENCODE(addr); pte |= GEN6_PTE_ADDR_ENCODE(addr);
/* Mark the page as writeable. Other platforms don't have a
* setting for read-only/writable, so this matches that behavior.
*/
if (!(flags & PTE_READ_ONLY)) if (!(flags & PTE_READ_ONLY))
pte |= BYT_PTE_WRITEABLE; pte |= BYT_PTE_WRITEABLE;
...@@ -1174,6 +1176,8 @@ i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv) ...@@ -1174,6 +1176,8 @@ i915_ppgtt_create(struct drm_device *dev, struct drm_i915_file_private *fpriv)
ppgtt->file_priv = fpriv; ppgtt->file_priv = fpriv;
trace_i915_ppgtt_create(&ppgtt->base);
return ppgtt; return ppgtt;
} }
...@@ -1182,6 +1186,8 @@ void i915_ppgtt_release(struct kref *kref) ...@@ -1182,6 +1186,8 @@ void i915_ppgtt_release(struct kref *kref)
struct i915_hw_ppgtt *ppgtt = struct i915_hw_ppgtt *ppgtt =
container_of(kref, struct i915_hw_ppgtt, ref); container_of(kref, struct i915_hw_ppgtt, ref);
trace_i915_ppgtt_release(&ppgtt->base);
/* vmas should already be unbound */ /* vmas should already be unbound */
WARN_ON(!list_empty(&ppgtt->base.active_list)); WARN_ON(!list_empty(&ppgtt->base.active_list));
WARN_ON(!list_empty(&ppgtt->base.inactive_list)); WARN_ON(!list_empty(&ppgtt->base.inactive_list));
...@@ -1658,7 +1664,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node, ...@@ -1658,7 +1664,7 @@ static void i915_gtt_color_adjust(struct drm_mm_node *node,
} }
} }
int i915_gem_setup_global_gtt(struct drm_device *dev, static int i915_gem_setup_global_gtt(struct drm_device *dev,
unsigned long start, unsigned long start,
unsigned long mappable_end, unsigned long mappable_end,
unsigned long end) unsigned long end)
...@@ -1952,9 +1958,17 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv) ...@@ -1952,9 +1958,17 @@ static void chv_setup_private_ppat(struct drm_i915_private *dev_priv)
* Only the snoop bit has meaning for CHV, the rest is * Only the snoop bit has meaning for CHV, the rest is
* ignored. * ignored.
* *
* Note that the harware enforces snooping for all page * The hardware will never snoop for certain types of accesses:
* table accesses. The snoop bit is actually ignored for * - CPU GTT (GMADR->GGTT->no snoop->memory)
* PDEs. * - PPGTT page tables
* - some other special cycles
*
* As with BDW, we also need to consider the following for GT accesses:
* "For GGTT, there is NO pat_sel[2:0] from the entry,
* so RTL will always use the value corresponding to
* pat_sel = 000".
* Which means we must set the snoop bit in PAT entry 0
* in order to keep the global status page working.
*/ */
pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) | pat = GEN8_PPAT(0, CHV_PPAT_SNOOP) |
GEN8_PPAT(1, 0) | GEN8_PPAT(1, 0) |
......
...@@ -274,8 +274,6 @@ struct i915_hw_ppgtt { ...@@ -274,8 +274,6 @@ struct i915_hw_ppgtt {
int i915_gem_gtt_init(struct drm_device *dev); int i915_gem_gtt_init(struct drm_device *dev);
void i915_gem_init_global_gtt(struct drm_device *dev); void i915_gem_init_global_gtt(struct drm_device *dev);
int i915_gem_setup_global_gtt(struct drm_device *dev, unsigned long start,
unsigned long mappable_end, unsigned long end);
void i915_global_gtt_cleanup(struct drm_device *dev); void i915_global_gtt_cleanup(struct drm_device *dev);
......
...@@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev) ...@@ -178,6 +178,15 @@ i915_gem_detect_bit_6_swizzle(struct drm_device *dev)
} }
break; break;
} }
/* check for L-shaped memory aka modified enhanced addressing */
if (IS_GEN4(dev)) {
uint32_t ddc2 = I915_READ(DCC2);
if (!(ddc2 & DCC2_MODIFIED_ENHANCED_DISABLE))
dev_priv->quirks |= QUIRK_PIN_SWIZZLED_PAGES;
}
if (dcc == 0xffffffff) { if (dcc == 0xffffffff) {
DRM_ERROR("Couldn't read from MCHBAR. " DRM_ERROR("Couldn't read from MCHBAR. "
"Disabling tiling.\n"); "Disabling tiling.\n");
...@@ -380,6 +389,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data, ...@@ -380,6 +389,15 @@ i915_gem_set_tiling(struct drm_device *dev, void *data,
ret = i915_gem_object_ggtt_unbind(obj); ret = i915_gem_object_ggtt_unbind(obj);
if (ret == 0) { if (ret == 0) {
if (obj->pages &&
obj->madv == I915_MADV_WILLNEED &&
dev_priv->quirks & QUIRK_PIN_SWIZZLED_PAGES) {
if (args->tiling_mode == I915_TILING_NONE)
i915_gem_object_unpin_pages(obj);
if (obj->tiling_mode == I915_TILING_NONE)
i915_gem_object_pin_pages(obj);
}
obj->fence_dirty = obj->fence_dirty =
obj->last_fenced_seqno || obj->last_fenced_seqno ||
obj->fence_reg != I915_FENCE_REG_NONE; obj->fence_reg != I915_FENCE_REG_NONE;
......
...@@ -242,11 +242,15 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a) ...@@ -242,11 +242,15 @@ static const char *hangcheck_action_to_str(enum intel_ring_hangcheck_action a)
static void i915_ring_error_state(struct drm_i915_error_state_buf *m, static void i915_ring_error_state(struct drm_i915_error_state_buf *m,
struct drm_device *dev, struct drm_device *dev,
struct drm_i915_error_ring *ring) struct drm_i915_error_state *error,
int ring_idx)
{ {
struct drm_i915_error_ring *ring = &error->ring[ring_idx];
if (!ring->valid) if (!ring->valid)
return; return;
err_printf(m, "%s command stream:\n", ring_str(ring_idx));
err_printf(m, " HEAD: 0x%08x\n", ring->head); err_printf(m, " HEAD: 0x%08x\n", ring->head);
err_printf(m, " TAIL: 0x%08x\n", ring->tail); err_printf(m, " TAIL: 0x%08x\n", ring->tail);
err_printf(m, " CTL: 0x%08x\n", ring->ctl); err_printf(m, " CTL: 0x%08x\n", ring->ctl);
...@@ -388,10 +392,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m, ...@@ -388,10 +392,8 @@ int i915_error_state_to_str(struct drm_i915_error_state_buf *m,
if (INTEL_INFO(dev)->gen == 7) if (INTEL_INFO(dev)->gen == 7)
err_printf(m, "ERR_INT: 0x%08x\n", error->err_int); err_printf(m, "ERR_INT: 0x%08x\n", error->err_int);
for (i = 0; i < ARRAY_SIZE(error->ring); i++) { for (i = 0; i < ARRAY_SIZE(error->ring); i++)
err_printf(m, "%s command stream:\n", ring_str(i)); i915_ring_error_state(m, dev, error, i);
i915_ring_error_state(m, dev, &error->ring[i]);
}
for (i = 0; i < error->vm_count; i++) { for (i = 0; i < error->vm_count; i++) {
err_printf(m, "vm[%d]\n", i); err_printf(m, "vm[%d]\n", i);
...@@ -807,9 +809,8 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv, ...@@ -807,9 +809,8 @@ static void gen8_record_semaphore_state(struct drm_i915_private *dev_priv,
if (!error->semaphore_obj) if (!error->semaphore_obj)
error->semaphore_obj = error->semaphore_obj =
i915_error_object_create(dev_priv, i915_error_ggtt_object_create(dev_priv,
dev_priv->semaphore_obj, dev_priv->semaphore_obj);
&dev_priv->gtt.base);
for_each_ring(to, dev_priv, i) { for_each_ring(to, dev_priv, i) {
int idx; int idx;
......
This diff is collapsed.
...@@ -248,6 +248,16 @@ ...@@ -248,6 +248,16 @@
#define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19) #define MI_DISPLAY_FLIP_IVB_SPRITE_B (3 << 19)
#define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19) #define MI_DISPLAY_FLIP_IVB_PLANE_C (4 << 19)
#define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19) #define MI_DISPLAY_FLIP_IVB_SPRITE_C (5 << 19)
/* SKL ones */
#define MI_DISPLAY_FLIP_SKL_PLANE_1_A (0 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_1_B (1 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_1_C (2 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_2_A (4 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_2_B (5 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_2_C (6 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_3_A (7 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_3_B (8 << 8)
#define MI_DISPLAY_FLIP_SKL_PLANE_3_C (9 << 8)
#define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */ #define MI_SEMAPHORE_MBOX MI_INSTR(0x16, 1) /* gen6, gen7 */
#define MI_SEMAPHORE_GLOBAL_GTT (1<<22) #define MI_SEMAPHORE_GLOBAL_GTT (1<<22)
#define MI_SEMAPHORE_UPDATE (1<<21) #define MI_SEMAPHORE_UPDATE (1<<21)
...@@ -314,6 +324,8 @@ ...@@ -314,6 +324,8 @@
#define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */ #define MI_BATCH_GTT (2<<6) /* aliased with (1<<7) on gen4 */
#define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1) #define MI_BATCH_BUFFER_START_GEN8 MI_INSTR(0x31, 1)
#define MI_PREDICATE_SRC0 (0x2400)
#define MI_PREDICATE_SRC1 (0x2408)
#define MI_PREDICATE_RESULT_2 (0x2214) #define MI_PREDICATE_RESULT_2 (0x2214)
#define LOWER_SLICE_ENABLED (1<<0) #define LOWER_SLICE_ENABLED (1<<0)
...@@ -564,6 +576,7 @@ enum punit_power_well { ...@@ -564,6 +576,7 @@ enum punit_power_well {
#define PUNIT_REG_GPU_LFM 0xd3 #define PUNIT_REG_GPU_LFM 0xd3
#define PUNIT_REG_GPU_FREQ_REQ 0xd4 #define PUNIT_REG_GPU_FREQ_REQ 0xd4
#define PUNIT_REG_GPU_FREQ_STS 0xd8 #define PUNIT_REG_GPU_FREQ_STS 0xd8
#define GPLLENABLE (1<<4)
#define GENFREQSTATUS (1<<0) #define GENFREQSTATUS (1<<0)
#define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc #define PUNIT_REG_MEDIA_TURBO_FREQ_REQ 0xdc
#define PUNIT_REG_CZ_TIMESTAMP 0xce #define PUNIT_REG_CZ_TIMESTAMP 0xce
...@@ -2030,6 +2043,8 @@ enum punit_power_well { ...@@ -2030,6 +2043,8 @@ enum punit_power_well {
#define DCC_ADDRESSING_MODE_MASK (3 << 0) #define DCC_ADDRESSING_MODE_MASK (3 << 0)
#define DCC_CHANNEL_XOR_DISABLE (1 << 10) #define DCC_CHANNEL_XOR_DISABLE (1 << 10)
#define DCC_CHANNEL_XOR_BIT_17 (1 << 9) #define DCC_CHANNEL_XOR_BIT_17 (1 << 9)
#define DCC2 0x10204
#define DCC2_MODIFIED_ENHANCED_DISABLE (1 << 20)
/* Pineview MCH register contains DDR3 setting */ /* Pineview MCH register contains DDR3 setting */
#define CSHRDDR3CTL 0x101a8 #define CSHRDDR3CTL 0x101a8
...@@ -2313,7 +2328,6 @@ enum punit_power_well { ...@@ -2313,7 +2328,6 @@ enum punit_power_well {
#define GEN6_GT_THREAD_STATUS_REG 0x13805c #define GEN6_GT_THREAD_STATUS_REG 0x13805c
#define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7 #define GEN6_GT_THREAD_STATUS_CORE_MASK 0x7
#define GEN6_GT_THREAD_STATUS_CORE_MASK_HSW (0x7 | (0x07 << 16))
#define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948) #define GEN6_GT_PERF_STATUS (MCHBAR_MIRROR_BASE_SNB + 0x5948)
#define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994) #define GEN6_RP_STATE_LIMITS (MCHBAR_MIRROR_BASE_SNB + 0x5994)
...@@ -4904,6 +4918,18 @@ enum punit_power_well { ...@@ -4904,6 +4918,18 @@ enum punit_power_well {
#define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE) #define PF_VSCALE(pipe) _PIPE(pipe, _PFA_VSCALE, _PFB_VSCALE)
#define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE) #define PF_HSCALE(pipe) _PIPE(pipe, _PFA_HSCALE, _PFB_HSCALE)
#define _PSA_CTL 0x68180
#define _PSB_CTL 0x68980
#define PS_ENABLE (1<<31)
#define _PSA_WIN_SZ 0x68174
#define _PSB_WIN_SZ 0x68974
#define _PSA_WIN_POS 0x68170
#define _PSB_WIN_POS 0x68970
#define PS_CTL(pipe) _PIPE(pipe, _PSA_CTL, _PSB_CTL)
#define PS_WIN_SZ(pipe) _PIPE(pipe, _PSA_WIN_SZ, _PSB_WIN_SZ)
#define PS_WIN_POS(pipe) _PIPE(pipe, _PSA_WIN_POS, _PSB_WIN_POS)
/* legacy palette */ /* legacy palette */
#define _LGC_PALETTE_A 0x4a000 #define _LGC_PALETTE_A 0x4a000
#define _LGC_PALETTE_B 0x4a800 #define _LGC_PALETTE_B 0x4a800
...@@ -5048,6 +5074,9 @@ enum punit_power_well { ...@@ -5048,6 +5074,9 @@ enum punit_power_well {
#define GEN8_DE_PORT_IIR 0x44448 #define GEN8_DE_PORT_IIR 0x44448
#define GEN8_DE_PORT_IER 0x4444c #define GEN8_DE_PORT_IER 0x4444c
#define GEN8_PORT_DP_A_HOTPLUG (1 << 3) #define GEN8_PORT_DP_A_HOTPLUG (1 << 3)
#define GEN9_AUX_CHANNEL_D (1 << 27)
#define GEN9_AUX_CHANNEL_C (1 << 26)
#define GEN9_AUX_CHANNEL_B (1 << 25)
#define GEN8_AUX_CHANNEL_A (1 << 0) #define GEN8_AUX_CHANNEL_A (1 << 0)
#define GEN8_DE_MISC_ISR 0x44460 #define GEN8_DE_MISC_ISR 0x44460
...@@ -5131,6 +5160,7 @@ enum punit_power_well { ...@@ -5131,6 +5160,7 @@ enum punit_power_well {
/* GEN8 chicken */ /* GEN8 chicken */
#define HDC_CHICKEN0 0x7300 #define HDC_CHICKEN0 0x7300
#define HDC_FORCE_NON_COHERENT (1<<4) #define HDC_FORCE_NON_COHERENT (1<<4)
#define HDC_DONOT_FETCH_MEM_WHEN_MASKED (1<<11)
#define HDC_FENCE_DEST_SLM_DISABLE (1<<14) #define HDC_FENCE_DEST_SLM_DISABLE (1<<14)
/* WaCatErrorRejectionIssue */ /* WaCatErrorRejectionIssue */
...@@ -6010,11 +6040,12 @@ enum punit_power_well { ...@@ -6010,11 +6040,12 @@ enum punit_power_well {
#define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5) #define GEN6_ENCODE_RC6_VID(mv) (((mv) - 245) / 5)
#define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245) #define GEN6_DECODE_RC6_VID(vids) (((vids) * 5) + 245)
#define DISPLAY_IPS_CONTROL 0x19 #define DISPLAY_IPS_CONTROL 0x19
#define HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL 0x1A
#define GEN6_PCODE_DATA 0x138128 #define GEN6_PCODE_DATA 0x138128
#define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8 #define GEN6_PCODE_FREQ_IA_RATIO_SHIFT 8
#define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16 #define GEN6_PCODE_FREQ_RING_RATIO_SHIFT 16
#define GEN6_PCODE_DATA1 0x13812C
#define GEN9_PCODE_DATA1 0x13812C
#define GEN9_PCODE_READ_MEM_LATENCY 0x6 #define GEN9_PCODE_READ_MEM_LATENCY 0x6
#define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF #define GEN9_MEM_LATENCY_LEVEL_MASK 0xFF
#define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8 #define GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT 8
...@@ -6427,6 +6458,83 @@ enum punit_power_well { ...@@ -6427,6 +6458,83 @@ enum punit_power_well {
#define LCPLL_CD_SOURCE_FCLK (1<<21) #define LCPLL_CD_SOURCE_FCLK (1<<21)
#define LCPLL_CD_SOURCE_FCLK_DONE (1<<19) #define LCPLL_CD_SOURCE_FCLK_DONE (1<<19)
/*
* SKL Clocks
*/
/* CDCLK_CTL */
#define CDCLK_CTL 0x46000
#define CDCLK_FREQ_SEL_MASK (3<<26)
#define CDCLK_FREQ_450_432 (0<<26)
#define CDCLK_FREQ_540 (1<<26)
#define CDCLK_FREQ_337_308 (2<<26)
#define CDCLK_FREQ_675_617 (3<<26)
#define CDCLK_FREQ_DECIMAL_MASK (0x7ff)
/* LCPLL_CTL */
#define LCPLL1_CTL 0x46010
#define LCPLL2_CTL 0x46014
#define LCPLL_PLL_ENABLE (1<<31)
/* DPLL control1 */
#define DPLL_CTRL1 0x6C058
#define DPLL_CTRL1_HDMI_MODE(id) (1<<((id)*6+5))
#define DPLL_CTRL1_SSC(id) (1<<((id)*6+4))
#define DPLL_CRTL1_LINK_RATE_MASK(id) (7<<((id)*6+1))
#define DPLL_CRTL1_LINK_RATE_SHIFT(id) ((id)*6+1)
#define DPLL_CRTL1_LINK_RATE(linkrate, id) ((linkrate)<<((id)*6+1))
#define DPLL_CTRL1_OVERRIDE(id) (1<<((id)*6))
#define DPLL_CRTL1_LINK_RATE_2700 0
#define DPLL_CRTL1_LINK_RATE_1350 1
#define DPLL_CRTL1_LINK_RATE_810 2
#define DPLL_CRTL1_LINK_RATE_1620 3
#define DPLL_CRTL1_LINK_RATE_1080 4
#define DPLL_CRTL1_LINK_RATE_2160 5
/* DPLL control2 */
#define DPLL_CTRL2 0x6C05C
#define DPLL_CTRL2_DDI_CLK_OFF(port) (1<<(port+15))
#define DPLL_CTRL2_DDI_CLK_SEL_MASK(port) (3<<((port)*3+1))
#define DPLL_CTRL2_DDI_CLK_SEL_SHIFT(port) ((port)*3+1)
#define DPLL_CTRL2_DDI_CLK_SEL(clk, port) (clk<<((port)*3+1))
#define DPLL_CTRL2_DDI_SEL_OVERRIDE(port) (1<<((port)*3))
/* DPLL Status */
#define DPLL_STATUS 0x6C060
#define DPLL_LOCK(id) (1<<((id)*8))
/* DPLL cfg */
#define DPLL1_CFGCR1 0x6C040
#define DPLL2_CFGCR1 0x6C048
#define DPLL3_CFGCR1 0x6C050
#define DPLL_CFGCR1_FREQ_ENABLE (1<<31)
#define DPLL_CFGCR1_DCO_FRACTION_MASK (0x7fff<<9)
#define DPLL_CFGCR1_DCO_FRACTION(x) (x<<9)
#define DPLL_CFGCR1_DCO_INTEGER_MASK (0x1ff)
#define DPLL1_CFGCR2 0x6C044
#define DPLL2_CFGCR2 0x6C04C
#define DPLL3_CFGCR2 0x6C054
#define DPLL_CFGCR2_QDIV_RATIO_MASK (0xff<<8)
#define DPLL_CFGCR2_QDIV_RATIO(x) (x<<8)
#define DPLL_CFGCR2_QDIV_MODE(x) (x<<7)
#define DPLL_CFGCR2_KDIV_MASK (3<<5)
#define DPLL_CFGCR2_KDIV(x) (x<<5)
#define DPLL_CFGCR2_KDIV_5 (0<<5)
#define DPLL_CFGCR2_KDIV_2 (1<<5)
#define DPLL_CFGCR2_KDIV_3 (2<<5)
#define DPLL_CFGCR2_KDIV_1 (3<<5)
#define DPLL_CFGCR2_PDIV_MASK (7<<2)
#define DPLL_CFGCR2_PDIV(x) (x<<2)
#define DPLL_CFGCR2_PDIV_1 (0<<2)
#define DPLL_CFGCR2_PDIV_2 (1<<2)
#define DPLL_CFGCR2_PDIV_3 (2<<2)
#define DPLL_CFGCR2_PDIV_7 (4<<2)
#define DPLL_CFGCR2_CENTRAL_FREQ_MASK (3)
#define GET_CFG_CR1_REG(id) (DPLL1_CFGCR1 + (id - SKL_DPLL1) * 8)
#define GET_CFG_CR2_REG(id) (DPLL1_CFGCR2 + (id - SKL_DPLL1) * 8)
/* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register, /* Please see hsw_read_dcomp() and hsw_write_dcomp() before using this register,
* since on HSW we can't write to it using I915_WRITE. */ * since on HSW we can't write to it using I915_WRITE. */
#define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C) #define D_COMP_HSW (MCHBAR_MIRROR_BASE_SNB + 0x5F0C)
......
...@@ -203,34 +203,19 @@ static void i915_save_display(struct drm_device *dev) ...@@ -203,34 +203,19 @@ static void i915_save_display(struct drm_device *dev)
i915_save_display_reg(dev); i915_save_display_reg(dev);
/* LVDS state */ /* LVDS state */
if (HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS); dev_priv->regfile.saveLVDS = I915_READ(PCH_LVDS);
} else if (IS_VALLEYVIEW(dev)) { else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->regfile.saveBLC_HIST_CTL =
I915_READ(VLV_BLC_HIST_CTL(PIPE_A));
dev_priv->regfile.saveBLC_HIST_CTL_B =
I915_READ(VLV_BLC_HIST_CTL(PIPE_B));
} else {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
if (IS_MOBILE(dev) && !IS_I830(dev))
dev_priv->regfile.saveLVDS = I915_READ(LVDS); dev_priv->regfile.saveLVDS = I915_READ(LVDS);
}
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev))
dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
/* Panel power sequencer */
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PCH_PP_CONTROL);
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS); dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PCH_PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PCH_PP_OFF_DELAYS);
dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR); dev_priv->regfile.savePP_DIVISOR = I915_READ(PCH_PP_DIVISOR);
} else { } else if (!IS_VALLEYVIEW(dev)) {
dev_priv->regfile.savePP_CONTROL = I915_READ(PP_CONTROL);
dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS); dev_priv->regfile.savePP_ON_DELAYS = I915_READ(PP_ON_DELAYS);
dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS); dev_priv->regfile.savePP_OFF_DELAYS = I915_READ(PP_OFF_DELAYS);
dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR); dev_priv->regfile.savePP_DIVISOR = I915_READ(PP_DIVISOR);
...@@ -259,29 +244,19 @@ static void i915_restore_display(struct drm_device *dev) ...@@ -259,29 +244,19 @@ static void i915_restore_display(struct drm_device *dev)
if (drm_core_check_feature(dev, DRIVER_MODESET)) if (drm_core_check_feature(dev, DRIVER_MODESET))
mask = ~LVDS_PORT_EN; mask = ~LVDS_PORT_EN;
/* LVDS state */
if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask); I915_WRITE(PCH_LVDS, dev_priv->regfile.saveLVDS & mask);
else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) else if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask); I915_WRITE(LVDS, dev_priv->regfile.saveLVDS & mask);
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) /* Panel power sequencer */
I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
if (HAS_PCH_SPLIT(dev)) { if (HAS_PCH_SPLIT(dev)) {
I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PCH_PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PCH_PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PCH_PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL); I915_WRITE(PCH_PP_CONTROL, dev_priv->regfile.savePP_CONTROL);
I915_WRITE(RSTDBYCTL, } else if (!IS_VALLEYVIEW(dev)) {
dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
} else if (IS_VALLEYVIEW(dev)) {
I915_WRITE(VLV_BLC_HIST_CTL(PIPE_A),
dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(VLV_BLC_HIST_CTL(PIPE_B),
dev_priv->regfile.saveBLC_HIST_CTL);
} else {
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS); I915_WRITE(PP_ON_DELAYS, dev_priv->regfile.savePP_ON_DELAYS);
I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS); I915_WRITE(PP_OFF_DELAYS, dev_priv->regfile.savePP_OFF_DELAYS);
I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR); I915_WRITE(PP_DIVISOR, dev_priv->regfile.savePP_DIVISOR);
...@@ -368,6 +343,8 @@ int i915_restore_state(struct drm_device *dev) ...@@ -368,6 +343,8 @@ int i915_restore_state(struct drm_device *dev)
I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR); I915_WRITE(_FDI_RXA_IMR, dev_priv->regfile.saveFDI_RXA_IMR);
I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR); I915_WRITE(_FDI_RXB_IMR, dev_priv->regfile.saveFDI_RXB_IMR);
I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG); I915_WRITE(PCH_PORT_HOTPLUG, dev_priv->regfile.savePCH_PORT_HOTPLUG);
I915_WRITE(RSTDBYCTL,
dev_priv->regfile.saveMCHBAR_RENDER_STANDBY);
} else { } else {
I915_WRITE(IER, dev_priv->regfile.saveIER); I915_WRITE(IER, dev_priv->regfile.saveIER);
I915_WRITE(IMR, dev_priv->regfile.saveIMR); I915_WRITE(IMR, dev_priv->regfile.saveIMR);
......
...@@ -587,6 +587,110 @@ TRACE_EVENT(intel_gpu_freq_change, ...@@ -587,6 +587,110 @@ TRACE_EVENT(intel_gpu_freq_change,
TP_printk("new_freq=%u", __entry->freq) TP_printk("new_freq=%u", __entry->freq)
); );
/**
* DOC: i915_ppgtt_create and i915_ppgtt_release tracepoints
*
* With full ppgtt enabled each process using drm will allocate at least one
* translation table. With these traces it is possible to keep track of the
* allocation and of the lifetime of the tables; this can be used during
* testing/debug to verify that we are not leaking ppgtts.
* These traces identify the ppgtt through the vm pointer, which is also printed
* by the i915_vma_bind and i915_vma_unbind tracepoints.
*/
DECLARE_EVENT_CLASS(i915_ppgtt,
TP_PROTO(struct i915_address_space *vm),
TP_ARGS(vm),
TP_STRUCT__entry(
__field(struct i915_address_space *, vm)
__field(u32, dev)
),
TP_fast_assign(
__entry->vm = vm;
__entry->dev = vm->dev->primary->index;
),
TP_printk("dev=%u, vm=%p", __entry->dev, __entry->vm)
)
DEFINE_EVENT(i915_ppgtt, i915_ppgtt_create,
TP_PROTO(struct i915_address_space *vm),
TP_ARGS(vm)
);
DEFINE_EVENT(i915_ppgtt, i915_ppgtt_release,
TP_PROTO(struct i915_address_space *vm),
TP_ARGS(vm)
);
/**
* DOC: i915_context_create and i915_context_free tracepoints
*
* These tracepoints are used to track creation and deletion of contexts.
* If full ppgtt is enabled, they also print the address of the vm assigned to
* the context.
*/
DECLARE_EVENT_CLASS(i915_context,
TP_PROTO(struct intel_context *ctx),
TP_ARGS(ctx),
TP_STRUCT__entry(
__field(u32, dev)
__field(struct intel_context *, ctx)
__field(struct i915_address_space *, vm)
),
TP_fast_assign(
__entry->ctx = ctx;
__entry->vm = ctx->ppgtt ? &ctx->ppgtt->base : NULL;
__entry->dev = ctx->file_priv->dev_priv->dev->primary->index;
),
TP_printk("dev=%u, ctx=%p, ctx_vm=%p",
__entry->dev, __entry->ctx, __entry->vm)
)
DEFINE_EVENT(i915_context, i915_context_create,
TP_PROTO(struct intel_context *ctx),
TP_ARGS(ctx)
);
DEFINE_EVENT(i915_context, i915_context_free,
TP_PROTO(struct intel_context *ctx),
TP_ARGS(ctx)
);
/**
* DOC: switch_mm tracepoint
*
* This tracepoint allows tracking of the mm switch, which is an important point
* in the lifetime of the vm in the legacy submission path. This tracepoint is
* called only if full ppgtt is enabled.
*/
TRACE_EVENT(switch_mm,
TP_PROTO(struct intel_engine_cs *ring, struct intel_context *to),
TP_ARGS(ring, to),
TP_STRUCT__entry(
__field(u32, ring)
__field(struct intel_context *, to)
__field(struct i915_address_space *, vm)
__field(u32, dev)
),
TP_fast_assign(
__entry->ring = ring->id;
__entry->to = to;
__entry->vm = to->ppgtt? &to->ppgtt->base : NULL;
__entry->dev = ring->dev->primary->index;
),
TP_printk("dev=%u, ring=%u, ctx=%p, ctx_vm=%p",
__entry->dev, __entry->ring, __entry->to, __entry->vm)
);
#endif /* _I915_TRACE_H_ */ #endif /* _I915_TRACE_H_ */
/* This part must be outside protection */ /* This part must be outside protection */
......
...@@ -270,6 +270,12 @@ void i915_save_display_reg(struct drm_device *dev) ...@@ -270,6 +270,12 @@ void i915_save_display_reg(struct drm_device *dev)
} }
/* FIXME: regfile.save TV & SDVO state */ /* FIXME: regfile.save TV & SDVO state */
/* Panel fitter */
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
dev_priv->regfile.savePFIT_CONTROL = I915_READ(PFIT_CONTROL);
dev_priv->regfile.savePFIT_PGM_RATIOS = I915_READ(PFIT_PGM_RATIOS);
}
/* Backlight */ /* Backlight */
if (INTEL_INFO(dev)->gen <= 4) if (INTEL_INFO(dev)->gen <= 4)
pci_read_config_byte(dev->pdev, PCI_LBPC, pci_read_config_byte(dev->pdev, PCI_LBPC,
...@@ -284,6 +290,7 @@ void i915_save_display_reg(struct drm_device *dev) ...@@ -284,6 +290,7 @@ void i915_save_display_reg(struct drm_device *dev)
dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL); dev_priv->regfile.saveBLC_PWM_CTL = I915_READ(BLC_PWM_CTL);
if (INTEL_INFO(dev)->gen >= 4) if (INTEL_INFO(dev)->gen >= 4)
dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2); dev_priv->regfile.saveBLC_PWM_CTL2 = I915_READ(BLC_PWM_CTL2);
dev_priv->regfile.saveBLC_HIST_CTL = I915_READ(BLC_HIST_CTL);
} }
return; return;
...@@ -313,6 +320,13 @@ void i915_restore_display_reg(struct drm_device *dev) ...@@ -313,6 +320,13 @@ void i915_restore_display_reg(struct drm_device *dev)
if (INTEL_INFO(dev)->gen >= 4) if (INTEL_INFO(dev)->gen >= 4)
I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2); I915_WRITE(BLC_PWM_CTL2, dev_priv->regfile.saveBLC_PWM_CTL2);
I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL); I915_WRITE(BLC_PWM_CTL, dev_priv->regfile.saveBLC_PWM_CTL);
I915_WRITE(BLC_HIST_CTL, dev_priv->regfile.saveBLC_HIST_CTL);
}
/* Panel fitter */
if (!IS_I830(dev) && !IS_845G(dev) && !HAS_PCH_SPLIT(dev)) {
I915_WRITE(PFIT_PGM_RATIOS, dev_priv->regfile.savePFIT_PGM_RATIOS);
I915_WRITE(PFIT_CONTROL, dev_priv->regfile.savePFIT_CONTROL);
} }
/* Display port ratios (must be done before clock is set) */ /* Display port ratios (must be done before clock is set) */
......
...@@ -107,7 +107,7 @@ static bool intel_eld_uptodate(struct drm_connector *connector, ...@@ -107,7 +107,7 @@ static bool intel_eld_uptodate(struct drm_connector *connector,
tmp &= ~bits_elda; tmp &= ~bits_elda;
I915_WRITE(reg_elda, tmp); I915_WRITE(reg_elda, tmp);
for (i = 0; i < eld[2]; i++) for (i = 0; i < drm_eld_size(eld) / 4; i++)
if (I915_READ(reg_edid) != *((uint32_t *)eld + i)) if (I915_READ(reg_edid) != *((uint32_t *)eld + i))
return false; return false;
...@@ -162,7 +162,7 @@ static void g4x_audio_codec_enable(struct drm_connector *connector, ...@@ -162,7 +162,7 @@ static void g4x_audio_codec_enable(struct drm_connector *connector,
len = (tmp >> 9) & 0x1f; /* ELD buffer size */ len = (tmp >> 9) & 0x1f; /* ELD buffer size */
I915_WRITE(G4X_AUD_CNTL_ST, tmp); I915_WRITE(G4X_AUD_CNTL_ST, tmp);
len = min_t(int, eld[2], len); len = min(drm_eld_size(eld) / 4, len);
DRM_DEBUG_DRIVER("ELD size %d\n", len); DRM_DEBUG_DRIVER("ELD size %d\n", len);
for (i = 0; i < len; i++) for (i = 0; i < len; i++)
I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i)); I915_WRITE(G4X_HDMIW_HDMIEDID, *((uint32_t *)eld + i));
...@@ -194,6 +194,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder) ...@@ -194,6 +194,7 @@ static void hsw_audio_codec_disable(struct intel_encoder *encoder)
/* Invalidate ELD */ /* Invalidate ELD */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
tmp &= ~AUDIO_ELD_VALID(pipe); tmp &= ~AUDIO_ELD_VALID(pipe);
tmp &= ~AUDIO_OUTPUT_ENABLE(pipe);
I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp); I915_WRITE(HSW_AUD_PIN_ELD_CP_VLD, tmp);
} }
...@@ -209,7 +210,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector, ...@@ -209,7 +210,7 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
int len, i; int len, i;
DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n", DRM_DEBUG_KMS("Enable audio codec on pipe %c, %u bytes ELD\n",
pipe_name(pipe), eld[2]); pipe_name(pipe), drm_eld_size(eld));
/* Enable audio presence detect, invalidate ELD */ /* Enable audio presence detect, invalidate ELD */
tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD); tmp = I915_READ(HSW_AUD_PIN_ELD_CP_VLD);
...@@ -230,8 +231,8 @@ static void hsw_audio_codec_enable(struct drm_connector *connector, ...@@ -230,8 +231,8 @@ static void hsw_audio_codec_enable(struct drm_connector *connector,
I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp); I915_WRITE(HSW_AUD_DIP_ELD_CTRL(pipe), tmp);
/* Up to 84 bytes of hw ELD buffer */ /* Up to 84 bytes of hw ELD buffer */
len = min_t(int, eld[2], 21); len = min(drm_eld_size(eld), 84);
for (i = 0; i < len; i++) for (i = 0; i < len / 4; i++)
I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i)); I915_WRITE(HSW_AUD_EDID_DATA(pipe), *((uint32_t *)eld + i));
/* ELD valid */ /* ELD valid */
...@@ -320,7 +321,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, ...@@ -320,7 +321,7 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
int aud_cntrl_st2; int aud_cntrl_st2;
DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n", DRM_DEBUG_KMS("Enable audio codec on port %c, pipe %c, %u bytes ELD\n",
port_name(port), pipe_name(pipe), eld[2]); port_name(port), pipe_name(pipe), drm_eld_size(eld));
/* /*
* FIXME: We're supposed to wait for vblank here, but we have vblanks * FIXME: We're supposed to wait for vblank here, but we have vblanks
...@@ -364,8 +365,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector, ...@@ -364,8 +365,8 @@ static void ilk_audio_codec_enable(struct drm_connector *connector,
I915_WRITE(aud_cntl_st, tmp); I915_WRITE(aud_cntl_st, tmp);
/* Up to 84 bytes of hw ELD buffer */ /* Up to 84 bytes of hw ELD buffer */
len = min_t(int, eld[2], 21); len = min(drm_eld_size(eld), 84);
for (i = 0; i < len; i++) for (i = 0; i < len / 4; i++)
I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i)); I915_WRITE(hdmiw_hdmiedid, *((uint32_t *)eld + i));
/* ELD valid */ /* ELD valid */
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -292,6 +292,9 @@ struct intel_crtc_config { ...@@ -292,6 +292,9 @@ struct intel_crtc_config {
* between pch encoders and cpu encoders. */ * between pch encoders and cpu encoders. */
bool has_pch_encoder; bool has_pch_encoder;
/* Are we sending infoframes on the attached port */
bool has_infoframe;
/* CPU Transcoder for the pipe. Currently this can only differ from the /* CPU Transcoder for the pipe. Currently this can only differ from the
* pipe on Haswell (where we have a special eDP transcoder). */ * pipe on Haswell (where we have a special eDP transcoder). */
enum transcoder cpu_transcoder; enum transcoder cpu_transcoder;
...@@ -340,7 +343,10 @@ struct intel_crtc_config { ...@@ -340,7 +343,10 @@ struct intel_crtc_config {
/* Selected dpll when shared or DPLL_ID_PRIVATE. */ /* Selected dpll when shared or DPLL_ID_PRIVATE. */
enum intel_dpll_id shared_dpll; enum intel_dpll_id shared_dpll;
/* PORT_CLK_SEL for DDI ports. */ /*
* - PORT_CLK_SEL for DDI ports on HSW/BDW.
* - enum skl_dpll on SKL
*/
uint32_t ddi_pll_sel; uint32_t ddi_pll_sel;
/* Actual register state of the dpll, for shared dpll cross-checking. */ /* Actual register state of the dpll, for shared dpll cross-checking. */
...@@ -552,6 +558,7 @@ struct intel_hdmi { ...@@ -552,6 +558,7 @@ struct intel_hdmi {
void (*set_infoframes)(struct drm_encoder *encoder, void (*set_infoframes)(struct drm_encoder *encoder,
bool enable, bool enable,
struct drm_display_mode *adjusted_mode); struct drm_display_mode *adjusted_mode);
bool (*infoframe_enabled)(struct drm_encoder *encoder);
}; };
struct intel_dp_mst_encoder; struct intel_dp_mst_encoder;
...@@ -784,8 +791,9 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); ...@@ -784,8 +791,9 @@ void gen5_enable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen5_disable_gt_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask);
void gen8_enable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_reset_rps_interrupts(struct drm_device *dev);
void gen8_disable_pm_irq(struct drm_i915_private *dev_priv, uint32_t mask); void gen6_enable_rps_interrupts(struct drm_device *dev);
void gen6_disable_rps_interrupts(struct drm_device *dev);
void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv); void intel_runtime_pm_disable_interrupts(struct drm_i915_private *dev_priv);
void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv); void intel_runtime_pm_enable_interrupts(struct drm_i915_private *dev_priv);
static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv) static inline bool intel_irqs_enabled(struct drm_i915_private *dev_priv)
...@@ -992,21 +1000,16 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp); ...@@ -992,21 +1000,16 @@ void intel_edp_backlight_off(struct intel_dp *intel_dp);
void intel_edp_panel_vdd_on(struct intel_dp *intel_dp); void intel_edp_panel_vdd_on(struct intel_dp *intel_dp);
void intel_edp_panel_on(struct intel_dp *intel_dp); void intel_edp_panel_on(struct intel_dp *intel_dp);
void intel_edp_panel_off(struct intel_dp *intel_dp); void intel_edp_panel_off(struct intel_dp *intel_dp);
void intel_edp_psr_enable(struct intel_dp *intel_dp);
void intel_edp_psr_disable(struct intel_dp *intel_dp);
void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate); void intel_dp_set_drrs_state(struct drm_device *dev, int refresh_rate);
void intel_edp_psr_invalidate(struct drm_device *dev,
unsigned frontbuffer_bits);
void intel_edp_psr_flush(struct drm_device *dev,
unsigned frontbuffer_bits);
void intel_edp_psr_init(struct drm_device *dev);
void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector); void intel_dp_add_properties(struct intel_dp *intel_dp, struct drm_connector *connector);
void intel_dp_mst_suspend(struct drm_device *dev); void intel_dp_mst_suspend(struct drm_device *dev);
void intel_dp_mst_resume(struct drm_device *dev); void intel_dp_mst_resume(struct drm_device *dev);
int intel_dp_max_link_bw(struct intel_dp *intel_dp); int intel_dp_max_link_bw(struct intel_dp *intel_dp);
void intel_dp_hot_plug(struct intel_encoder *intel_encoder); void intel_dp_hot_plug(struct intel_encoder *intel_encoder);
void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv); void vlv_power_sequencer_reset(struct drm_i915_private *dev_priv);
uint32_t intel_dp_pack_aux(const uint8_t *src, int src_bytes);
void intel_dp_unpack_aux(uint32_t src, uint8_t *dst, int dst_bytes);
/* intel_dp_mst.c */ /* intel_dp_mst.c */
int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id); int intel_dp_mst_encoder_init(struct intel_digital_port *intel_dig_port, int conn_id);
void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port); void intel_dp_mst_encoder_cleanup(struct intel_digital_port *intel_dig_port);
...@@ -1096,7 +1099,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *crtc, ...@@ -1096,7 +1099,7 @@ void intel_gmch_panel_fitting(struct intel_crtc *crtc,
int fitting_mode); int fitting_mode);
void intel_panel_set_backlight_acpi(struct intel_connector *connector, void intel_panel_set_backlight_acpi(struct intel_connector *connector,
u32 level, u32 max); u32 level, u32 max);
int intel_panel_setup_backlight(struct drm_connector *connector); int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe);
void intel_panel_enable_backlight(struct intel_connector *connector); void intel_panel_enable_backlight(struct intel_connector *connector);
void intel_panel_disable_backlight(struct intel_connector *connector); void intel_panel_disable_backlight(struct intel_connector *connector);
void intel_panel_destroy_backlight(struct drm_connector *connector); void intel_panel_destroy_backlight(struct drm_connector *connector);
...@@ -1106,6 +1109,19 @@ extern struct drm_display_mode *intel_find_panel_downclock( ...@@ -1106,6 +1109,19 @@ extern struct drm_display_mode *intel_find_panel_downclock(
struct drm_device *dev, struct drm_device *dev,
struct drm_display_mode *fixed_mode, struct drm_display_mode *fixed_mode,
struct drm_connector *connector); struct drm_connector *connector);
void intel_backlight_register(struct drm_device *dev);
void intel_backlight_unregister(struct drm_device *dev);
/* intel_psr.c */
bool intel_psr_is_enabled(struct drm_device *dev);
void intel_psr_enable(struct intel_dp *intel_dp);
void intel_psr_disable(struct intel_dp *intel_dp);
void intel_psr_invalidate(struct drm_device *dev,
unsigned frontbuffer_bits);
void intel_psr_flush(struct drm_device *dev,
unsigned frontbuffer_bits);
void intel_psr_init(struct drm_device *dev);
/* intel_runtime_pm.c */ /* intel_runtime_pm.c */
int intel_power_domains_init(struct drm_i915_private *); int intel_power_domains_init(struct drm_i915_private *);
......
...@@ -156,7 +156,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj, ...@@ -156,7 +156,7 @@ void intel_fb_obj_invalidate(struct drm_i915_gem_object *obj,
intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring); intel_mark_fb_busy(dev, obj->frontbuffer_bits, ring);
intel_edp_psr_invalidate(dev, obj->frontbuffer_bits); intel_psr_invalidate(dev, obj->frontbuffer_bits);
} }
/** /**
...@@ -182,7 +182,7 @@ void intel_frontbuffer_flush(struct drm_device *dev, ...@@ -182,7 +182,7 @@ void intel_frontbuffer_flush(struct drm_device *dev,
intel_mark_fb_busy(dev, frontbuffer_bits, NULL); intel_mark_fb_busy(dev, frontbuffer_bits, NULL);
intel_edp_psr_flush(dev, frontbuffer_bits); intel_psr_flush(dev, frontbuffer_bits);
/* /*
* FIXME: Unconditional fbc flushing here is a rather gross hack and * FIXME: Unconditional fbc flushing here is a rather gross hack and
......
...@@ -166,6 +166,19 @@ static void g4x_write_infoframe(struct drm_encoder *encoder, ...@@ -166,6 +166,19 @@ static void g4x_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(VIDEO_DIP_CTL); POSTING_READ(VIDEO_DIP_CTL);
} }
static bool g4x_infoframe_enabled(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_digital_port *intel_dig_port = enc_to_dig_port(encoder);
u32 val = I915_READ(VIDEO_DIP_CTL);
if (VIDEO_DIP_PORT(intel_dig_port->port) == (val & VIDEO_DIP_PORT_MASK))
return val & VIDEO_DIP_ENABLE;
return false;
}
static void ibx_write_infoframe(struct drm_encoder *encoder, static void ibx_write_infoframe(struct drm_encoder *encoder,
enum hdmi_infoframe_type type, enum hdmi_infoframe_type type,
const void *frame, ssize_t len) const void *frame, ssize_t len)
...@@ -204,6 +217,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder, ...@@ -204,6 +217,17 @@ static void ibx_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(reg); POSTING_READ(reg);
} }
static bool ibx_infoframe_enabled(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
return val & VIDEO_DIP_ENABLE;
}
static void cpt_write_infoframe(struct drm_encoder *encoder, static void cpt_write_infoframe(struct drm_encoder *encoder,
enum hdmi_infoframe_type type, enum hdmi_infoframe_type type,
const void *frame, ssize_t len) const void *frame, ssize_t len)
...@@ -245,6 +269,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder, ...@@ -245,6 +269,17 @@ static void cpt_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(reg); POSTING_READ(reg);
} }
static bool cpt_infoframe_enabled(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
int reg = TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
return val & VIDEO_DIP_ENABLE;
}
static void vlv_write_infoframe(struct drm_encoder *encoder, static void vlv_write_infoframe(struct drm_encoder *encoder,
enum hdmi_infoframe_type type, enum hdmi_infoframe_type type,
const void *frame, ssize_t len) const void *frame, ssize_t len)
...@@ -283,6 +318,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder, ...@@ -283,6 +318,17 @@ static void vlv_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(reg); POSTING_READ(reg);
} }
static bool vlv_infoframe_enabled(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
int reg = VLV_TVIDEO_DIP_CTL(intel_crtc->pipe);
u32 val = I915_READ(reg);
return val & VIDEO_DIP_ENABLE;
}
static void hsw_write_infoframe(struct drm_encoder *encoder, static void hsw_write_infoframe(struct drm_encoder *encoder,
enum hdmi_infoframe_type type, enum hdmi_infoframe_type type,
const void *frame, ssize_t len) const void *frame, ssize_t len)
...@@ -320,6 +366,18 @@ static void hsw_write_infoframe(struct drm_encoder *encoder, ...@@ -320,6 +366,18 @@ static void hsw_write_infoframe(struct drm_encoder *encoder,
POSTING_READ(ctl_reg); POSTING_READ(ctl_reg);
} }
static bool hsw_infoframe_enabled(struct drm_encoder *encoder)
{
struct drm_device *dev = encoder->dev;
struct drm_i915_private *dev_priv = dev->dev_private;
struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
u32 ctl_reg = HSW_TVIDEO_DIP_CTL(intel_crtc->config.cpu_transcoder);
u32 val = I915_READ(ctl_reg);
return val & (VIDEO_DIP_ENABLE_AVI_HSW | VIDEO_DIP_ENABLE_SPD_HSW |
VIDEO_DIP_ENABLE_VS_HSW);
}
/* /*
* The data we write to the DIP data buffer registers is 1 byte bigger than the * The data we write to the DIP data buffer registers is 1 byte bigger than the
* HDMI infoframe size because of an ECC/reserved byte at position 3 (starting * HDMI infoframe size because of an ECC/reserved byte at position 3 (starting
...@@ -724,6 +782,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder, ...@@ -724,6 +782,9 @@ static void intel_hdmi_get_config(struct intel_encoder *encoder,
if (tmp & HDMI_MODE_SELECT_HDMI) if (tmp & HDMI_MODE_SELECT_HDMI)
pipe_config->has_hdmi_sink = true; pipe_config->has_hdmi_sink = true;
if (intel_hdmi->infoframe_enabled(&encoder->base))
pipe_config->has_infoframe = true;
if (tmp & SDVO_AUDIO_ENABLE) if (tmp & SDVO_AUDIO_ENABLE)
pipe_config->has_audio = true; pipe_config->has_audio = true;
...@@ -925,6 +986,9 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder, ...@@ -925,6 +986,9 @@ bool intel_hdmi_compute_config(struct intel_encoder *encoder,
pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink; pipe_config->has_hdmi_sink = intel_hdmi->has_hdmi_sink;
if (pipe_config->has_hdmi_sink)
pipe_config->has_infoframe = true;
if (intel_hdmi->color_range_auto) { if (intel_hdmi->color_range_auto) {
/* See CEA-861-E - 5.1 Default Encoding Parameters */ /* See CEA-861-E - 5.1 Default Encoding Parameters */
if (pipe_config->has_hdmi_sink && if (pipe_config->has_hdmi_sink &&
...@@ -1619,18 +1683,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port, ...@@ -1619,18 +1683,23 @@ void intel_hdmi_init_connector(struct intel_digital_port *intel_dig_port,
if (IS_VALLEYVIEW(dev)) { if (IS_VALLEYVIEW(dev)) {
intel_hdmi->write_infoframe = vlv_write_infoframe; intel_hdmi->write_infoframe = vlv_write_infoframe;
intel_hdmi->set_infoframes = vlv_set_infoframes; intel_hdmi->set_infoframes = vlv_set_infoframes;
intel_hdmi->infoframe_enabled = vlv_infoframe_enabled;
} else if (IS_G4X(dev)) { } else if (IS_G4X(dev)) {
intel_hdmi->write_infoframe = g4x_write_infoframe; intel_hdmi->write_infoframe = g4x_write_infoframe;
intel_hdmi->set_infoframes = g4x_set_infoframes; intel_hdmi->set_infoframes = g4x_set_infoframes;
intel_hdmi->infoframe_enabled = g4x_infoframe_enabled;
} else if (HAS_DDI(dev)) { } else if (HAS_DDI(dev)) {
intel_hdmi->write_infoframe = hsw_write_infoframe; intel_hdmi->write_infoframe = hsw_write_infoframe;
intel_hdmi->set_infoframes = hsw_set_infoframes; intel_hdmi->set_infoframes = hsw_set_infoframes;
intel_hdmi->infoframe_enabled = hsw_infoframe_enabled;
} else if (HAS_PCH_IBX(dev)) { } else if (HAS_PCH_IBX(dev)) {
intel_hdmi->write_infoframe = ibx_write_infoframe; intel_hdmi->write_infoframe = ibx_write_infoframe;
intel_hdmi->set_infoframes = ibx_set_infoframes; intel_hdmi->set_infoframes = ibx_set_infoframes;
intel_hdmi->infoframe_enabled = ibx_infoframe_enabled;
} else { } else {
intel_hdmi->write_infoframe = cpt_write_infoframe; intel_hdmi->write_infoframe = cpt_write_infoframe;
intel_hdmi->set_infoframes = cpt_set_infoframes; intel_hdmi->set_infoframes = cpt_set_infoframes;
intel_hdmi->infoframe_enabled = cpt_infoframe_enabled;
} }
if (HAS_DDI(dev)) if (HAS_DDI(dev))
......
This diff is collapsed.
...@@ -24,6 +24,8 @@ ...@@ -24,6 +24,8 @@
#ifndef _INTEL_LRC_H_ #ifndef _INTEL_LRC_H_
#define _INTEL_LRC_H_ #define _INTEL_LRC_H_
#define GEN8_LR_CONTEXT_ALIGN 4096
/* Execlists regs */ /* Execlists regs */
#define RING_ELSP(ring) ((ring)->mmio_base+0x230) #define RING_ELSP(ring) ((ring)->mmio_base+0x230)
#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234) #define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
...@@ -67,6 +69,8 @@ int intel_lr_context_render_state_init(struct intel_engine_cs *ring, ...@@ -67,6 +69,8 @@ int intel_lr_context_render_state_init(struct intel_engine_cs *ring,
void intel_lr_context_free(struct intel_context *ctx); void intel_lr_context_free(struct intel_context *ctx);
int intel_lr_context_deferred_create(struct intel_context *ctx, int intel_lr_context_deferred_create(struct intel_context *ctx,
struct intel_engine_cs *ring); struct intel_engine_cs *ring);
void intel_lr_context_unpin(struct intel_engine_cs *ring,
struct intel_context *ctx);
/* Execlists */ /* Execlists */
int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists); int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
...@@ -104,11 +108,11 @@ struct intel_ctx_submit_request { ...@@ -104,11 +108,11 @@ struct intel_ctx_submit_request {
u32 tail; u32 tail;
struct list_head execlist_link; struct list_head execlist_link;
struct work_struct work;
int elsp_submitted; int elsp_submitted;
}; };
void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring); void intel_execlists_handle_ctx_events(struct intel_engine_cs *ring);
void intel_execlists_retire_requests(struct intel_engine_cs *ring);
#endif /* _INTEL_LRC_H_ */ #endif /* _INTEL_LRC_H_ */
...@@ -1116,7 +1116,7 @@ void intel_lvds_init(struct drm_device *dev) ...@@ -1116,7 +1116,7 @@ void intel_lvds_init(struct drm_device *dev)
drm_connector_register(connector); drm_connector_register(connector);
intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
intel_panel_setup_backlight(connector); intel_panel_setup_backlight(connector, INVALID_PIPE);
return; return;
......
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
This diff is collapsed.
...@@ -148,7 +148,8 @@ struct intel_engine_cs { ...@@ -148,7 +148,8 @@ struct intel_engine_cs {
int (*init)(struct intel_engine_cs *ring); int (*init)(struct intel_engine_cs *ring);
int (*init_context)(struct intel_engine_cs *ring); int (*init_context)(struct intel_engine_cs *ring,
struct intel_context *ctx);
void (*write_tail)(struct intel_engine_cs *ring, void (*write_tail)(struct intel_engine_cs *ring,
u32 value); u32 value);
...@@ -235,6 +236,7 @@ struct intel_engine_cs { ...@@ -235,6 +236,7 @@ struct intel_engine_cs {
/* Execlists */ /* Execlists */
spinlock_t execlist_lock; spinlock_t execlist_lock;
struct list_head execlist_queue; struct list_head execlist_queue;
struct list_head execlist_retired_req_list;
u8 next_context_status_buffer; u8 next_context_status_buffer;
u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */ u32 irq_keep_mask; /* bitmask for interrupts that should not be masked */
int (*emit_request)(struct intel_ringbuffer *ringbuf); int (*emit_request)(struct intel_ringbuffer *ringbuf);
...@@ -381,6 +383,9 @@ intel_write_status_page(struct intel_engine_cs *ring, ...@@ -381,6 +383,9 @@ intel_write_status_page(struct intel_engine_cs *ring,
#define I915_GEM_HWS_SCRATCH_INDEX 0x30 #define I915_GEM_HWS_SCRATCH_INDEX 0x30
#define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT) #define I915_GEM_HWS_SCRATCH_ADDR (I915_GEM_HWS_SCRATCH_INDEX << MI_STORE_DWORD_INDEX_SHIFT)
void intel_unpin_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
int intel_pin_and_map_ringbuffer_obj(struct drm_device *dev,
struct intel_ringbuffer *ringbuf);
void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf); void intel_destroy_ringbuffer_obj(struct intel_ringbuffer *ringbuf);
int intel_alloc_ringbuffer_obj(struct drm_device *dev, int intel_alloc_ringbuffer_obj(struct drm_device *dev,
struct intel_ringbuffer *ringbuf); struct intel_ringbuffer *ringbuf);
...@@ -424,6 +429,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev); ...@@ -424,6 +429,8 @@ int intel_init_vebox_ring_buffer(struct drm_device *dev);
u64 intel_ring_get_active_head(struct intel_engine_cs *ring); u64 intel_ring_get_active_head(struct intel_engine_cs *ring);
void intel_ring_setup_status_page(struct intel_engine_cs *ring); void intel_ring_setup_status_page(struct intel_engine_cs *ring);
int init_workarounds_ring(struct intel_engine_cs *ring);
static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf) static inline u32 intel_ring_get_tail(struct intel_ringbuffer *ringbuf)
{ {
return ringbuf->tail; return ringbuf->tail;
...@@ -441,7 +448,4 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno) ...@@ -441,7 +448,4 @@ static inline void i915_trace_irq_get(struct intel_engine_cs *ring, u32 seqno)
ring->trace_irq_seqno = seqno; ring->trace_irq_seqno = seqno;
} }
/* DRI warts */
int intel_render_ring_init_dri(struct drm_device *dev, u64 start, u32 size);
#endif /* _INTEL_RINGBUFFER_H_ */ #endif /* _INTEL_RINGBUFFER_H_ */
...@@ -577,6 +577,23 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv, ...@@ -577,6 +577,23 @@ static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
power_well->data != PIPE_C); power_well->data != PIPE_C);
chv_set_pipe_power_well(dev_priv, power_well, true); chv_set_pipe_power_well(dev_priv, power_well, true);
if (power_well->data == PIPE_A) {
spin_lock_irq(&dev_priv->irq_lock);
valleyview_enable_display_irqs(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock);
/*
* During driver initialization/resume we can avoid restoring the
* part of the HW/SW state that will be inited anyway explicitly.
*/
if (dev_priv->power_domains.initializing)
return;
intel_hpd_init(dev_priv);
i915_redisable_vga_power_on(dev_priv->dev);
}
} }
static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
...@@ -586,6 +603,12 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv, ...@@ -586,6 +603,12 @@ static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
power_well->data != PIPE_B && power_well->data != PIPE_B &&
power_well->data != PIPE_C); power_well->data != PIPE_C);
if (power_well->data == PIPE_A) {
spin_lock_irq(&dev_priv->irq_lock);
valleyview_disable_display_irqs(dev_priv);
spin_unlock_irq(&dev_priv->irq_lock);
}
chv_set_pipe_power_well(dev_priv, power_well, false); chv_set_pipe_power_well(dev_priv, power_well, false);
if (power_well->data == PIPE_A) if (power_well->data == PIPE_A)
......
...@@ -1264,10 +1264,11 @@ intel_prepare_sprite_plane(struct drm_plane *plane, ...@@ -1264,10 +1264,11 @@ intel_prepare_sprite_plane(struct drm_plane *plane,
struct drm_device *dev = plane->dev; struct drm_device *dev = plane->dev;
struct drm_crtc *crtc = state->crtc; struct drm_crtc *crtc = state->crtc;
struct intel_crtc *intel_crtc = to_intel_crtc(crtc); struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
struct intel_plane *intel_plane = to_intel_plane(plane);
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
struct drm_framebuffer *fb = state->fb; struct drm_framebuffer *fb = state->fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); struct drm_i915_gem_object *old_obj = intel_plane->obj;
int ret; int ret;
if (old_obj != obj) { if (old_obj != obj) {
...@@ -1302,7 +1303,7 @@ intel_commit_sprite_plane(struct drm_plane *plane, ...@@ -1302,7 +1303,7 @@ intel_commit_sprite_plane(struct drm_plane *plane,
enum pipe pipe = intel_crtc->pipe; enum pipe pipe = intel_crtc->pipe;
struct drm_framebuffer *fb = state->fb; struct drm_framebuffer *fb = state->fb;
struct drm_i915_gem_object *obj = intel_fb_obj(fb); struct drm_i915_gem_object *obj = intel_fb_obj(fb);
struct drm_i915_gem_object *old_obj = intel_fb_obj(plane->fb); struct drm_i915_gem_object *old_obj = intel_plane->obj;
int crtc_x, crtc_y; int crtc_x, crtc_y;
unsigned int crtc_w, crtc_h; unsigned int crtc_w, crtc_h;
uint32_t src_x, src_y, src_w, src_h; uint32_t src_x, src_y, src_w, src_h;
......
This diff is collapsed.
...@@ -1699,7 +1699,8 @@ nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode) ...@@ -1699,7 +1699,8 @@ nv50_audio_mode_set(struct drm_encoder *encoder, struct drm_display_mode *mode)
drm_edid_to_eld(&nv_connector->base, nv_connector->edid); drm_edid_to_eld(&nv_connector->base, nv_connector->edid);
memcpy(args.data, nv_connector->base.eld, sizeof(args.data)); memcpy(args.data, nv_connector->base.eld, sizeof(args.data));
nvif_mthd(disp->disp, 0, &args, sizeof(args.base) + args.data[2] * 4); nvif_mthd(disp->disp, 0, &args,
sizeof(args.base) + drm_eld_size(args.data));
} }
static void static void
......
...@@ -340,6 +340,7 @@ typedef struct drm_i915_irq_wait { ...@@ -340,6 +340,7 @@ typedef struct drm_i915_irq_wait {
#define I915_PARAM_HAS_EXEC_HANDLE_LUT 26 #define I915_PARAM_HAS_EXEC_HANDLE_LUT 26
#define I915_PARAM_HAS_WT 27 #define I915_PARAM_HAS_WT 27
#define I915_PARAM_CMD_PARSER_VERSION 28 #define I915_PARAM_CMD_PARSER_VERSION 28
#define I915_PARAM_HAS_COHERENT_PHYS_GTT 29
typedef struct drm_i915_getparam { typedef struct drm_i915_getparam {
int param; int param;
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment