Commit 2618b555 authored by Ben Dooks's avatar Ben Dooks Committed by Kukjin Kim

ARM: S3C64XX: Change to using s3c_gpio_cfgpin_range()

Change the code setting ranges of GPIO pins using s3c_gpio_cfgpin() to
use the recently introduced s3c_gpio_cfgpin_range().
Signed-off-by: default avatarBen Dooks <ben-linux@fluff.org>
Signed-off-by: default avatarKukjin Kim <kgene.kim@samsung.com>
parent f5321760
...@@ -24,25 +24,22 @@ ...@@ -24,25 +24,22 @@
static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev) static int s3c64xx_i2sv3_cfg_gpio(struct platform_device *pdev)
{ {
unsigned int base;
switch (pdev->id) { switch (pdev->id) {
case 0: case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C_GPIO_SFN(3)); base = S3C64XX_GPD(0);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C_GPIO_SFN(3));
break; break;
case 1: case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C_GPIO_SFN(3)); base = S3C64XX_GPE(0);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C_GPIO_SFN(3)); break;
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C_GPIO_SFN(3));
default: default:
printk(KERN_DEBUG "Invalid I2S Controller number!"); printk(KERN_DEBUG "Invalid I2S Controller number!");
return -EINVAL; return -EINVAL;
} }
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(3));
return 0; return 0;
} }
...@@ -51,10 +48,7 @@ static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev) ...@@ -51,10 +48,7 @@ static int s3c64xx_i2sv4_cfg_gpio(struct platform_device *pdev)
s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin(S3C64XX_GPC(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin(S3C64XX_GPC(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5)); s3c_gpio_cfgpin(S3C64XX_GPC(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S3C64XX_GPH(6), S3C_GPIO_SFN(4)); s3c_gpio_cfgpin_range(S3C64XX_GPH(6), 4, S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPH(7), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPH(8), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPH(9), S3C_GPIO_SFN(4));
return 0; return 0;
} }
...@@ -163,26 +157,21 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4); ...@@ -163,26 +157,21 @@ EXPORT_SYMBOL(s3c64xx_device_iisv4);
static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev) static int s3c64xx_pcm_cfg_gpio(struct platform_device *pdev)
{ {
unsigned int base;
switch (pdev->id) { switch (pdev->id) {
case 0: case 0:
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C_GPIO_SFN(2)); base = S3C64XX_GPD(0);
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C_GPIO_SFN(2));
break; break;
case 1: case 1:
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C_GPIO_SFN(2)); base = S3C64XX_GPE(0);
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C_GPIO_SFN(2));
break; break;
default: default:
printk(KERN_DEBUG "Invalid PCM Controller number!"); printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL; return -EINVAL;
} }
s3c_gpio_cfgpin_range(base, 5, S3C_GPIO_SFN(2));
return 0; return 0;
} }
...@@ -256,24 +245,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1); ...@@ -256,24 +245,12 @@ EXPORT_SYMBOL(s3c64xx_device_pcm1);
static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev) static int s3c64xx_ac97_cfg_gpd(struct platform_device *pdev)
{ {
s3c_gpio_cfgpin(S3C64XX_GPD(0), S3C_GPIO_SFN(4)); return s3c_gpio_cfgpin_range(S3C64XX_GPD(0), 5, S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPD(1), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPD(2), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPD(3), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPD(4), S3C_GPIO_SFN(4));
return 0;
} }
static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev) static int s3c64xx_ac97_cfg_gpe(struct platform_device *pdev)
{ {
s3c_gpio_cfgpin(S3C64XX_GPE(0), S3C_GPIO_SFN(4)); return s3c_gpio_cfgpin_range(S3C64XX_GPE(0), 5, S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPE(1), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPE(2), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPE(3), S3C_GPIO_SFN(4));
s3c_gpio_cfgpin(S3C64XX_GPE(4), S3C_GPIO_SFN(4));
return 0;
} }
static struct resource s3c64xx_ac97_resource[] = { static struct resource s3c64xx_ac97_resource[] = {
......
...@@ -30,8 +30,8 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width) ...@@ -30,8 +30,8 @@ void s3c64xx_setup_sdhci0_cfg_gpio(struct platform_device *dev, int width)
end = S3C64XX_GPG(2 + width); end = S3C64XX_GPG(2 + width);
/* Set all the necessary GPG pins to special-function 0 */ /* Set all the necessary GPG pins to special-function 0 */
s3c_gpio_cfgpin_range(S3C64XX_GPG(0), 2 + width, S3C_GPIO_SFN(2));
for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) { for (gpio = S3C64XX_GPG(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
} }
...@@ -50,8 +50,8 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width) ...@@ -50,8 +50,8 @@ void s3c64xx_setup_sdhci1_cfg_gpio(struct platform_device *dev, int width)
end = S3C64XX_GPH(2 + width); end = S3C64XX_GPH(2 + width);
/* Set all the necessary GPG pins to special-function 0 */ /* Set all the necessary GPG pins to special-function 0 */
s3c_gpio_cfgpin_range(S3C64XX_GPH(0), 2 + width, S3C_GPIO_SFN(2));
for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) { for (gpio = S3C64XX_GPH(0); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
} }
...@@ -69,14 +69,14 @@ void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width) ...@@ -69,14 +69,14 @@ void s3c64xx_setup_sdhci2_cfg_gpio(struct platform_device *dev, int width)
end = S3C64XX_GPH(6 + width); end = S3C64XX_GPH(6 + width);
/* Set all the necessary GPH pins to special-function 1 */ /* Set all the necessary GPH pins to special-function 1 */
s3c_gpio_cfgpin_range(S3C64XX_GPH(6), width, S3C_GPIO_SFN(3));
for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) { for (gpio = S3C64XX_GPH(6); gpio < end; gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
} }
/* Set all the necessary GPC pins to special-function 1 */ /* Set all the necessary GPC pins to special-function 1 */
s3c_gpio_cfgpin_range(S3C64XX_GPC(4), 2, S3C_GPIO_SFN(3));
for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) { for (gpio = S3C64XX_GPC(4); gpio < S3C64XX_GPC(6); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(3));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE); s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
} }
} }
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