Commit 2678bc5c authored by Borislav Petkov's avatar Borislav Petkov Committed by Greg Kroah-Hartman

x86/microcode/intel: Add a helper which gives the microcode revision

commit 4167709b upstream.

Since on Intel we're required to do CPUID(1) first, before reading
the microcode revision MSR, let's add a special helper which does the
required steps so that we don't forget to do them next time, when we
want to read the microcode revision.
Signed-off-by: default avatarBorislav Petkov <bp@suse.de>
Link: http://lkml.kernel.org/r/20170109114147.5082-4-bp@alien8.deSigned-off-by: default avatarThomas Gleixner <tglx@linutronix.de>
[bwh: Backported to 4.9:
 - Keep using sync_core(), which will alway includes the necessary CPUID
 - Adjust context]
Signed-off-by: default avatarBen Hutchings <ben@decadent.org.uk>
Signed-off-by: default avatarGreg Kroah-Hartman <gregkh@linuxfoundation.org>
parent a7501dca
...@@ -52,6 +52,21 @@ struct extended_sigtable { ...@@ -52,6 +52,21 @@ struct extended_sigtable {
#define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE) #define exttable_size(et) ((et)->count * EXT_SIGNATURE_SIZE + EXT_HEADER_SIZE)
static inline u32 intel_get_microcode_revision(void)
{
u32 rev, dummy;
native_wrmsrl(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */
native_rdmsr(MSR_IA32_UCODE_REV, dummy, rev);
return rev;
}
extern int has_newer_microcode(void *mc, unsigned int csig, int cpf, int rev); extern int has_newer_microcode(void *mc, unsigned int csig, int cpf, int rev);
extern int microcode_sanity_check(void *mc, int print_err); extern int microcode_sanity_check(void *mc, int print_err);
extern int find_matching_signature(void *mc, unsigned int csig, int cpf); extern int find_matching_signature(void *mc, unsigned int csig, int cpf);
......
...@@ -14,6 +14,7 @@ ...@@ -14,6 +14,7 @@
#include <asm/bugs.h> #include <asm/bugs.h>
#include <asm/cpu.h> #include <asm/cpu.h>
#include <asm/intel-family.h> #include <asm/intel-family.h>
#include <asm/microcode_intel.h>
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
#include <linux/topology.h> #include <linux/topology.h>
...@@ -137,14 +138,8 @@ static void early_init_intel(struct cpuinfo_x86 *c) ...@@ -137,14 +138,8 @@ static void early_init_intel(struct cpuinfo_x86 *c)
(c->x86 == 0x6 && c->x86_model >= 0x0e)) (c->x86 == 0x6 && c->x86_model >= 0x0e))
set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC); set_cpu_cap(c, X86_FEATURE_CONSTANT_TSC);
if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64)) { if (c->x86 >= 6 && !cpu_has(c, X86_FEATURE_IA64))
unsigned lower_word; c->microcode = intel_get_microcode_revision();
wrmsr(MSR_IA32_UCODE_REV, 0, 0);
/* Required by the SDM */
sync_core();
rdmsr(MSR_IA32_UCODE_REV, lower_word, c->microcode);
}
/* Now if any of them are set, check the blacklist and clear the lot */ /* Now if any of them are set, check the blacklist and clear the lot */
if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) || if ((cpu_has(c, X86_FEATURE_SPEC_CTRL) ||
......
...@@ -386,15 +386,8 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci) ...@@ -386,15 +386,8 @@ static int collect_cpu_info_early(struct ucode_cpu_info *uci)
native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]); native_rdmsr(MSR_IA32_PLATFORM_ID, val[0], val[1]);
csig.pf = 1 << ((val[1] >> 18) & 7); csig.pf = 1 << ((val[1] >> 18) & 7);
} }
native_wrmsrl(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */ csig.rev = intel_get_microcode_revision();
sync_core();
/* get the current revision from MSR 0x8B */
native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
csig.rev = val[1];
uci->cpu_sig = csig; uci->cpu_sig = csig;
uci->valid = 1; uci->valid = 1;
...@@ -618,7 +611,7 @@ static inline void print_ucode(struct ucode_cpu_info *uci) ...@@ -618,7 +611,7 @@ static inline void print_ucode(struct ucode_cpu_info *uci)
static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
{ {
struct microcode_intel *mc; struct microcode_intel *mc;
unsigned int val[2]; u32 rev;
mc = uci->mc; mc = uci->mc;
if (!mc) if (!mc)
...@@ -626,21 +619,16 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early) ...@@ -626,21 +619,16 @@ static int apply_microcode_early(struct ucode_cpu_info *uci, bool early)
/* write microcode via MSR 0x79 */ /* write microcode via MSR 0x79 */
native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); native_wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
native_wrmsrl(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */ rev = intel_get_microcode_revision();
sync_core(); if (rev != mc->hdr.rev)
/* get the current revision from MSR 0x8B */
native_rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
if (val[1] != mc->hdr.rev)
return -1; return -1;
#ifdef CONFIG_X86_64 #ifdef CONFIG_X86_64
/* Flush global tlb. This is precaution. */ /* Flush global tlb. This is precaution. */
flush_tlb_early(); flush_tlb_early();
#endif #endif
uci->cpu_sig.rev = val[1]; uci->cpu_sig.rev = rev;
if (early) if (early)
print_ucode(uci); print_ucode(uci);
...@@ -904,8 +892,8 @@ static int apply_microcode_intel(int cpu) ...@@ -904,8 +892,8 @@ static int apply_microcode_intel(int cpu)
struct microcode_intel *mc; struct microcode_intel *mc;
struct ucode_cpu_info *uci; struct ucode_cpu_info *uci;
struct cpuinfo_x86 *c; struct cpuinfo_x86 *c;
unsigned int val[2];
static int prev_rev; static int prev_rev;
u32 rev;
/* We should bind the task to the CPU */ /* We should bind the task to the CPU */
if (WARN_ON(raw_smp_processor_id() != cpu)) if (WARN_ON(raw_smp_processor_id() != cpu))
...@@ -926,33 +914,28 @@ static int apply_microcode_intel(int cpu) ...@@ -926,33 +914,28 @@ static int apply_microcode_intel(int cpu)
/* write microcode via MSR 0x79 */ /* write microcode via MSR 0x79 */
wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits); wrmsrl(MSR_IA32_UCODE_WRITE, (unsigned long)mc->bits);
wrmsrl(MSR_IA32_UCODE_REV, 0);
/* As documented in the SDM: Do a CPUID 1 here */
sync_core();
/* get the current revision from MSR 0x8B */ rev = intel_get_microcode_revision();
rdmsr(MSR_IA32_UCODE_REV, val[0], val[1]);
if (val[1] != mc->hdr.rev) { if (rev != mc->hdr.rev) {
pr_err("CPU%d update to revision 0x%x failed\n", pr_err("CPU%d update to revision 0x%x failed\n",
cpu, mc->hdr.rev); cpu, mc->hdr.rev);
return -1; return -1;
} }
if (val[1] != prev_rev) { if (rev != prev_rev) {
pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n", pr_info("updated to revision 0x%x, date = %04x-%02x-%02x\n",
val[1], rev,
mc->hdr.date & 0xffff, mc->hdr.date & 0xffff,
mc->hdr.date >> 24, mc->hdr.date >> 24,
(mc->hdr.date >> 16) & 0xff); (mc->hdr.date >> 16) & 0xff);
prev_rev = val[1]; prev_rev = rev;
} }
c = &cpu_data(cpu); c = &cpu_data(cpu);
uci->cpu_sig.rev = val[1]; uci->cpu_sig.rev = rev;
c->microcode = val[1]; c->microcode = rev;
return 0; return 0;
} }
......
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