Commit 2789658f authored by Maxim Kochetkov's avatar Maxim Kochetkov Committed by David S. Miller

soc: mscc: ocelot: add MII registers description

Add the register definitions for the MSCC MIIM MDIO controller in
preparation for seville_vsc9959.c to create its accessors for the
internal MDIO bus.

Since we've introduced elements to ocelot_regfields that are not
instantiated by felix and ocelot, we need to define the size of the
regfields arrays explicitly, otherwise ocelot_regfields_init, which
iterates up to REGFIELD_MAX, will fault on the undefined regfield
entries (if we're lucky).
Signed-off-by: default avatarMaxim Kochetkov <fido_max@inbox.ru>
Signed-off-by: default avatarVladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: default avatarFlorian Fainelli <f.fainelli@gmail.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent 91c724cf
...@@ -469,7 +469,7 @@ static const struct resource vsc9959_imdio_res = { ...@@ -469,7 +469,7 @@ static const struct resource vsc9959_imdio_res = {
.name = "imdio", .name = "imdio",
}; };
static const struct reg_field vsc9959_regfields[] = { static const struct reg_field vsc9959_regfields[REGFIELD_MAX] = {
[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6), [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 6, 6),
[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5), [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 5),
[ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30), [ANA_ANEVENTS_FLOOD_DISCARD] = REG_FIELD(ANA_ANEVENTS, 30, 30),
......
...@@ -316,7 +316,7 @@ static const u32 *ocelot_regmap[TARGET_MAX] = { ...@@ -316,7 +316,7 @@ static const u32 *ocelot_regmap[TARGET_MAX] = {
[DEV_GMII] = ocelot_dev_gmii_regmap, [DEV_GMII] = ocelot_dev_gmii_regmap,
}; };
static const struct reg_field ocelot_regfields[] = { static const struct reg_field ocelot_regfields[REGFIELD_MAX] = {
[ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11), [ANA_ADVLEARN_VLAN_CHK] = REG_FIELD(ANA_ADVLEARN, 11, 11),
[ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10), [ANA_ADVLEARN_LEARN_MIRROR] = REG_FIELD(ANA_ADVLEARN, 0, 10),
[ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27), [ANA_ANEVENTS_MSTI_DROP] = REG_FIELD(ANA_ANEVENTS, 27, 27),
......
...@@ -409,6 +409,9 @@ enum ocelot_reg { ...@@ -409,6 +409,9 @@ enum ocelot_reg {
PTP_CLK_CFG_ADJ_CFG, PTP_CLK_CFG_ADJ_CFG,
PTP_CLK_CFG_ADJ_FREQ, PTP_CLK_CFG_ADJ_FREQ,
GCB_SOFT_RST = GCB << TARGET_OFFSET, GCB_SOFT_RST = GCB << TARGET_OFFSET,
GCB_MIIM_MII_STATUS,
GCB_MIIM_MII_CMD,
GCB_MIIM_MII_DATA,
DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET, DEV_CLOCK_CFG = DEV_GMII << TARGET_OFFSET,
DEV_PORT_MISC, DEV_PORT_MISC,
DEV_EVENTS, DEV_EVENTS,
...@@ -496,6 +499,8 @@ enum ocelot_regfield { ...@@ -496,6 +499,8 @@ enum ocelot_regfield {
SYS_RESET_CFG_MEM_ENA, SYS_RESET_CFG_MEM_ENA,
SYS_RESET_CFG_MEM_INIT, SYS_RESET_CFG_MEM_INIT,
GCB_SOFT_RST_SWC_RST, GCB_SOFT_RST_SWC_RST,
GCB_MIIM_MII_STATUS_PENDING,
GCB_MIIM_MII_STATUS_BUSY,
REGFIELD_MAX REGFIELD_MAX
}; };
......
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