Commit 289bcffb authored by Likun Gao's avatar Likun Gao Committed by Alex Deucher

drm/amdgpu: support imu for gfx11

Add support to initialize imu for gfx v11.
IMU is a new power management block for
gfx which manages gfx power.
Signed-off-by: default avatarLikun Gao <Likun.Gao@amd.com>
Reviewed-by: default avatarHawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18ee4ce6
...@@ -130,7 +130,8 @@ amdgpu-y += \ ...@@ -130,7 +130,8 @@ amdgpu-y += \
gfx_v9_0.o \ gfx_v9_0.o \
gfx_v9_4.o \ gfx_v9_4.o \
gfx_v9_4_2.o \ gfx_v9_4_2.o \
gfx_v10_0.o gfx_v10_0.o \
imu_v11_0.o
# add async DMA block # add async DMA block
amdgpu-y += \ amdgpu-y += \
......
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
#include "clearstate_defs.h" #include "clearstate_defs.h"
#include "amdgpu_ring.h" #include "amdgpu_ring.h"
#include "amdgpu_rlc.h" #include "amdgpu_rlc.h"
#include "amdgpu_imu.h"
#include "soc15.h" #include "soc15.h"
#include "amdgpu_ras.h" #include "amdgpu_ras.h"
...@@ -274,6 +275,7 @@ struct amdgpu_gfx { ...@@ -274,6 +275,7 @@ struct amdgpu_gfx {
struct amdgpu_me me; struct amdgpu_me me;
struct amdgpu_mec mec; struct amdgpu_mec mec;
struct amdgpu_kiq kiq; struct amdgpu_kiq kiq;
struct amdgpu_imu imu;
struct amdgpu_scratch scratch; struct amdgpu_scratch scratch;
const struct firmware *me_fw; /* ME firmware */ const struct firmware *me_fw; /* ME firmware */
uint32_t me_fw_version; uint32_t me_fw_version;
...@@ -287,6 +289,8 @@ struct amdgpu_gfx { ...@@ -287,6 +289,8 @@ struct amdgpu_gfx {
uint32_t mec_fw_version; uint32_t mec_fw_version;
const struct firmware *mec2_fw; /* MEC2 firmware */ const struct firmware *mec2_fw; /* MEC2 firmware */
uint32_t mec2_fw_version; uint32_t mec2_fw_version;
const struct firmware *imu_fw; /* IMU firmware */
uint32_t imu_fw_version;
uint32_t me_feature_version; uint32_t me_feature_version;
uint32_t ce_feature_version; uint32_t ce_feature_version;
uint32_t pfp_feature_version; uint32_t pfp_feature_version;
......
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __AMDGPU_IMU_H__
#define __AMDGPU_IMU_H__
struct amdgpu_imu_funcs {
int (*init_microcode)(struct amdgpu_device *adev);
int (*load_microcode)(struct amdgpu_device *adev);
void (*setup_imu)(struct amdgpu_device *adev);
int (*start_imu)(struct amdgpu_device *adev);
void (*program_rlc_ram)(struct amdgpu_device *adev);
};
struct imu_rlc_ram_golden {
u32 hwip;
u32 instance;
u32 segment;
u32 reg;
u32 data;
u32 addr_mask;
};
#define IMU_RLC_RAM_GOLDEN_VALUE(ip, inst, reg, data, addr_mask) \
{ ip##_HWIP, inst, reg##_BASE_IDX, reg, data, addr_mask }
struct amdgpu_imu {
const struct amdgpu_imu_funcs *funcs;
};
#endif
...@@ -126,6 +126,19 @@ void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr) ...@@ -126,6 +126,19 @@ void amdgpu_ucode_print_gfx_hdr(const struct common_firmware_header *hdr)
} }
} }
void amdgpu_ucode_print_imu_hdr(const struct common_firmware_header *hdr)
{
uint16_t version_major = le16_to_cpu(hdr->header_version_major);
uint16_t version_minor = le16_to_cpu(hdr->header_version_minor);
DRM_DEBUG("IMU\n");
amdgpu_ucode_print_common_hdr(hdr);
if (version_major != 1) {
DRM_ERROR("Unknown GFX ucode version: %u.%u\n", version_major, version_minor);
}
}
void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr) void amdgpu_ucode_print_rlc_hdr(const struct common_firmware_header *hdr)
{ {
uint16_t version_major = le16_to_cpu(hdr->header_version_major); uint16_t version_major = le16_to_cpu(hdr->header_version_major);
......
This diff is collapsed.
/*
* Copyright 2021 Advanced Micro Devices, Inc.
*
* Permission is hereby granted, free of charge, to any person obtaining a
* copy of this software and associated documentation files (the "Software"),
* to deal in the Software without restriction, including without limitation
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
* and/or sell copies of the Software, and to permit persons to whom the
* Software is furnished to do so, subject to the following conditions:
*
* The above copyright notice and this permission notice shall be included in
* all copies or substantial portions of the Software.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
* OTHER DEALINGS IN THE SOFTWARE.
*
*/
#ifndef __IMU_V11_0_H__
#define __IMU_V11_0_H__
extern const struct amdgpu_imu_funcs gfx_v11_0_imu_funcs;
#endif
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