Commit 28c5dcb2 authored by Suzuki K Poulose's avatar Suzuki K Poulose Committed by Catalin Marinas

arm64: Rename cpuid_feature field extract routines

Now that we have a clear understanding of the sign of a feature,
rename the routines to reflect the sign, so that it is not misused.
The cpuid_feature_extract_field() now accepts a 'sign' parameter.
Signed-off-by: default avatarSuzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: default avatarWill Deacon <will.deacon@arm.com>
Acked-by: default avatarMarc Zyngier <marc.zyngier@arm.com>
Signed-off-by: default avatarCatalin Marinas <catalin.marinas@arm.com>
parent ff96f7bc
...@@ -121,15 +121,15 @@ static inline void cpus_set_cap(unsigned int num) ...@@ -121,15 +121,15 @@ static inline void cpus_set_cap(unsigned int num)
} }
static inline int __attribute_const__ static inline int __attribute_const__
cpuid_feature_extract_field_width(u64 features, int field, int width) cpuid_feature_extract_signed_field_width(u64 features, int field, int width)
{ {
return (s64)(features << (64 - width - field)) >> (64 - width); return (s64)(features << (64 - width - field)) >> (64 - width);
} }
static inline int __attribute_const__ static inline int __attribute_const__
cpuid_feature_extract_field(u64 features, int field) cpuid_feature_extract_signed_field(u64 features, int field)
{ {
return cpuid_feature_extract_field_width(features, field, 4); return cpuid_feature_extract_signed_field_width(features, field, 4);
} }
static inline unsigned int __attribute_const__ static inline unsigned int __attribute_const__
...@@ -149,17 +149,23 @@ static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp) ...@@ -149,17 +149,23 @@ static inline u64 arm64_ftr_mask(struct arm64_ftr_bits *ftrp)
return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift); return (u64)GENMASK(ftrp->shift + ftrp->width - 1, ftrp->shift);
} }
static inline int __attribute_const__
cpuid_feature_extract_field(u64 features, int field, bool sign)
{
return (sign) ?
cpuid_feature_extract_signed_field(features, field) :
cpuid_feature_extract_unsigned_field(features, field);
}
static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val) static inline s64 arm64_ftr_value(struct arm64_ftr_bits *ftrp, u64 val)
{ {
return ftrp->sign ? return (s64)cpuid_feature_extract_field(val, ftrp->shift, ftrp->sign);
cpuid_feature_extract_field_width(val, ftrp->shift, ftrp->width) :
cpuid_feature_extract_unsigned_field_width(val, ftrp->shift, ftrp->width);
} }
static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0) static inline bool id_aa64mmfr0_mixed_endian_el0(u64 mmfr0)
{ {
return cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 || return cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL_SHIFT) == 0x1 ||
cpuid_feature_extract_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1; cpuid_feature_extract_unsigned_field(mmfr0, ID_AA64MMFR0_BIGENDEL0_SHIFT) == 0x1;
} }
void __init setup_cpu_features(void); void __init setup_cpu_features(void);
......
...@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void) ...@@ -307,7 +307,7 @@ static inline unsigned int kvm_get_vmid_bits(void)
{ {
int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1); int reg = read_system_reg(SYS_ID_AA64MMFR1_EL1);
return (cpuid_feature_extract_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8; return (cpuid_feature_extract_unsigned_field(reg, ID_AA64MMFR1_VMIDBITS_SHIFT) == 2) ? 16 : 8;
} }
#endif /* __ASSEMBLY__ */ #endif /* __ASSEMBLY__ */
......
...@@ -618,7 +618,7 @@ u64 read_system_reg(u32 id) ...@@ -618,7 +618,7 @@ u64 read_system_reg(u32 id)
static bool static bool
feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry) feature_matches(u64 reg, const struct arm64_cpu_capabilities *entry)
{ {
int val = cpuid_feature_extract_field(reg, entry->field_pos); int val = cpuid_feature_extract_field(reg, entry->field_pos, entry->sign);
return val >= entry->min_field_value; return val >= entry->min_field_value;
} }
......
...@@ -34,7 +34,7 @@ ...@@ -34,7 +34,7 @@
/* Determine debug architecture. */ /* Determine debug architecture. */
u8 debug_monitors_arch(void) u8 debug_monitors_arch(void)
{ {
return cpuid_feature_extract_field(read_system_reg(SYS_ID_AA64DFR0_EL1), return cpuid_feature_extract_unsigned_field(read_system_reg(SYS_ID_AA64DFR0_EL1),
ID_AA64DFR0_DEBUGVER_SHIFT); ID_AA64DFR0_DEBUGVER_SHIFT);
} }
......
...@@ -688,7 +688,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu, ...@@ -688,7 +688,7 @@ static bool trap_dbgidr(struct kvm_vcpu *vcpu,
} else { } else {
u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1); u64 dfr = read_system_reg(SYS_ID_AA64DFR0_EL1);
u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1); u64 pfr = read_system_reg(SYS_ID_AA64PFR0_EL1);
u32 el3 = !!cpuid_feature_extract_field(pfr, ID_AA64PFR0_EL3_SHIFT); u32 el3 = !!cpuid_feature_extract_unsigned_field(pfr, ID_AA64PFR0_EL3_SHIFT);
p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) | p->regval = ((((dfr >> ID_AA64DFR0_WRPS_SHIFT) & 0xf) << 28) |
(((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) | (((dfr >> ID_AA64DFR0_BRPS_SHIFT) & 0xf) << 24) |
......
...@@ -45,7 +45,7 @@ static cpumask_t tlb_flush_pending; ...@@ -45,7 +45,7 @@ static cpumask_t tlb_flush_pending;
static u32 get_cpu_asid_bits(void) static u32 get_cpu_asid_bits(void)
{ {
u32 asid; u32 asid;
int fld = cpuid_feature_extract_field(read_cpuid(SYS_ID_AA64MMFR0_EL1), int fld = cpuid_feature_extract_unsigned_field(read_cpuid(SYS_ID_AA64MMFR0_EL1),
ID_AA64MMFR0_ASID_SHIFT); ID_AA64MMFR0_ASID_SHIFT);
switch (fld) { switch (fld) {
......
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