Commit 293623f7 authored by Ville Syrjälä's avatar Ville Syrjälä Committed by Daniel Vetter

drm/i915: Make i9xx_crtc_clock_get() use dpll_hw_state

We already extract the DPLL state to pipe_config, so let's make use of
it in i9xx_crtc_clock_get() and avoid the register reads.

This will also make the function closer to being useable with PCH DPLL
since the registers for those live in a different address.

Also kill the useless adjusted_mode.clock zeroing. It's already zero at
this point.

v2: Read out DPLL state in intel_crtc_mode_get()
Signed-off-by: default avatarVille Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by: default avatarJani Nikula <jani.nikula@intel.com>
Signed-off-by: default avatarDaniel Vetter <daniel.vetter@ffwll.ch>
parent 6878da05
...@@ -7348,14 +7348,14 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, ...@@ -7348,14 +7348,14 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct drm_device *dev = crtc->base.dev; struct drm_device *dev = crtc->base.dev;
struct drm_i915_private *dev_priv = dev->dev_private; struct drm_i915_private *dev_priv = dev->dev_private;
int pipe = pipe_config->cpu_transcoder; int pipe = pipe_config->cpu_transcoder;
u32 dpll = I915_READ(DPLL(pipe)); u32 dpll = pipe_config->dpll_hw_state.dpll;
u32 fp; u32 fp;
intel_clock_t clock; intel_clock_t clock;
if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0) if ((dpll & DISPLAY_RATE_SELECT_FPA1) == 0)
fp = I915_READ(FP0(pipe)); fp = pipe_config->dpll_hw_state.fp0;
else else
fp = I915_READ(FP1(pipe)); fp = pipe_config->dpll_hw_state.fp1;
clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT; clock.m1 = (fp & FP_M1_DIV_MASK) >> FP_M1_DIV_SHIFT;
if (IS_PINEVIEW(dev)) { if (IS_PINEVIEW(dev)) {
...@@ -7386,7 +7386,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc, ...@@ -7386,7 +7386,6 @@ static void i9xx_crtc_clock_get(struct intel_crtc *crtc,
default: default:
DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed " DRM_DEBUG_KMS("Unknown DPLL mode %08x in programmed "
"mode\n", (int)(dpll & DPLL_MODE_MASK)); "mode\n", (int)(dpll & DPLL_MODE_MASK));
pipe_config->adjusted_mode.clock = 0;
return; return;
} }
...@@ -7486,6 +7485,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, ...@@ -7486,6 +7485,7 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
int hsync = I915_READ(HSYNC(cpu_transcoder)); int hsync = I915_READ(HSYNC(cpu_transcoder));
int vtot = I915_READ(VTOTAL(cpu_transcoder)); int vtot = I915_READ(VTOTAL(cpu_transcoder));
int vsync = I915_READ(VSYNC(cpu_transcoder)); int vsync = I915_READ(VSYNC(cpu_transcoder));
enum pipe pipe = intel_crtc->pipe;
mode = kzalloc(sizeof(*mode), GFP_KERNEL); mode = kzalloc(sizeof(*mode), GFP_KERNEL);
if (!mode) if (!mode)
...@@ -7498,8 +7498,11 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev, ...@@ -7498,8 +7498,11 @@ struct drm_display_mode *intel_crtc_mode_get(struct drm_device *dev,
* Note, if LVDS ever uses a non-1 pixel multiplier, we'll need * Note, if LVDS ever uses a non-1 pixel multiplier, we'll need
* to use a real value here instead. * to use a real value here instead.
*/ */
pipe_config.cpu_transcoder = (enum transcoder) intel_crtc->pipe; pipe_config.cpu_transcoder = (enum transcoder) pipe;
pipe_config.pixel_multiplier = 1; pipe_config.pixel_multiplier = 1;
pipe_config.dpll_hw_state.dpll = I915_READ(DPLL(pipe));
pipe_config.dpll_hw_state.fp0 = I915_READ(FP0(pipe));
pipe_config.dpll_hw_state.fp1 = I915_READ(FP1(pipe));
i9xx_crtc_clock_get(intel_crtc, &pipe_config); i9xx_crtc_clock_get(intel_crtc, &pipe_config);
mode->clock = pipe_config.adjusted_mode.clock; mode->clock = pipe_config.adjusted_mode.clock;
......
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