Commit 2b5a30ca authored by Ranjani Sridharan's avatar Ranjani Sridharan Committed by Mark Brown

ASoC: SOF: Intel: MTL: Enable DMI L1

DMI L1 should be enabled unconditionally after FW boot is complete.
Signed-off-by: default avatarRanjani Sridharan <ranjani.sridharan@linux.intel.com>
Reviewed-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: default avatarBard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: default avatarPeter Ujfalusi <peter.ujfalusi@linux.intel.com>
Link: https://lore.kernel.org/r/20230220075804.4829-4-peter.ujfalusi@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent 1133a9aa
...@@ -280,6 +280,9 @@ static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev) ...@@ -280,6 +280,9 @@ static int mtl_dsp_post_fw_run(struct snd_sof_dev *sdev)
} }
hda_sdw_int_enable(sdev, true); hda_sdw_int_enable(sdev, true);
/* enable DMI L1 */
snd_sof_dsp_update_bits(sdev, HDA_DSP_HDA_BAR, MTL_EM2, MTL_EM2_L1SEN, MTL_EM2_L1SEN);
return 0; return 0;
} }
......
...@@ -28,6 +28,8 @@ ...@@ -28,6 +28,8 @@
#define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0) #define MTL_HFINTIPPTR_PTR_MASK GENMASK(20, 0)
#define MTL_HDA_VS_D0I3C 0x1D4A #define MTL_HDA_VS_D0I3C 0x1D4A
#define MTL_EM2 0x1c44
#define MTL_EM2_L1SEN BIT(13)
#define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00 #define MTL_DSP2CXCAP_PRIMARY_CORE 0x178D00
#define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04 #define MTL_DSP2CXCTL_PRIMARY_CORE 0x178D04
......
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