Commit 2b83557a authored by Linus Walleij's avatar Linus Walleij Committed by David S. Miller

ARM: dts: marvell: Fix some common switch mistakes

Fix some errors in the Marvell MV88E6xxx switch descriptions:
- The top node had no address size or cells.
- switch0@0 is not OK, should be ethernet-switch@0.
- The ports node should be named ethernet-ports
- The ethernet-ports node should have port@0 etc children, no
  plural "ports" in the children.
- Ports should be named ethernet-port@0 etc
- PHYs should be named ethernet-phy@0 etc

This serves as an example of fixes needed for introducing a
schema for the bindings, but the patch can simply be applied.
Reviewed-by: default avatarAndrew Lunn <andrew@lunn.ch>
Signed-off-by: default avatarLinus Walleij <linus.walleij@linaro.org>
Reviewed-by: default avatarFlorian Fainelli <florian.fainelli@broadcom.com>
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parent ddae07ce
...@@ -149,39 +149,37 @@ led@0 { ...@@ -149,39 +149,37 @@ led@0 {
}; };
}; };
switch: switch@10 { switch: ethernet-switch@10 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0x10>; reg = <0x10>;
interrupt-controller; interrupt-controller;
#interrupt-cells = <2>; #interrupt-cells = <2>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { ethernet-port@0 {
reg = <0>; reg = <0>;
label = "lan0"; label = "lan0";
}; };
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan1"; label = "lan1";
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan2"; label = "lan2";
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan3"; label = "lan3";
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
ethernet = <&eth1>; ethernet = <&eth1>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -196,25 +194,25 @@ mdio { ...@@ -196,25 +194,25 @@ mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
switchphy0: switchphy@0 { switchphy0: ethernet-phy@0 {
reg = <0>; reg = <0>;
interrupt-parent = <&switch>; interrupt-parent = <&switch>;
interrupts = <0 IRQ_TYPE_LEVEL_HIGH>; interrupts = <0 IRQ_TYPE_LEVEL_HIGH>;
}; };
switchphy1: switchphy@1 { switchphy1: ethernet-phy@1 {
reg = <1>; reg = <1>;
interrupt-parent = <&switch>; interrupt-parent = <&switch>;
interrupts = <1 IRQ_TYPE_LEVEL_HIGH>; interrupts = <1 IRQ_TYPE_LEVEL_HIGH>;
}; };
switchphy2: switchphy@2 { switchphy2: ethernet-phy@2 {
reg = <2>; reg = <2>;
interrupt-parent = <&switch>; interrupt-parent = <&switch>;
interrupts = <2 IRQ_TYPE_LEVEL_HIGH>; interrupts = <2 IRQ_TYPE_LEVEL_HIGH>;
}; };
switchphy3: switchphy@3 { switchphy3: ethernet-phy@3 {
reg = <3>; reg = <3>;
interrupt-parent = <&switch>; interrupt-parent = <&switch>;
interrupts = <3 IRQ_TYPE_LEVEL_HIGH>; interrupts = <3 IRQ_TYPE_LEVEL_HIGH>;
......
...@@ -77,51 +77,49 @@ &mdio { ...@@ -77,51 +77,49 @@ &mdio {
pinctrl-0 = <&mdio_pins>; pinctrl-0 = <&mdio_pins>;
status = "okay"; status = "okay";
switch@0 { ethernet-switch@0 {
compatible = "marvell,mv88e6190"; compatible = "marvell,mv88e6190";
#address-cells = <1>;
#interrupt-cells = <2>; #interrupt-cells = <2>;
interrupt-controller; interrupt-controller;
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <7 IRQ_TYPE_LEVEL_LOW>; interrupts = <7 IRQ_TYPE_LEVEL_LOW>;
pinctrl-0 = <&switch_interrupt_pins>; pinctrl-0 = <&switch_interrupt_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
#size-cells = <0>;
reg = <0>; reg = <0>;
mdio { mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
switch0phy1: switch0phy1@1 { switch0phy1: ethernet-phy@1 {
reg = <0x1>; reg = <0x1>;
}; };
switch0phy2: switch0phy2@2 { switch0phy2: ethernet-phy@2 {
reg = <0x2>; reg = <0x2>;
}; };
switch0phy3: switch0phy3@3 { switch0phy3: ethernet-phy@3 {
reg = <0x3>; reg = <0x3>;
}; };
switch0phy4: switch0phy4@4 { switch0phy4: ethernet-phy@4 {
reg = <0x4>; reg = <0x4>;
}; };
switch0phy5: switch0phy5@5 { switch0phy5: ethernet-phy@5 {
reg = <0x5>; reg = <0x5>;
}; };
switch0phy6: switch0phy6@6 { switch0phy6: ethernet-phy@6 {
reg = <0x6>; reg = <0x6>;
}; };
switch0phy7: switch0phy7@7 { switch0phy7: ethernet-phy@7 {
reg = <0x7>; reg = <0x7>;
}; };
switch0phy8: switch0phy8@8 { switch0phy8: ethernet-phy@8 {
reg = <0x8>; reg = <0x8>;
}; };
}; };
...@@ -142,11 +140,11 @@ phy2: ethernet-phy@c { ...@@ -142,11 +140,11 @@ phy2: ethernet-phy@c {
}; };
}; };
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { ethernet-port@0 {
ethernet = <&eth0>; ethernet = <&eth0>;
phy-mode = "rgmii"; phy-mode = "rgmii";
reg = <0>; reg = <0>;
...@@ -158,55 +156,55 @@ fixed-link { ...@@ -158,55 +156,55 @@ fixed-link {
}; };
}; };
port@1 { ethernet-port@1 {
label = "lan1"; label = "lan1";
phy-handle = <&switch0phy1>; phy-handle = <&switch0phy1>;
reg = <1>; reg = <1>;
}; };
port@2 { ethernet-port@2 {
label = "lan2"; label = "lan2";
phy-handle = <&switch0phy2>; phy-handle = <&switch0phy2>;
reg = <2>; reg = <2>;
}; };
port@3 { ethernet-port@3 {
label = "lan3"; label = "lan3";
phy-handle = <&switch0phy3>; phy-handle = <&switch0phy3>;
reg = <3>; reg = <3>;
}; };
port@4 { ethernet-port@4 {
label = "lan4"; label = "lan4";
phy-handle = <&switch0phy4>; phy-handle = <&switch0phy4>;
reg = <4>; reg = <4>;
}; };
port@5 { ethernet-port@5 {
label = "lan5"; label = "lan5";
phy-handle = <&switch0phy5>; phy-handle = <&switch0phy5>;
reg = <5>; reg = <5>;
}; };
port@6 { ethernet-port@6 {
label = "lan6"; label = "lan6";
phy-handle = <&switch0phy6>; phy-handle = <&switch0phy6>;
reg = <6>; reg = <6>;
}; };
port@7 { ethernet-port@7 {
label = "lan7"; label = "lan7";
phy-handle = <&switch0phy7>; phy-handle = <&switch0phy7>;
reg = <7>; reg = <7>;
}; };
port@8 { ethernet-port@8 {
label = "lan8"; label = "lan8";
phy-handle = <&switch0phy8>; phy-handle = <&switch0phy8>;
reg = <8>; reg = <8>;
}; };
port@9 { ethernet-port@9 {
/* 88X3310P external phy */ /* 88X3310P external phy */
label = "lan9"; label = "lan9";
phy-handle = <&phy1>; phy-handle = <&phy1>;
...@@ -214,7 +212,7 @@ port@9 { ...@@ -214,7 +212,7 @@ port@9 {
reg = <9>; reg = <9>;
}; };
port@a { ethernet-port@a {
/* 88X3310P external phy */ /* 88X3310P external phy */
label = "lan10"; label = "lan10";
phy-handle = <&phy2>; phy-handle = <&phy2>;
......
...@@ -7,66 +7,66 @@ / { ...@@ -7,66 +7,66 @@ / {
}; };
&mdio { &mdio {
switch0: switch0@4 { switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6190"; compatible = "marvell,mv88e6190";
reg = <4>; reg = <4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>; pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan8"; label = "lan8";
phy-handle = <&switch0phy0>; phy-handle = <&switch0phy0>;
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan7"; label = "lan7";
phy-handle = <&switch0phy1>; phy-handle = <&switch0phy1>;
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan6"; label = "lan6";
phy-handle = <&switch0phy2>; phy-handle = <&switch0phy2>;
}; };
port@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "lan5"; label = "lan5";
phy-handle = <&switch0phy3>; phy-handle = <&switch0phy3>;
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
label = "lan4"; label = "lan4";
phy-handle = <&switch0phy4>; phy-handle = <&switch0phy4>;
}; };
port@6 { ethernet-port@6 {
reg = <6>; reg = <6>;
label = "lan3"; label = "lan3";
phy-handle = <&switch0phy5>; phy-handle = <&switch0phy5>;
}; };
port@7 { ethernet-port@7 {
reg = <7>; reg = <7>;
label = "lan2"; label = "lan2";
phy-handle = <&switch0phy6>; phy-handle = <&switch0phy6>;
}; };
port@8 { ethernet-port@8 {
reg = <8>; reg = <8>;
label = "lan1"; label = "lan1";
phy-handle = <&switch0phy7>; phy-handle = <&switch0phy7>;
}; };
port@10 { ethernet-port@10 {
reg = <10>; reg = <10>;
phy-mode = "2500base-x"; phy-mode = "2500base-x";
...@@ -83,35 +83,35 @@ mdio { ...@@ -83,35 +83,35 @@ mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
switch0phy0: switch0phy0@1 { switch0phy0: ethernet-phy@1 {
reg = <0x1>; reg = <0x1>;
}; };
switch0phy1: switch0phy1@2 { switch0phy1: ethernet-phy@2 {
reg = <0x2>; reg = <0x2>;
}; };
switch0phy2: switch0phy2@3 { switch0phy2: ethernet-phy@3 {
reg = <0x3>; reg = <0x3>;
}; };
switch0phy3: switch0phy3@4 { switch0phy3: ethernet-phy@4 {
reg = <0x4>; reg = <0x4>;
}; };
switch0phy4: switch0phy4@5 { switch0phy4: ethernet-phy@5 {
reg = <0x5>; reg = <0x5>;
}; };
switch0phy5: switch0phy5@6 { switch0phy5: ethernet-phy@6 {
reg = <0x6>; reg = <0x6>;
}; };
switch0phy6: switch0phy6@7 { switch0phy6: ethernet-phy@7 {
reg = <0x7>; reg = <0x7>;
}; };
switch0phy7: switch0phy7@8 { switch0phy7: ethernet-phy@8 {
reg = <0x8>; reg = <0x8>;
}; };
}; };
......
...@@ -11,42 +11,42 @@ &sfp0 { ...@@ -11,42 +11,42 @@ &sfp0 {
}; };
&mdio { &mdio {
switch0: switch0@4 { switch0: ethernet-switch@4 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
reg = <4>; reg = <4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&cf_gtr_switch_reset_pins>; pinctrl-0 = <&cf_gtr_switch_reset_pins>;
reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>; reset-gpios = <&gpio0 18 GPIO_ACTIVE_LOW>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan2"; label = "lan2";
phy-handle = <&switch0phy0>; phy-handle = <&switch0phy0>;
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan1"; label = "lan1";
phy-handle = <&switch0phy1>; phy-handle = <&switch0phy1>;
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan4"; label = "lan4";
phy-handle = <&switch0phy2>; phy-handle = <&switch0phy2>;
}; };
port@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "lan3"; label = "lan3";
phy-handle = <&switch0phy3>; phy-handle = <&switch0phy3>;
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
phy-mode = "2500base-x"; phy-mode = "2500base-x";
ethernet = <&eth1>; ethernet = <&eth1>;
...@@ -63,19 +63,19 @@ mdio { ...@@ -63,19 +63,19 @@ mdio {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
switch0phy0: switch0phy0@11 { switch0phy0: ethernet-phy@11 {
reg = <0x11>; reg = <0x11>;
}; };
switch0phy1: switch0phy1@12 { switch0phy1: ethernet-phy@12 {
reg = <0x12>; reg = <0x12>;
}; };
switch0phy2: switch0phy2@13 { switch0phy2: ethernet-phy@13 {
reg = <0x13>; reg = <0x13>;
}; };
switch0phy3: switch0phy3@14 { switch0phy3: ethernet-phy@14 {
reg = <0x14>; reg = <0x14>;
}; };
}; };
......
...@@ -158,42 +158,40 @@ nand: nand@0 { ...@@ -158,42 +158,40 @@ nand: nand@0 {
&mdio { &mdio {
status = "okay"; status = "okay";
switch@0 { ethernet-switch@0 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; reg = <0>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { ethernet-port@0 {
reg = <0>; reg = <0>;
label = "lan4"; label = "lan4";
}; };
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan3"; label = "lan3";
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan2"; label = "lan2";
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan1"; label = "lan1";
}; };
port@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "wan"; label = "wan";
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
phy-mode = "sgmii"; phy-mode = "sgmii";
ethernet = <&eth2>; ethernet = <&eth2>;
......
...@@ -435,12 +435,10 @@ phy1: ethernet-phy@1 { ...@@ -435,12 +435,10 @@ phy1: ethernet-phy@1 {
}; };
/* Switch MV88E6176 at address 0x10 */ /* Switch MV88E6176 at address 0x10 */
switch@10 { ethernet-switch@10 {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&swint_pins>; pinctrl-0 = <&swint_pins>;
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
dsa,member = <0 0>; dsa,member = <0 0>;
reg = <0x10>; reg = <0x10>;
...@@ -448,36 +446,36 @@ switch@10 { ...@@ -448,36 +446,36 @@ switch@10 {
interrupt-parent = <&gpio1>; interrupt-parent = <&gpio1>;
interrupts = <13 IRQ_TYPE_LEVEL_LOW>; interrupts = <13 IRQ_TYPE_LEVEL_LOW>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
ports@0 { ethernet-port@0 {
reg = <0>; reg = <0>;
label = "lan0"; label = "lan0";
}; };
ports@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan1"; label = "lan1";
}; };
ports@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan2"; label = "lan2";
}; };
ports@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan3"; label = "lan3";
}; };
ports@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "lan4"; label = "lan4";
}; };
ports@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
ethernet = <&eth1>; ethernet = <&eth1>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
...@@ -488,7 +486,7 @@ fixed-link { ...@@ -488,7 +486,7 @@ fixed-link {
}; };
}; };
ports@6 { ethernet-port@6 {
reg = <6>; reg = <6>;
ethernet = <&eth0>; ethernet = <&eth0>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
......
...@@ -92,44 +92,42 @@ pcie2-0-w-disable-hog { ...@@ -92,44 +92,42 @@ pcie2-0-w-disable-hog {
&mdio { &mdio {
status = "okay"; status = "okay";
switch@4 { ethernet-switch@4 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <4>; reg = <4>;
pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>; pinctrl-0 = <&clearfog_dsa0_clk_pins &clearfog_dsa0_pins>;
pinctrl-names = "default"; pinctrl-names = "default";
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { ethernet-port@0 {
reg = <0>; reg = <0>;
label = "lan5"; label = "lan5";
}; };
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan4"; label = "lan4";
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan3"; label = "lan3";
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan2"; label = "lan2";
}; };
port@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "lan1"; label = "lan1";
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
ethernet = <&eth1>; ethernet = <&eth1>;
phy-mode = "1000base-x"; phy-mode = "1000base-x";
...@@ -140,7 +138,7 @@ fixed-link { ...@@ -140,7 +138,7 @@ fixed-link {
}; };
}; };
port@6 { ethernet-port@6 {
/* 88E1512 external phy */ /* 88E1512 external phy */
reg = <6>; reg = <6>;
label = "lan6"; label = "lan6";
......
...@@ -265,42 +265,40 @@ flash@0 { ...@@ -265,42 +265,40 @@ flash@0 {
&mdio { &mdio {
status = "okay"; status = "okay";
switch@0 { ethernet-switch@0 {
compatible = "marvell,mv88e6085"; compatible = "marvell,mv88e6085";
#address-cells = <1>;
#size-cells = <0>;
reg = <0>; reg = <0>;
ports { ethernet-ports {
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
port@0 { ethernet-port@0 {
reg = <0>; reg = <0>;
label = "lan4"; label = "lan4";
}; };
port@1 { ethernet-port@1 {
reg = <1>; reg = <1>;
label = "lan3"; label = "lan3";
}; };
port@2 { ethernet-port@2 {
reg = <2>; reg = <2>;
label = "lan2"; label = "lan2";
}; };
port@3 { ethernet-port@3 {
reg = <3>; reg = <3>;
label = "lan1"; label = "lan1";
}; };
port@4 { ethernet-port@4 {
reg = <4>; reg = <4>;
label = "internet"; label = "internet";
}; };
port@5 { ethernet-port@5 {
reg = <5>; reg = <5>;
phy-mode = "rgmii-id"; phy-mode = "rgmii-id";
ethernet = <&eth0>; ethernet = <&eth0>;
......
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