Commit 2bd1b5e2 authored by Linus Torvalds's avatar Linus Torvalds

Merge bk://bk.arm.linux.org.uk/linux-2.6-rmk

into ppc970.osdl.org:/home/torvalds/v2.6/linux
parents 5f4e3bbd b99c2a51
......@@ -68,7 +68,6 @@
* f1200000 12000000 EBI registers
* f1300000 13000000 Counter/Timer
* f1400000 14000000 Interrupt controller
* f1500000 15000000 RTC
* f1600000 16000000 UART 0
* f1700000 17000000 UART 1
* f1a00000 1a000000 Debug LEDs
......@@ -81,7 +80,6 @@ static struct map_desc ap_io_desc[] __initdata = {
{ IO_ADDRESS(INTEGRATOR_EBI_BASE), INTEGRATOR_EBI_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_CT_BASE), INTEGRATOR_CT_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_IC_BASE), INTEGRATOR_IC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_RTC_BASE), INTEGRATOR_RTC_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_UART0_BASE), INTEGRATOR_UART0_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_UART1_BASE), INTEGRATOR_UART1_BASE, SZ_4K, MT_DEVICE },
{ IO_ADDRESS(INTEGRATOR_DBG_BASE), INTEGRATOR_DBG_BASE, SZ_4K, MT_DEVICE },
......
/*
* linux/arch/arm/mach-integrator/time.c
*
* Copyright (C) 2000-2001 Deep Blue Solutions
* Copyright (C) 2000-2001 Deep Blue Solutions Ltd.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/module.h>
#include <linux/kernel.h>
#include <linux/time.h>
#include <linux/mc146818rtc.h>
#include <linux/interrupt.h>
#include <linux/init.h>
#include <linux/device.h>
#include <asm/hardware/amba.h>
#include <asm/hardware.h>
#include <asm/io.h>
#include <asm/uaccess.h>
#include <asm/rtc.h>
#define RTC_DR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 0)
#define RTC_MR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 4)
#define RTC_STAT (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 8)
#define RTC_EOI (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 8)
#define RTC_LR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 12)
#define RTC_CR (IO_ADDRESS(INTEGRATOR_RTC_BASE) + 16)
#define RTC_CR_MIE 0x00000001
#define RTC_DR (0)
#define RTC_MR (4)
#define RTC_STAT (8)
#define RTC_EOI (8)
#define RTC_LR (12)
#define RTC_CR (16)
#define RTC_CR_MIE (1 << 0)
extern int (*set_rtc)(void);
static void *rtc_base;
static int integrator_set_rtc(void)
{
__raw_writel(xtime.tv_sec, RTC_LR);
__raw_writel(xtime.tv_sec, rtc_base + RTC_LR);
return 1;
}
static int integrator_rtc_init(void)
static void rtc_read_alarm(struct rtc_wkalrm *alrm)
{
rtc_time_to_tm(readl(rtc_base + RTC_MR), &alrm->time);
}
static int rtc_set_alarm(struct rtc_wkalrm *alrm)
{
unsigned long time;
int ret;
ret = rtc_tm_to_time(&alrm->time, &time);
if (ret == 0)
writel(time, rtc_base + RTC_MR);
return ret;
}
static void rtc_read_time(struct rtc_time *tm)
{
__raw_writel(0, RTC_CR);
__raw_writel(0, RTC_EOI);
rtc_time_to_tm(readl(rtc_base + RTC_DR), tm);
}
/*
* Set the RTC time. Unfortunately, we can't accurately set
* the point at which the counter updates.
*
* Also, since RTC_LR is transferred to RTC_CR on next rising
* edge of the 1Hz clock, we must write the time one second
* in advance.
*/
static int rtc_set_time(struct rtc_time *tm)
{
unsigned long time;
int ret;
ret = rtc_tm_to_time(tm, &time);
if (ret == 0)
writel(time + 1, rtc_base + RTC_LR);
return ret;
}
static struct rtc_ops rtc_ops = {
.owner = THIS_MODULE,
.read_time = rtc_read_time,
.set_time = rtc_set_time,
.read_alarm = rtc_read_alarm,
.set_alarm = rtc_set_alarm,
};
static irqreturn_t rtc_interrupt(int irq, void *dev_id, struct pt_regs *regs)
{
writel(0, rtc_base + RTC_EOI);
return IRQ_HANDLED;
}
static int rtc_probe(struct amba_device *dev, void *id)
{
int ret;
if (rtc_base)
return -EBUSY;
ret = amba_request_regions(dev, NULL);
if (ret)
goto out;
rtc_base = ioremap(dev->res.start, SZ_4K);
if (!rtc_base) {
ret = -ENOMEM;
goto res_out;
}
__raw_writel(0, rtc_base + RTC_CR);
__raw_writel(0, rtc_base + RTC_EOI);
xtime.tv_sec = __raw_readl(rtc_base + RTC_DR);
ret = request_irq(dev->irq[0], rtc_interrupt, SA_INTERRUPT,
"rtc-pl030", rtc_base);
if (ret)
goto map_out;
xtime.tv_sec = __raw_readl(RTC_DR);
ret = register_rtc(&rtc_ops);
if (ret)
goto irq_out;
set_rtc = integrator_set_rtc;
return 0;
irq_out:
free_irq(dev->irq[0], rtc_base);
map_out:
iounmap(rtc_base);
rtc_base = NULL;
res_out:
amba_release_regions(dev);
out:
return ret;
}
static int rtc_remove(struct amba_device *dev)
{
set_rtc = NULL;
writel(0, rtc_base + RTC_CR);
free_irq(dev->irq[0], rtc_base);
unregister_rtc(&rtc_ops);
iounmap(rtc_base);
rtc_base = NULL;
amba_release_regions(dev);
return 0;
}
static struct timespec rtc_delta;
static int rtc_suspend(struct amba_device *dev, u32 state)
{
struct timespec rtc;
rtc.tv_sec = readl(rtc_base + RTC_DR);
rtc.tv_nsec = 0;
save_time_delta(&rtc_delta, &rtc);
return 0;
}
__initcall(integrator_rtc_init);
static int rtc_resume(struct amba_device *dev)
{
struct timespec rtc;
rtc.tv_sec = readl(rtc_base + RTC_DR);
rtc.tv_nsec = 0;
restore_time_delta(&rtc_delta, &rtc);
return 0;
}
static struct amba_id rtc_ids[] = {
{
.id = 0x00041030,
.mask = 0x000fffff,
},
{ 0, 0 },
};
static struct amba_driver rtc_driver = {
.drv = {
.name = "rtc-pl030",
},
.probe = rtc_probe,
.remove = rtc_remove,
.suspend = rtc_suspend,
.resume = rtc_resume,
.id_table = rtc_ids,
};
static int __init integrator_rtc_init(void)
{
return amba_driver_register(&rtc_driver);
}
static void __exit integrator_rtc_exit(void)
{
amba_driver_unregister(&rtc_driver);
}
module_init(integrator_rtc_init);
module_exit(integrator_rtc_exit);
......@@ -21,6 +21,19 @@
subs \irqnr, \base, \irqnr
1001:
/*
* IXP465 has an upper IRQ status register
*/
#if defined(CONFIG_CPU_IXP46X)
bne 1002f
ldr \irqstat, =(IXP4XX_INTC_BASE_VIRT+IXP4XX_ICIP2_OFFSET)
ldr \irqstat, [\irqstat] @ get upper interrupts
mov \irqnr, #63
clz \irqstat, \irqstat
cmp \irqstat, #32
subne \irqnr, \irqnr, \irqstat
1002:
#endif
.endm
......@@ -27,6 +27,13 @@
#define pcibios_assign_all_busses() 1
#if defined(CONFIG_CPU_IXP465) && !defined(__ASSEMBLY__)
extern unsigned int processor_id;
#define cpu_is_ixp465() ((processor_id & 0xffffffc0) == 0x69054200)
#else
#define cpu_is_ixp465() (0)
#endif
/* Register locations and bits */
#include "ixp4xx-regs.h"
......
......@@ -15,7 +15,6 @@
#ifndef _ARCH_IXP4XX_IRQS_H_
#define _ARCH_IXP4XX_IRQS_H_
#define NR_IRQS 32
#define IRQ_IXP4XX_NPEA 0
#define IRQ_IXP4XX_NPEB 1
......@@ -50,6 +49,27 @@
#define IRQ_IXP4XX_SW_INT1 30
#define IRQ_IXP4XX_SW_INT2 31
#ifndef CONFIG_CPU_IXP46X
#define NR_IRQS 32
#else
/*
* IXP465 adds new sources
*/
#define IRQ_IXP4XX_USB_HOST 32
#define IRQ_IXP4XX_I2C 33
#define IRQ_IXP4XX_SSP 34
#define IRQ_IXP4XX_TSYNC 35
#define IRQ_IXP4XX_EAU_DONE 36
#define IRQ_IXP4XX_SHA_DONE 37
#define IRQ_IXP4XX_SWCP_PE 58
#define IRQ_IXP4XX_QM_PE 60
#define IRQ_IXP4XX_MCU_ECC 61
#define IRQ_IXP4XX_EXP_PE 62
#define NR_IRQS 64
#endif
#define XSCALE_PMU_IRQ (IRQ_IXP4XX_XSCALE_PMU)
/*
......
......@@ -129,6 +129,17 @@
#define IXP4XX_ICIH_OFFSET 0x18 /* IRQ Highest Pri Int */
#define IXP4XX_ICFH_OFFSET 0x1C /* FIQ Highest Pri Int */
/*
* IXP465-only
*/
#define IXP4XX_ICPR2_OFFSET 0x20 /* Interrupt Status 2 */
#define IXP4XX_ICMR2_OFFSET 0x24 /* Interrupt Enable 2 */
#define IXP4XX_ICLR2_OFFSET 0x28 /* Interrupt IRQ/FIQ Select 2 */
#define IXP4XX_ICIP2_OFFSET 0x2C /* IRQ Status */
#define IXP4XX_ICFP2_OFFSET 0x30 /* FIQ Status */
#define IXP4XX_ICEEN_OFFSET 0x34 /* Error High Pri Enable */
/*
* Interrupt Controller Register Definitions.
*/
......@@ -143,6 +154,12 @@
#define IXP4XX_ICHR IXP4XX_INTC_REG(IXP4XX_ICHR_OFFSET)
#define IXP4XX_ICIH IXP4XX_INTC_REG(IXP4XX_ICIH_OFFSET)
#define IXP4XX_ICFH IXP4XX_INTC_REG(IXP4XX_ICFH_OFFSET)
#define IXP4XX_ICPR2 IXP4XX_INTC_REG(IXP4XX_ICPR2_OFFSET)
#define IXP4XX_ICMR2 IXP4XX_INTC_REG(IXP4XX_ICMR2_OFFSET)
#define IXP4XX_ICLR2 IXP4XX_INTC_REG(IXP4XX_ICLR2_OFFSET)
#define IXP4XX_ICIP2 IXP4XX_INTC_REG(IXP4XX_ICIP2_OFFSET)
#define IXP4XX_ICFP2 IXP4XX_INTC_REG(IXP4XX_ICFP2_OFFSET)
#define IXP4XX_ICEEN IXP4XX_INTC_REG(IXP4XX_ICEEN_OFFSET)
/*
* Constants to make it easy to access GPIO registers
......@@ -548,4 +565,19 @@
#define DCMD_LENGTH 0x01fff /* length mask (max = 8K - 1) */
#ifndef __ASSEMBLY__
static inline int cpu_is_ixp46x(void)
{
#ifdef CONFIG_CPU_IXP46X
unsigned int processor_id;
asm("mrc p15, 0, %0, cr0, cr0, 0;" : "=r"(processor_id) :);
if ((processor_id & 0xffffff00) == 0x69054200)
return 1;
#endif
return 0;
}
#endif
#endif
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