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Commit 2bd7c3e1 authored by David S. Miller's avatar David S. Miller
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Merge branch 'net-hns3-add-some-optimizations-and-cleanups' 

Huazhong Tan says:

====================
net: hns3: add some optimizations and cleanups

This series adds some code optimizations and cleanups for
the HNS3 ethernet driver.

[patch 1/9] dumps some debug information when reset fail.

[patch 2/9] dumps some struct netdev_queue information when
TX timeout.

[patch 3/9] cleanups some magic numbers.

[patch 4/9] cleanups some coding style issue.

[patch 5/9] fixes a compiler warning.

[patch 6/9] optimizes some local variable initialization.

[patch 7/9] modifies some comments.

[patch 8/9] cleanups some print format warnings.

[patch 9/9] cleanups byte order issue.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 79697744 39edaf24
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Showing with 278 additions and 207 deletions
drivers/net/ethernet/hisilicon/hns3/hclge_mbx.h
View file @ 2bd7c3e1
...@@ -47,7 +47,7 @@ enum HCLGE_MBX_OPCODE { ...@@ -47,7 +47,7 @@ enum HCLGE_MBX_OPCODE {
HCLGE_MBX_GET_MEDIA_TYPE, /* (VF -> PF) get media type */ HCLGE_MBX_GET_MEDIA_TYPE, /* (VF -> PF) get media type */
HCLGE_MBX_PUSH_PROMISC_INFO, /* (PF -> VF) push vf promisc info */ HCLGE_MBX_PUSH_PROMISC_INFO, /* (PF -> VF) push vf promisc info */
HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf reset status */ HCLGE_MBX_GET_VF_FLR_STATUS = 200, /* (M7 -> PF) get vf flr status */
HCLGE_MBX_PUSH_LINK_STATUS, /* (M7 -> PF) get port link status */ HCLGE_MBX_PUSH_LINK_STATUS, /* (M7 -> PF) get port link status */
HCLGE_MBX_NCSI_ERROR, /* (M7 -> PF) receive a NCSI error */ HCLGE_MBX_NCSI_ERROR, /* (M7 -> PF) receive a NCSI error */
}; };
...@@ -72,7 +72,7 @@ enum hclge_mbx_vlan_cfg_subcode { ...@@ -72,7 +72,7 @@ enum hclge_mbx_vlan_cfg_subcode {
}; };
#define HCLGE_MBX_MAX_MSG_SIZE 16 #define HCLGE_MBX_MAX_MSG_SIZE 16
#define HCLGE_MBX_MAX_RESP_DATA_SIZE 8 #define HCLGE_MBX_MAX_RESP_DATA_SIZE 8U
#define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM 3 #define HCLGE_MBX_RING_MAP_BASIC_MSG_NUM 3
#define HCLGE_MBX_RING_NODE_VARIABLE_NUM 3 #define HCLGE_MBX_RING_NODE_VARIABLE_NUM 3
......
drivers/net/ethernet/hisilicon/hns3/hnae3.c
View file @ 2bd7c3e1
...@@ -146,7 +146,7 @@ void hnae3_unregister_client(struct hnae3_client *client) ...@@ -146,7 +146,7 @@ void hnae3_unregister_client(struct hnae3_client *client)
return; return;
mutex_lock(&hnae3_common_lock); mutex_lock(&hnae3_common_lock);
/* one system should only have one client for every type */
list_for_each_entry(client_tmp, &hnae3_client_list, node) { list_for_each_entry(client_tmp, &hnae3_client_list, node) {
if (client_tmp->type == client->type) { if (client_tmp->type == client->type) {
existed = true; existed = true;
......
drivers/net/ethernet/hisilicon/hns3/hnae3.h
View file @ 2bd7c3e1
...@@ -130,7 +130,6 @@ enum hnae3_module_type { ...@@ -130,7 +130,6 @@ enum hnae3_module_type {
HNAE3_MODULE_TYPE_CR = 0x04, HNAE3_MODULE_TYPE_CR = 0x04,
HNAE3_MODULE_TYPE_KR = 0x05, HNAE3_MODULE_TYPE_KR = 0x05,
HNAE3_MODULE_TYPE_TP = 0x06, HNAE3_MODULE_TYPE_TP = 0x06,
}; };
enum hnae3_fec_mode { enum hnae3_fec_mode {
...@@ -576,7 +575,8 @@ struct hnae3_ae_algo { ...@@ -576,7 +575,8 @@ struct hnae3_ae_algo {
const struct pci_device_id *pdev_id_table; const struct pci_device_id *pdev_id_table;
}; };
#define HNAE3_INT_NAME_LEN (IFNAMSIZ + 16) #define HNAE3_INT_NAME_EXT_LEN 32 /* Max extra information length */
#define HNAE3_INT_NAME_LEN (IFNAMSIZ + HNAE3_INT_NAME_EXT_LEN)
#define HNAE3_ITR_COUNTDOWN_START 100 #define HNAE3_ITR_COUNTDOWN_START 100
struct hnae3_tc_info { struct hnae3_tc_info {
......
drivers/net/ethernet/hisilicon/hns3/hns3_debugfs.c
View file @ 2bd7c3e1
...@@ -57,68 +57,68 @@ static int hns3_dbg_queue_info(struct hnae3_handle *h, ...@@ -57,68 +57,68 @@ static int hns3_dbg_queue_info(struct hnae3_handle *h,
HNS3_RING_RX_RING_BASEADDR_H_REG); HNS3_RING_RX_RING_BASEADDR_H_REG);
base_add_l = readl_relaxed(ring->tqp->io_base + base_add_l = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BASEADDR_L_REG); HNS3_RING_RX_RING_BASEADDR_L_REG);
dev_info(&h->pdev->dev, "RX(%d) BASE ADD: 0x%08x%08x\n", i, dev_info(&h->pdev->dev, "RX(%u) BASE ADD: 0x%08x%08x\n", i,
base_add_h, base_add_l); base_add_h, base_add_l);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_NUM_REG); HNS3_RING_RX_RING_BD_NUM_REG);
dev_info(&h->pdev->dev, "RX(%d) RING BD NUM: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING BD NUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_BD_LEN_REG); HNS3_RING_RX_RING_BD_LEN_REG);
dev_info(&h->pdev->dev, "RX(%d) RING BD LEN: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING BD LEN: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_TAIL_REG); HNS3_RING_RX_RING_TAIL_REG);
dev_info(&h->pdev->dev, "RX(%d) RING TAIL: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING TAIL: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_HEAD_REG); HNS3_RING_RX_RING_HEAD_REG);
dev_info(&h->pdev->dev, "RX(%d) RING HEAD: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING HEAD: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_FBDNUM_REG); HNS3_RING_RX_RING_FBDNUM_REG);
dev_info(&h->pdev->dev, "RX(%d) RING FBDNUM: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING FBDNUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_RX_RING_PKTNUM_RECORD_REG); HNS3_RING_RX_RING_PKTNUM_RECORD_REG);
dev_info(&h->pdev->dev, "RX(%d) RING PKTNUM: %u\n", i, value); dev_info(&h->pdev->dev, "RX(%u) RING PKTNUM: %u\n", i, value);
ring = &priv->ring[i]; ring = &priv->ring[i];
base_add_h = readl_relaxed(ring->tqp->io_base + base_add_h = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BASEADDR_H_REG); HNS3_RING_TX_RING_BASEADDR_H_REG);
base_add_l = readl_relaxed(ring->tqp->io_base + base_add_l = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BASEADDR_L_REG); HNS3_RING_TX_RING_BASEADDR_L_REG);
dev_info(&h->pdev->dev, "TX(%d) BASE ADD: 0x%08x%08x\n", i, dev_info(&h->pdev->dev, "TX(%u) BASE ADD: 0x%08x%08x\n", i,
base_add_h, base_add_l); base_add_h, base_add_l);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_BD_NUM_REG); HNS3_RING_TX_RING_BD_NUM_REG);
dev_info(&h->pdev->dev, "TX(%d) RING BD NUM: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING BD NUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TC_REG); HNS3_RING_TX_RING_TC_REG);
dev_info(&h->pdev->dev, "TX(%d) RING TC: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING TC: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_TAIL_REG); HNS3_RING_TX_RING_TAIL_REG);
dev_info(&h->pdev->dev, "TX(%d) RING TAIL: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING TAIL: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_HEAD_REG); HNS3_RING_TX_RING_HEAD_REG);
dev_info(&h->pdev->dev, "TX(%d) RING HEAD: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING HEAD: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_FBDNUM_REG); HNS3_RING_TX_RING_FBDNUM_REG);
dev_info(&h->pdev->dev, "TX(%d) RING FBDNUM: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING FBDNUM: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_OFFSET_REG); HNS3_RING_TX_RING_OFFSET_REG);
dev_info(&h->pdev->dev, "TX(%d) RING OFFSET: %u\n", i, value); dev_info(&h->pdev->dev, "TX(%u) RING OFFSET: %u\n", i, value);
value = readl_relaxed(ring->tqp->io_base + value = readl_relaxed(ring->tqp->io_base +
HNS3_RING_TX_RING_PKTNUM_RECORD_REG); HNS3_RING_TX_RING_PKTNUM_RECORD_REG);
dev_info(&h->pdev->dev, "TX(%d) RING PKTNUM: %u\n\n", i, dev_info(&h->pdev->dev, "TX(%u) RING PKTNUM: %u\n\n", i,
value); value);
} }
...@@ -190,21 +190,24 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf) ...@@ -190,21 +190,24 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf)
addr = le64_to_cpu(tx_desc->addr); addr = le64_to_cpu(tx_desc->addr);
dev_info(dev, "TX Queue Num: %u, BD Index: %u\n", q_num, tx_index); dev_info(dev, "TX Queue Num: %u, BD Index: %u\n", q_num, tx_index);
dev_info(dev, "(TX)addr: %pad\n", &addr); dev_info(dev, "(TX)addr: %pad\n", &addr);
dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.vlan_tag); dev_info(dev, "(TX)vlan_tag: %u\n", le16_to_cpu(tx_desc->tx.vlan_tag));
dev_info(dev, "(TX)send_size: %u\n", tx_desc->tx.send_size); dev_info(dev, "(TX)send_size: %u\n",
le16_to_cpu(tx_desc->tx.send_size));
dev_info(dev, "(TX)vlan_tso: %u\n", tx_desc->tx.type_cs_vlan_tso); dev_info(dev, "(TX)vlan_tso: %u\n", tx_desc->tx.type_cs_vlan_tso);
dev_info(dev, "(TX)l2_len: %u\n", tx_desc->tx.l2_len); dev_info(dev, "(TX)l2_len: %u\n", tx_desc->tx.l2_len);
dev_info(dev, "(TX)l3_len: %u\n", tx_desc->tx.l3_len); dev_info(dev, "(TX)l3_len: %u\n", tx_desc->tx.l3_len);
dev_info(dev, "(TX)l4_len: %u\n", tx_desc->tx.l4_len); dev_info(dev, "(TX)l4_len: %u\n", tx_desc->tx.l4_len);
dev_info(dev, "(TX)vlan_tag: %u\n", tx_desc->tx.outer_vlan_tag); dev_info(dev, "(TX)vlan_tag: %u\n",
dev_info(dev, "(TX)tv: %u\n", tx_desc->tx.tv); le16_to_cpu(tx_desc->tx.outer_vlan_tag));
dev_info(dev, "(TX)tv: %u\n", le16_to_cpu(tx_desc->tx.tv));
dev_info(dev, "(TX)vlan_msec: %u\n", tx_desc->tx.ol_type_vlan_msec); dev_info(dev, "(TX)vlan_msec: %u\n", tx_desc->tx.ol_type_vlan_msec);
dev_info(dev, "(TX)ol2_len: %u\n", tx_desc->tx.ol2_len); dev_info(dev, "(TX)ol2_len: %u\n", tx_desc->tx.ol2_len);
dev_info(dev, "(TX)ol3_len: %u\n", tx_desc->tx.ol3_len); dev_info(dev, "(TX)ol3_len: %u\n", tx_desc->tx.ol3_len);
dev_info(dev, "(TX)ol4_len: %u\n", tx_desc->tx.ol4_len); dev_info(dev, "(TX)ol4_len: %u\n", tx_desc->tx.ol4_len);
dev_info(dev, "(TX)paylen: %u\n", tx_desc->tx.paylen); dev_info(dev, "(TX)paylen: %u\n", le32_to_cpu(tx_desc->tx.paylen));
dev_info(dev, "(TX)vld_ra_ri: %u\n", tx_desc->tx.bdtp_fe_sc_vld_ra_ri); dev_info(dev, "(TX)vld_ra_ri: %u\n",
dev_info(dev, "(TX)mss: %u\n", tx_desc->tx.mss); le16_to_cpu(tx_desc->tx.bdtp_fe_sc_vld_ra_ri));
dev_info(dev, "(TX)mss: %u\n", le16_to_cpu(tx_desc->tx.mss));
ring = &priv->ring[q_num + h->kinfo.num_tqps]; ring = &priv->ring[q_num + h->kinfo.num_tqps];
value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG); value = readl_relaxed(ring->tqp->io_base + HNS3_RING_RX_RING_TAIL_REG);
...@@ -214,15 +217,19 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf) ...@@ -214,15 +217,19 @@ static int hns3_dbg_bd_info(struct hnae3_handle *h, const char *cmd_buf)
addr = le64_to_cpu(rx_desc->addr); addr = le64_to_cpu(rx_desc->addr);
dev_info(dev, "RX Queue Num: %u, BD Index: %u\n", q_num, rx_index); dev_info(dev, "RX Queue Num: %u, BD Index: %u\n", q_num, rx_index);
dev_info(dev, "(RX)addr: %pad\n", &addr); dev_info(dev, "(RX)addr: %pad\n", &addr);
dev_info(dev, "(RX)l234_info: %u\n", rx_desc->rx.l234_info); dev_info(dev, "(RX)l234_info: %u\n",
dev_info(dev, "(RX)pkt_len: %u\n", rx_desc->rx.pkt_len); le32_to_cpu(rx_desc->rx.l234_info));
dev_info(dev, "(RX)size: %u\n", rx_desc->rx.size); dev_info(dev, "(RX)pkt_len: %u\n", le16_to_cpu(rx_desc->rx.pkt_len));
dev_info(dev, "(RX)rss_hash: %u\n", rx_desc->rx.rss_hash); dev_info(dev, "(RX)size: %u\n", le16_to_cpu(rx_desc->rx.size));
dev_info(dev, "(RX)fd_id: %u\n", rx_desc->rx.fd_id); dev_info(dev, "(RX)rss_hash: %u\n", le32_to_cpu(rx_desc->rx.rss_hash));
dev_info(dev, "(RX)vlan_tag: %u\n", rx_desc->rx.vlan_tag); dev_info(dev, "(RX)fd_id: %u\n", le16_to_cpu(rx_desc->rx.fd_id));
dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n", rx_desc->rx.o_dm_vlan_id_fb); dev_info(dev, "(RX)vlan_tag: %u\n", le16_to_cpu(rx_desc->rx.vlan_tag));
dev_info(dev, "(RX)ot_vlan_tag: %u\n", rx_desc->rx.ot_vlan_tag); dev_info(dev, "(RX)o_dm_vlan_id_fb: %u\n",
dev_info(dev, "(RX)bd_base_info: %u\n", rx_desc->rx.bd_base_info); le16_to_cpu(rx_desc->rx.o_dm_vlan_id_fb));
dev_info(dev, "(RX)ot_vlan_tag: %u\n",
le16_to_cpu(rx_desc->rx.ot_vlan_tag));
dev_info(dev, "(RX)bd_base_info: %u\n",
le32_to_cpu(rx_desc->rx.bd_base_info));
return 0; return 0;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3_enet.c
View file @ 2bd7c3e1
...@@ -1710,8 +1710,8 @@ static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan, ...@@ -1710,8 +1710,8 @@ static int hns3_ndo_set_vf_vlan(struct net_device *netdev, int vf, u16 vlan,
int ret = -EIO; int ret = -EIO;
netif_dbg(h, drv, netdev, netif_dbg(h, drv, netdev,
"set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=%u\n", "set vf vlan: vf=%d, vlan=%u, qos=%u, vlan_proto=0x%x\n",
vf, vlan, qos, vlan_proto); vf, vlan, qos, ntohs(vlan_proto));
if (h->ae_algo->ops->set_vf_vlan_filter) if (h->ae_algo->ops->set_vf_vlan_filter)
ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan, ret = h->ae_algo->ops->set_vf_vlan_filter(h, vf, vlan,
...@@ -1771,7 +1771,7 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) ...@@ -1771,7 +1771,7 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
{ {
struct hns3_nic_priv *priv = netdev_priv(ndev); struct hns3_nic_priv *priv = netdev_priv(ndev);
struct hnae3_handle *h = hns3_get_handle(ndev); struct hnae3_handle *h = hns3_get_handle(ndev);
struct hns3_enet_ring *tx_ring = NULL; struct hns3_enet_ring *tx_ring;
struct napi_struct *napi; struct napi_struct *napi;
int timeout_queue = 0; int timeout_queue = 0;
int hw_head, hw_tail; int hw_head, hw_tail;
...@@ -1792,6 +1792,9 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev) ...@@ -1792,6 +1792,9 @@ static bool hns3_get_tx_timeo_queue_info(struct net_device *ndev)
time_after(jiffies, time_after(jiffies,
(trans_start + ndev->watchdog_timeo))) { (trans_start + ndev->watchdog_timeo))) {
timeout_queue = i; timeout_queue = i;
netdev_info(ndev, "queue state: 0x%lx, delta msecs: %u\n",
q->state,
jiffies_to_msecs(jiffies - trans_start));
break; break;
} }
} }
...@@ -1999,7 +2002,7 @@ bool hns3_is_phys_func(struct pci_dev *pdev) ...@@ -1999,7 +2002,7 @@ bool hns3_is_phys_func(struct pci_dev *pdev)
case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF: case HNAE3_DEV_ID_100G_RDMA_DCB_PFC_VF:
return false; return false;
default: default:
dev_warn(&pdev->dev, "un-recognized pci device-id %d", dev_warn(&pdev->dev, "un-recognized pci device-id %u",
dev_id); dev_id);
} }
...@@ -3936,14 +3939,14 @@ static void hns3_info_show(struct hns3_nic_priv *priv) ...@@ -3936,14 +3939,14 @@ static void hns3_info_show(struct hns3_nic_priv *priv)
struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo; struct hnae3_knic_private_info *kinfo = &priv->ae_handle->kinfo;
dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr); dev_info(priv->dev, "MAC address: %pM\n", priv->netdev->dev_addr);
dev_info(priv->dev, "Task queue pairs numbers: %d\n", kinfo->num_tqps); dev_info(priv->dev, "Task queue pairs numbers: %u\n", kinfo->num_tqps);
dev_info(priv->dev, "RSS size: %d\n", kinfo->rss_size); dev_info(priv->dev, "RSS size: %u\n", kinfo->rss_size);
dev_info(priv->dev, "Allocated RSS size: %d\n", kinfo->req_rss_size); dev_info(priv->dev, "Allocated RSS size: %u\n", kinfo->req_rss_size);
dev_info(priv->dev, "RX buffer length: %d\n", kinfo->rx_buf_len); dev_info(priv->dev, "RX buffer length: %u\n", kinfo->rx_buf_len);
dev_info(priv->dev, "Desc num per TX queue: %d\n", kinfo->num_tx_desc); dev_info(priv->dev, "Desc num per TX queue: %u\n", kinfo->num_tx_desc);
dev_info(priv->dev, "Desc num per RX queue: %d\n", kinfo->num_rx_desc); dev_info(priv->dev, "Desc num per RX queue: %u\n", kinfo->num_rx_desc);
dev_info(priv->dev, "Total number of enabled TCs: %d\n", kinfo->num_tc); dev_info(priv->dev, "Total number of enabled TCs: %u\n", kinfo->num_tc);
dev_info(priv->dev, "Max mtu size: %d\n", priv->netdev->max_mtu); dev_info(priv->dev, "Max mtu size: %u\n", priv->netdev->max_mtu);
} }
static int hns3_client_init(struct hnae3_handle *handle) static int hns3_client_init(struct hnae3_handle *handle)
...@@ -4563,7 +4566,7 @@ int hns3_set_channels(struct net_device *netdev, ...@@ -4563,7 +4566,7 @@ int hns3_set_channels(struct net_device *netdev,
if (new_tqp_num > hns3_get_max_available_channels(h) || if (new_tqp_num > hns3_get_max_available_channels(h) ||
new_tqp_num < 1) { new_tqp_num < 1) {
dev_err(&netdev->dev, dev_err(&netdev->dev,
"Change tqps fail, the tqp range is from 1 to %d", "Change tqps fail, the tqp range is from 1 to %u",
hns3_get_max_available_channels(h)); hns3_get_max_available_channels(h));
return -EINVAL; return -EINVAL;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3_enet.h
View file @ 2bd7c3e1
...@@ -186,7 +186,7 @@ enum hns3_nic_state { ...@@ -186,7 +186,7 @@ enum hns3_nic_state {
#define HNS3_TXD_MSS_S 0 #define HNS3_TXD_MSS_S 0
#define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S) #define HNS3_TXD_MSS_M (0x3fff << HNS3_TXD_MSS_S)
#define HNS3_TX_LAST_SIZE_M 0xffff #define HNS3_TX_LAST_SIZE_M 0xffff
#define HNS3_VECTOR_TX_IRQ BIT_ULL(0) #define HNS3_VECTOR_TX_IRQ BIT_ULL(0)
#define HNS3_VECTOR_RX_IRQ BIT_ULL(1) #define HNS3_VECTOR_RX_IRQ BIT_ULL(1)
...@@ -313,7 +313,7 @@ struct hns3_desc_cb { ...@@ -313,7 +313,7 @@ struct hns3_desc_cb {
u16 reuse_flag; u16 reuse_flag;
/* desc type, used by the ring user to mark the type of the priv data */ /* desc type, used by the ring user to mark the type of the priv data */
u16 type; u16 type;
}; };
......
drivers/net/ethernet/hisilicon/hns3/hns3_ethtool.c
View file @ 2bd7c3e1
...@@ -985,7 +985,7 @@ static int hns3_set_ringparam(struct net_device *ndev, ...@@ -985,7 +985,7 @@ static int hns3_set_ringparam(struct net_device *ndev,
} }
netdev_info(ndev, netdev_info(ndev,
"Changing Tx/Rx ring depth from %d/%d to %d/%d\n", "Changing Tx/Rx ring depth from %u/%u to %u/%u\n",
old_tx_desc_num, old_rx_desc_num, old_tx_desc_num, old_rx_desc_num,
new_tx_desc_num, new_rx_desc_num); new_tx_desc_num, new_rx_desc_num);
...@@ -1097,7 +1097,7 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue, ...@@ -1097,7 +1097,7 @@ static int hns3_get_coalesce_per_queue(struct net_device *netdev, u32 queue,
if (queue >= queue_num) { if (queue >= queue_num) {
netdev_err(netdev, netdev_err(netdev,
"Invalid queue value %d! Queue max id=%d\n", "Invalid queue value %u! Queue max id=%u\n",
queue, queue_num - 1); queue, queue_num - 1);
return -EINVAL; return -EINVAL;
} }
...@@ -1147,14 +1147,14 @@ static int hns3_check_gl_coalesce_para(struct net_device *netdev, ...@@ -1147,14 +1147,14 @@ static int hns3_check_gl_coalesce_para(struct net_device *netdev,
rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs); rx_gl = hns3_gl_round_down(cmd->rx_coalesce_usecs);
if (rx_gl != cmd->rx_coalesce_usecs) { if (rx_gl != cmd->rx_coalesce_usecs) {
netdev_info(netdev, netdev_info(netdev,
"rx_usecs(%d) rounded down to %d, because it must be multiple of 2.\n", "rx_usecs(%u) rounded down to %u, because it must be multiple of 2.\n",
cmd->rx_coalesce_usecs, rx_gl); cmd->rx_coalesce_usecs, rx_gl);
} }
tx_gl = hns3_gl_round_down(cmd->tx_coalesce_usecs); tx_gl = hns3_gl_round_down(cmd->tx_coalesce_usecs);
if (tx_gl != cmd->tx_coalesce_usecs) { if (tx_gl != cmd->tx_coalesce_usecs) {
netdev_info(netdev, netdev_info(netdev,
"tx_usecs(%d) rounded down to %d, because it must be multiple of 2.\n", "tx_usecs(%u) rounded down to %u, because it must be multiple of 2.\n",
cmd->tx_coalesce_usecs, tx_gl); cmd->tx_coalesce_usecs, tx_gl);
} }
...@@ -1182,7 +1182,7 @@ static int hns3_check_rl_coalesce_para(struct net_device *netdev, ...@@ -1182,7 +1182,7 @@ static int hns3_check_rl_coalesce_para(struct net_device *netdev,
rl = hns3_rl_round_down(cmd->rx_coalesce_usecs_high); rl = hns3_rl_round_down(cmd->rx_coalesce_usecs_high);
if (rl != cmd->rx_coalesce_usecs_high) { if (rl != cmd->rx_coalesce_usecs_high) {
netdev_info(netdev, netdev_info(netdev,
"usecs_high(%d) rounded down to %d, because it must be multiple of 4.\n", "usecs_high(%u) rounded down to %u, because it must be multiple of 4.\n",
cmd->rx_coalesce_usecs_high, rl); cmd->rx_coalesce_usecs_high, rl);
} }
...@@ -1211,7 +1211,7 @@ static int hns3_check_coalesce_para(struct net_device *netdev, ...@@ -1211,7 +1211,7 @@ static int hns3_check_coalesce_para(struct net_device *netdev,
if (cmd->use_adaptive_tx_coalesce == 1 || if (cmd->use_adaptive_tx_coalesce == 1 ||
cmd->use_adaptive_rx_coalesce == 1) { cmd->use_adaptive_rx_coalesce == 1) {
netdev_info(netdev, netdev_info(netdev,
"adaptive-tx=%d and adaptive-rx=%d, tx_usecs or rx_usecs will changed dynamically.\n", "adaptive-tx=%u and adaptive-rx=%u, tx_usecs or rx_usecs will changed dynamically.\n",
cmd->use_adaptive_tx_coalesce, cmd->use_adaptive_tx_coalesce,
cmd->use_adaptive_rx_coalesce); cmd->use_adaptive_rx_coalesce);
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.c
View file @ 2bd7c3e1
...@@ -145,7 +145,7 @@ static int hclge_cmd_csq_clean(struct hclge_hw *hw) ...@@ -145,7 +145,7 @@ static int hclge_cmd_csq_clean(struct hclge_hw *hw)
rmb(); /* Make sure head is ready before touch any data */ rmb(); /* Make sure head is ready before touch any data */
if (!is_valid_csq_clean_head(csq, head)) { if (!is_valid_csq_clean_head(csq, head)) {
dev_warn(&hdev->pdev->dev, "wrong cmd head (%d, %d-%d)\n", head, dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
csq->next_to_use, csq->next_to_clean); csq->next_to_use, csq->next_to_clean);
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"Disabling any further commands to IMP firmware\n"); "Disabling any further commands to IMP firmware\n");
...@@ -314,11 +314,10 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num) ...@@ -314,11 +314,10 @@ int hclge_cmd_send(struct hclge_hw *hw, struct hclge_desc *desc, int num)
} while (timeout < hw->cmq.tx_timeout); } while (timeout < hw->cmq.tx_timeout);
} }
if (!complete) { if (!complete)
retval = -EBADE; retval = -EBADE;
} else { else
retval = hclge_cmd_check_retval(hw, desc, num, ntc); retval = hclge_cmd_check_retval(hw, desc, num, ntc);
}
/* Clean the command send queue */ /* Clean the command send queue */
handle = hclge_cmd_csq_clean(hw); handle = hclge_cmd_csq_clean(hw);
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_cmd.h
View file @ 2bd7c3e1
...@@ -8,6 +8,7 @@ ...@@ -8,6 +8,7 @@
#include <linux/etherdevice.h> #include <linux/etherdevice.h>
#define HCLGE_CMDQ_TX_TIMEOUT 30000 #define HCLGE_CMDQ_TX_TIMEOUT 30000
#define HCLGE_DESC_DATA_LEN 6
struct hclge_dev; struct hclge_dev;
struct hclge_desc { struct hclge_desc {
...@@ -19,7 +20,7 @@ struct hclge_desc { ...@@ -19,7 +20,7 @@ struct hclge_desc {
__le16 flag; __le16 flag;
__le16 retval; __le16 retval;
__le16 rsv; __le16 rsv;
__le32 data[6]; __le32 data[HCLGE_DESC_DATA_LEN];
}; };
struct hclge_cmq_ring { struct hclge_cmq_ring {
...@@ -260,6 +261,7 @@ enum hclge_opcode_type { ...@@ -260,6 +261,7 @@ enum hclge_opcode_type {
/* NCL config command */ /* NCL config command */
HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011, HCLGE_OPC_QUERY_NCL_CONFIG = 0x7011,
/* M7 stats command */ /* M7 stats command */
HCLGE_OPC_M7_STATS_BD = 0x7012, HCLGE_OPC_M7_STATS_BD = 0x7012,
HCLGE_OPC_M7_STATS_INFO = 0x7013, HCLGE_OPC_M7_STATS_INFO = 0x7013,
...@@ -429,8 +431,10 @@ struct hclge_rx_pkt_buf_cmd { ...@@ -429,8 +431,10 @@ struct hclge_rx_pkt_buf_cmd {
#define HCLGE_PF_MAC_NUM_MASK 0x3 #define HCLGE_PF_MAC_NUM_MASK 0x3
#define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B) #define HCLGE_PF_STATE_MAIN BIT(HCLGE_PF_STATE_MAIN_B)
#define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B) #define HCLGE_PF_STATE_DONE BIT(HCLGE_PF_STATE_DONE_B)
#define HCLGE_VF_RST_STATUS_CMD 4
struct hclge_func_status_cmd { struct hclge_func_status_cmd {
__le32 vf_rst_state[4]; __le32 vf_rst_state[HCLGE_VF_RST_STATUS_CMD];
u8 pf_state; u8 pf_state;
u8 mac_id; u8 mac_id;
u8 rsv1; u8 rsv1;
...@@ -486,10 +490,12 @@ struct hclge_pf_res_cmd { ...@@ -486,10 +490,12 @@ struct hclge_pf_res_cmd {
#define HCLGE_CFG_UMV_TBL_SPACE_S 16 #define HCLGE_CFG_UMV_TBL_SPACE_S 16
#define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16) #define HCLGE_CFG_UMV_TBL_SPACE_M GENMASK(31, 16)
#define HCLGE_CFG_CMD_CNT 4
struct hclge_cfg_param_cmd { struct hclge_cfg_param_cmd {
__le32 offset; __le32 offset;
__le32 rsv; __le32 rsv;
__le32 param[4]; __le32 param[HCLGE_CFG_CMD_CNT];
}; };
#define HCLGE_MAC_MODE 0x0 #define HCLGE_MAC_MODE 0x0
...@@ -758,20 +764,27 @@ struct hclge_vlan_filter_ctrl_cmd { ...@@ -758,20 +764,27 @@ struct hclge_vlan_filter_ctrl_cmd {
u8 rsv2[19]; u8 rsv2[19];
}; };
#define HCLGE_VLAN_ID_OFFSET_STEP 160
#define HCLGE_VLAN_BYTE_SIZE 8
#define HCLGE_VLAN_OFFSET_BITMAP \
(HCLGE_VLAN_ID_OFFSET_STEP / HCLGE_VLAN_BYTE_SIZE)
struct hclge_vlan_filter_pf_cfg_cmd { struct hclge_vlan_filter_pf_cfg_cmd {
u8 vlan_offset; u8 vlan_offset;
u8 vlan_cfg; u8 vlan_cfg;
u8 rsv[2]; u8 rsv[2];
u8 vlan_offset_bitmap[20]; u8 vlan_offset_bitmap[HCLGE_VLAN_OFFSET_BITMAP];
}; };
#define HCLGE_MAX_VF_BYTES 16
struct hclge_vlan_filter_vf_cfg_cmd { struct hclge_vlan_filter_vf_cfg_cmd {
__le16 vlan_id; __le16 vlan_id;
u8 resp_code; u8 resp_code;
u8 rsv; u8 rsv;
u8 vlan_cfg; u8 vlan_cfg;
u8 rsv1[3]; u8 rsv1[3];
u8 vf_bitmap[16]; u8 vf_bitmap[HCLGE_MAX_VF_BYTES];
}; };
#define HCLGE_SWITCH_ANTI_SPOOF_B 0U #define HCLGE_SWITCH_ANTI_SPOOF_B 0U
...@@ -806,6 +819,7 @@ enum hclge_mac_vlan_cfg_sel { ...@@ -806,6 +819,7 @@ enum hclge_mac_vlan_cfg_sel {
#define HCLGE_CFG_NIC_ROCE_SEL_B 4 #define HCLGE_CFG_NIC_ROCE_SEL_B 4
#define HCLGE_ACCEPT_TAG2_B 5 #define HCLGE_ACCEPT_TAG2_B 5
#define HCLGE_ACCEPT_UNTAG2_B 6 #define HCLGE_ACCEPT_UNTAG2_B 6
#define HCLGE_VF_NUM_PER_BYTE 8
struct hclge_vport_vtag_tx_cfg_cmd { struct hclge_vport_vtag_tx_cfg_cmd {
u8 vport_vlan_cfg; u8 vport_vlan_cfg;
...@@ -813,7 +827,7 @@ struct hclge_vport_vtag_tx_cfg_cmd { ...@@ -813,7 +827,7 @@ struct hclge_vport_vtag_tx_cfg_cmd {
u8 rsv1[2]; u8 rsv1[2];
__le16 def_vlan_tag1; __le16 def_vlan_tag1;
__le16 def_vlan_tag2; __le16 def_vlan_tag2;
u8 vf_bitmap[8]; u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
u8 rsv2[8]; u8 rsv2[8];
}; };
...@@ -825,7 +839,7 @@ struct hclge_vport_vtag_rx_cfg_cmd { ...@@ -825,7 +839,7 @@ struct hclge_vport_vtag_rx_cfg_cmd {
u8 vport_vlan_cfg; u8 vport_vlan_cfg;
u8 vf_offset; u8 vf_offset;
u8 rsv1[6]; u8 rsv1[6];
u8 vf_bitmap[8]; u8 vf_bitmap[HCLGE_VF_NUM_PER_BYTE];
u8 rsv2[8]; u8 rsv2[8];
}; };
...@@ -864,7 +878,7 @@ struct hclge_mac_ethertype_idx_rd_cmd { ...@@ -864,7 +878,7 @@ struct hclge_mac_ethertype_idx_rd_cmd {
u8 flags; u8 flags;
u8 resp_code; u8 resp_code;
__le16 vlan_tag; __le16 vlan_tag;
u8 mac_addr[6]; u8 mac_addr[ETH_ALEN];
__le16 index; __le16 index;
__le16 ethter_type; __le16 ethter_type;
__le16 egress_port; __le16 egress_port;
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_dcb.c
View file @ 2bd7c3e1
...@@ -87,7 +87,7 @@ static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc, ...@@ -87,7 +87,7 @@ static int hclge_dcb_common_validate(struct hclge_dev *hdev, u8 num_tc,
for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) { for (i = 0; i < HNAE3_MAX_USER_PRIO; i++) {
if (prio_tc[i] >= num_tc) { if (prio_tc[i] >= num_tc) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"prio_tc[%u] checking failed, %u >= num_tc(%u)\n", "prio_tc[%d] checking failed, %u >= num_tc(%u)\n",
i, prio_tc[i], num_tc); i, prio_tc[i], num_tc);
return -EINVAL; return -EINVAL;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_err.c
View file @ 2bd7c3e1
...@@ -1747,7 +1747,7 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev, ...@@ -1747,7 +1747,7 @@ static void hclge_handle_over_8bd_err(struct hclge_dev *hdev,
if (vf_id) { if (vf_id) {
if (vf_id >= hdev->num_alloc_vport) { if (vf_id >= hdev->num_alloc_vport) {
dev_err(dev, "invalid vf id(%d)\n", vf_id); dev_err(dev, "invalid vf id(%u)\n", vf_id);
return; return;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_main.h
View file @ 2bd7c3e1
...@@ -141,7 +141,6 @@ ...@@ -141,7 +141,6 @@
/* Factor used to calculate offset and bitmap of VF num */ /* Factor used to calculate offset and bitmap of VF num */
#define HCLGE_VF_NUM_PER_CMD 64 #define HCLGE_VF_NUM_PER_CMD 64
#define HCLGE_VF_NUM_PER_BYTE 8
enum HLCGE_PORT_TYPE { enum HLCGE_PORT_TYPE {
HOST_PORT, HOST_PORT,
...@@ -656,7 +655,6 @@ struct hclge_rst_stats { ...@@ -656,7 +655,6 @@ struct hclge_rst_stats {
u32 hw_reset_done_cnt; /* the number of HW reset has completed */ u32 hw_reset_done_cnt; /* the number of HW reset has completed */
u32 pf_rst_cnt; /* the number of PF reset */ u32 pf_rst_cnt; /* the number of PF reset */
u32 flr_rst_cnt; /* the number of FLR */ u32 flr_rst_cnt; /* the number of FLR */
u32 core_rst_cnt; /* the number of CORE reset */
u32 global_rst_cnt; /* the number of GLOBAL */ u32 global_rst_cnt; /* the number of GLOBAL */
u32 imp_rst_cnt; /* the number of IMP reset */ u32 imp_rst_cnt; /* the number of IMP reset */
u32 reset_cnt; /* the number of reset */ u32 reset_cnt; /* the number of reset */
...@@ -1005,4 +1003,5 @@ int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev, ...@@ -1005,4 +1003,5 @@ int hclge_query_bd_num_cmd_send(struct hclge_dev *hdev,
void hclge_report_hw_error(struct hclge_dev *hdev, void hclge_report_hw_error(struct hclge_dev *hdev,
enum hnae3_hw_error_type type); enum hnae3_hw_error_type type);
void hclge_inform_vf_promisc_info(struct hclge_vport *vport); void hclge_inform_vf_promisc_info(struct hclge_vport *vport);
void hclge_dbg_dump_rst_info(struct hclge_dev *hdev);
#endif #endif
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mbx.c
View file @ 2bd7c3e1
...@@ -26,7 +26,7 @@ static int hclge_gen_resp_to_vf(struct hclge_vport *vport, ...@@ -26,7 +26,7 @@ static int hclge_gen_resp_to_vf(struct hclge_vport *vport,
if (resp_data_len > HCLGE_MBX_MAX_RESP_DATA_SIZE) { if (resp_data_len > HCLGE_MBX_MAX_RESP_DATA_SIZE) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"PF fail to gen resp to VF len %d exceeds max len %d\n", "PF fail to gen resp to VF len %u exceeds max len %u\n",
resp_data_len, resp_data_len,
HCLGE_MBX_MAX_RESP_DATA_SIZE); HCLGE_MBX_MAX_RESP_DATA_SIZE);
/* If resp_data_len is too long, set the value to max length /* If resp_data_len is too long, set the value to max length
...@@ -285,7 +285,7 @@ static int hclge_set_vf_uc_mac_addr(struct hclge_vport *vport, ...@@ -285,7 +285,7 @@ static int hclge_set_vf_uc_mac_addr(struct hclge_vport *vport,
false, HCLGE_MAC_ADDR_UC); false, HCLGE_MAC_ADDR_UC);
} else { } else {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"failed to set unicast mac addr, unknown subcode %d\n", "failed to set unicast mac addr, unknown subcode %u\n",
mbx_req->msg[1]); mbx_req->msg[1]);
return -EIO; return -EIO;
} }
...@@ -319,7 +319,7 @@ static int hclge_set_vf_mc_mac_addr(struct hclge_vport *vport, ...@@ -319,7 +319,7 @@ static int hclge_set_vf_mc_mac_addr(struct hclge_vport *vport,
false, HCLGE_MAC_ADDR_MC); false, HCLGE_MAC_ADDR_MC);
} else { } else {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"failed to set mcast mac addr, unknown subcode %d\n", "failed to set mcast mac addr, unknown subcode %u\n",
mbx_req->msg[1]); mbx_req->msg[1]);
return -EIO; return -EIO;
} }
...@@ -555,7 +555,7 @@ static void hclge_reset_vf(struct hclge_vport *vport, ...@@ -555,7 +555,7 @@ static void hclge_reset_vf(struct hclge_vport *vport,
struct hclge_dev *hdev = vport->back; struct hclge_dev *hdev = vport->back;
int ret; int ret;
dev_warn(&hdev->pdev->dev, "PF received VF reset request from VF %d!", dev_warn(&hdev->pdev->dev, "PF received VF reset request from VF %u!",
vport->vport_id); vport->vport_id);
ret = hclge_func_reset_cmd(hdev, vport->vport_id); ret = hclge_func_reset_cmd(hdev, vport->vport_id);
...@@ -590,7 +590,8 @@ static int hclge_get_queue_id_in_pf(struct hclge_vport *vport, ...@@ -590,7 +590,8 @@ static int hclge_get_queue_id_in_pf(struct hclge_vport *vport,
qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id); qid_in_pf = hclge_covert_handle_qid_global(&vport->nic, queue_id);
memcpy(resp_data, &qid_in_pf, sizeof(qid_in_pf)); memcpy(resp_data, &qid_in_pf, sizeof(qid_in_pf));
return hclge_gen_resp_to_vf(vport, mbx_req, 0, resp_data, 2); return hclge_gen_resp_to_vf(vport, mbx_req, 0, resp_data,
sizeof(resp_data));
} }
static int hclge_get_rss_key(struct hclge_vport *vport, static int hclge_get_rss_key(struct hclge_vport *vport,
...@@ -680,7 +681,7 @@ void hclge_mbx_handler(struct hclge_dev *hdev) ...@@ -680,7 +681,7 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
flag = le16_to_cpu(crq->desc[crq->next_to_use].flag); flag = le16_to_cpu(crq->desc[crq->next_to_use].flag);
if (unlikely(!hnae3_get_bit(flag, HCLGE_CMDQ_RX_OUTVLD_B))) { if (unlikely(!hnae3_get_bit(flag, HCLGE_CMDQ_RX_OUTVLD_B))) {
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"dropped invalid mailbox message, code = %d\n", "dropped invalid mailbox message, code = %u\n",
req->msg[0]); req->msg[0]);
/* dropping/not processing this invalid message */ /* dropping/not processing this invalid message */
...@@ -827,7 +828,7 @@ void hclge_mbx_handler(struct hclge_dev *hdev) ...@@ -827,7 +828,7 @@ void hclge_mbx_handler(struct hclge_dev *hdev)
break; break;
default: default:
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"un-supported mailbox message, code = %d\n", "un-supported mailbox message, code = %u\n",
req->msg[0]); req->msg[0]);
break; break;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_mdio.c
View file @ 2bd7c3e1
...@@ -134,7 +134,7 @@ int hclge_mac_mdio_config(struct hclge_dev *hdev) ...@@ -134,7 +134,7 @@ int hclge_mac_mdio_config(struct hclge_dev *hdev)
"no phy device is connected to mdio bus\n"); "no phy device is connected to mdio bus\n");
return 0; return 0;
} else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) { } else if (hdev->hw.mac.phy_addr >= PHY_MAX_ADDR) {
dev_err(&hdev->pdev->dev, "phy_addr(%d) is too large.\n", dev_err(&hdev->pdev->dev, "phy_addr(%u) is too large.\n",
hdev->hw.mac.phy_addr); hdev->hw.mac.phy_addr);
return -EINVAL; return -EINVAL;
} }
......
drivers/net/ethernet/hisilicon/hns3/hns3pf/hclge_tm.c
View file @ 2bd7c3e1
...@@ -544,7 +544,7 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate) ...@@ -544,7 +544,7 @@ int hclge_tm_qs_shaper_cfg(struct hclge_vport *vport, int max_tx_rate)
ret = hclge_cmd_send(&hdev->hw, &desc, 1); ret = hclge_cmd_send(&hdev->hw, &desc, 1);
if (ret) { if (ret) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"vf%d, qs%u failed to set tx_rate:%d, ret=%d\n", "vf%u, qs%u failed to set tx_rate:%d, ret=%d\n",
vport->vport_id, shap_cfg_cmd->qs_id, vport->vport_id, shap_cfg_cmd->qs_id,
max_tx_rate, ret); max_tx_rate, ret);
return ret; return ret;
...@@ -575,7 +575,7 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport) ...@@ -575,7 +575,7 @@ static void hclge_tm_vport_tc_info_update(struct hclge_vport *vport)
/* Set to user value, no larger than max_rss_size. */ /* Set to user value, no larger than max_rss_size. */
if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size && if (kinfo->req_rss_size != kinfo->rss_size && kinfo->req_rss_size &&
kinfo->req_rss_size <= max_rss_size) { kinfo->req_rss_size <= max_rss_size) {
dev_info(&hdev->pdev->dev, "rss changes from %d to %d\n", dev_info(&hdev->pdev->dev, "rss changes from %u to %u\n",
kinfo->rss_size, kinfo->req_rss_size); kinfo->rss_size, kinfo->req_rss_size);
kinfo->rss_size = kinfo->req_rss_size; kinfo->rss_size = kinfo->req_rss_size;
} else if (kinfo->rss_size > max_rss_size || } else if (kinfo->rss_size > max_rss_size ||
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_cmd.c
View file @ 2bd7c3e1
...@@ -50,7 +50,7 @@ static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw) ...@@ -50,7 +50,7 @@ static int hclgevf_cmd_csq_clean(struct hclgevf_hw *hw)
rmb(); /* Make sure head is ready before touch any data */ rmb(); /* Make sure head is ready before touch any data */
if (!hclgevf_is_valid_csq_clean_head(csq, head)) { if (!hclgevf_is_valid_csq_clean_head(csq, head)) {
dev_warn(&hdev->pdev->dev, "wrong cmd head (%d, %d-%d)\n", head, dev_warn(&hdev->pdev->dev, "wrong cmd head (%u, %d-%d)\n", head,
csq->next_to_use, csq->next_to_clean); csq->next_to_use, csq->next_to_clean);
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"Disabling any further commands to IMP firmware\n"); "Disabling any further commands to IMP firmware\n");
...@@ -92,9 +92,9 @@ static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring) ...@@ -92,9 +92,9 @@ static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
u32 reg_val; u32 reg_val;
if (ring->flag == HCLGEVF_TYPE_CSQ) { if (ring->flag == HCLGEVF_TYPE_CSQ) {
reg_val = (u32)ring->desc_dma_addr; reg_val = lower_32_bits(ring->desc_dma_addr);
hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val); hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_L_REG, reg_val);
reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1); reg_val = upper_32_bits(ring->desc_dma_addr);
hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val); hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_BASEADDR_H_REG, reg_val);
reg_val = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG); reg_val = hclgevf_read_dev(hw, HCLGEVF_NIC_CSQ_DEPTH_REG);
...@@ -105,9 +105,9 @@ static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring) ...@@ -105,9 +105,9 @@ static void hclgevf_cmd_config_regs(struct hclgevf_cmq_ring *ring)
hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0); hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_HEAD_REG, 0);
hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0); hclgevf_write_dev(hw, HCLGEVF_NIC_CSQ_TAIL_REG, 0);
} else { } else {
reg_val = (u32)ring->desc_dma_addr; reg_val = lower_32_bits(ring->desc_dma_addr);
hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val); hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_L_REG, reg_val);
reg_val = (u32)((ring->desc_dma_addr >> 31) >> 1); reg_val = upper_32_bits(ring->desc_dma_addr);
hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val); hclgevf_write_dev(hw, HCLGEVF_NIC_CRQ_BASEADDR_H_REG, reg_val);
reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S); reg_val = (ring->desc_num >> HCLGEVF_NIC_CMQ_DESC_NUM_S);
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_main.c
View file @ 2bd7c3e1
...@@ -1549,12 +1549,39 @@ static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev) ...@@ -1549,12 +1549,39 @@ static int hclgevf_reset_prepare_wait(struct hclgevf_dev *hdev)
return ret; return ret;
} }
static void hclgevf_dump_rst_info(struct hclgevf_dev *hdev)
{
dev_info(&hdev->pdev->dev, "VF function reset count: %u\n",
hdev->rst_stats.vf_func_rst_cnt);
dev_info(&hdev->pdev->dev, "FLR reset count: %u\n",
hdev->rst_stats.flr_rst_cnt);
dev_info(&hdev->pdev->dev, "VF reset count: %u\n",
hdev->rst_stats.vf_rst_cnt);
dev_info(&hdev->pdev->dev, "reset done count: %u\n",
hdev->rst_stats.rst_done_cnt);
dev_info(&hdev->pdev->dev, "HW reset done count: %u\n",
hdev->rst_stats.hw_rst_done_cnt);
dev_info(&hdev->pdev->dev, "reset count: %u\n",
hdev->rst_stats.rst_cnt);
dev_info(&hdev->pdev->dev, "reset fail count: %u\n",
hdev->rst_stats.rst_fail_cnt);
dev_info(&hdev->pdev->dev, "vector0 interrupt enable status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_MISC_VECTOR_REG_BASE));
dev_info(&hdev->pdev->dev, "vector0 interrupt status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_VECTOR0_CMDQ_STAT_REG));
dev_info(&hdev->pdev->dev, "handshake status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_CMDQ_TX_DEPTH_REG));
dev_info(&hdev->pdev->dev, "function reset status: 0x%x\n",
hclgevf_read_dev(&hdev->hw, HCLGEVF_RST_ING));
dev_info(&hdev->pdev->dev, "hdev state: 0x%lx\n", hdev->state);
}
static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
{ {
/* recover handshake status with IMP when reset fail */ /* recover handshake status with IMP when reset fail */
hclgevf_reset_handshake(hdev, true); hclgevf_reset_handshake(hdev, true);
hdev->rst_stats.rst_fail_cnt++; hdev->rst_stats.rst_fail_cnt++;
dev_err(&hdev->pdev->dev, "failed to reset VF(%d)\n", dev_err(&hdev->pdev->dev, "failed to reset VF(%u)\n",
hdev->rst_stats.rst_fail_cnt); hdev->rst_stats.rst_fail_cnt);
if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT) if (hdev->rst_stats.rst_fail_cnt < HCLGEVF_RESET_MAX_FAIL_CNT)
...@@ -1563,6 +1590,8 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev) ...@@ -1563,6 +1590,8 @@ static void hclgevf_reset_err_handle(struct hclgevf_dev *hdev)
if (hclgevf_is_reset_pending(hdev)) { if (hclgevf_is_reset_pending(hdev)) {
set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state); set_bit(HCLGEVF_RESET_PENDING, &hdev->reset_state);
hclgevf_reset_task_schedule(hdev); hclgevf_reset_task_schedule(hdev);
} else {
hclgevf_dump_rst_info(hdev);
} }
} }
...@@ -1784,6 +1813,8 @@ static void hclgevf_service_timer(struct timer_list *t) ...@@ -1784,6 +1813,8 @@ static void hclgevf_service_timer(struct timer_list *t)
static void hclgevf_reset_service_task(struct work_struct *work) static void hclgevf_reset_service_task(struct work_struct *work)
{ {
#define HCLGEVF_MAX_RESET_ATTEMPTS_CNT 3
struct hclgevf_dev *hdev = struct hclgevf_dev *hdev =
container_of(work, struct hclgevf_dev, rst_service_task); container_of(work, struct hclgevf_dev, rst_service_task);
int ret; int ret;
...@@ -1836,7 +1867,7 @@ static void hclgevf_reset_service_task(struct work_struct *work) ...@@ -1836,7 +1867,7 @@ static void hclgevf_reset_service_task(struct work_struct *work)
* We cannot do much for 2. but to check first we can try reset * We cannot do much for 2. but to check first we can try reset
* our PCIe + stack and see if it alleviates the problem. * our PCIe + stack and see if it alleviates the problem.
*/ */
if (hdev->reset_attempts > 3) { if (hdev->reset_attempts > HCLGEVF_MAX_RESET_ATTEMPTS_CNT) {
/* prepare for full reset of stack + pcie interface */ /* prepare for full reset of stack + pcie interface */
set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending); set_bit(HNAE3_VF_FULL_RESET, &hdev->reset_pending);
...@@ -2139,7 +2170,6 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev) ...@@ -2139,7 +2170,6 @@ static int hclgevf_rss_init_hw(struct hclgevf_dev *hdev)
ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg); ret = hclgevf_set_rss_input_tuple(hdev, rss_cfg);
if (ret) if (ret)
return ret; return ret;
} }
/* Initialize RSS indirect table */ /* Initialize RSS indirect table */
...@@ -2308,7 +2338,7 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev) ...@@ -2308,7 +2338,7 @@ static int hclgevf_init_msi(struct hclgevf_dev *hdev)
} }
if (vectors < hdev->num_msi) if (vectors < hdev->num_msi)
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"requested %d MSI/MSI-X, but allocated %d MSI/MSI-X\n", "requested %u MSI/MSI-X, but allocated %d MSI/MSI-X\n",
hdev->num_msi, vectors); hdev->num_msi, vectors);
hdev->num_msi = vectors; hdev->num_msi = vectors;
...@@ -2384,12 +2414,12 @@ static void hclgevf_info_show(struct hclgevf_dev *hdev) ...@@ -2384,12 +2414,12 @@ static void hclgevf_info_show(struct hclgevf_dev *hdev)
dev_info(dev, "VF info begin:\n"); dev_info(dev, "VF info begin:\n");
dev_info(dev, "Task queue pairs numbers: %d\n", hdev->num_tqps); dev_info(dev, "Task queue pairs numbers: %u\n", hdev->num_tqps);
dev_info(dev, "Desc num per TX queue: %d\n", hdev->num_tx_desc); dev_info(dev, "Desc num per TX queue: %u\n", hdev->num_tx_desc);
dev_info(dev, "Desc num per RX queue: %d\n", hdev->num_rx_desc); dev_info(dev, "Desc num per RX queue: %u\n", hdev->num_rx_desc);
dev_info(dev, "Numbers of vports: %d\n", hdev->num_alloc_vport); dev_info(dev, "Numbers of vports: %u\n", hdev->num_alloc_vport);
dev_info(dev, "HW tc map: %d\n", hdev->hw_tc_map); dev_info(dev, "HW tc map: 0x%x\n", hdev->hw_tc_map);
dev_info(dev, "PF media type of this VF: %d\n", dev_info(dev, "PF media type of this VF: %u\n",
hdev->hw.mac.media_type); hdev->hw.mac.media_type);
dev_info(dev, "VF info end.\n"); dev_info(dev, "VF info end.\n");
......
drivers/net/ethernet/hisilicon/hns3/hns3vf/hclgevf_mbx.c
View file @ 2bd7c3e1
...@@ -33,7 +33,7 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1, ...@@ -33,7 +33,7 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1,
if (resp_len > HCLGE_MBX_MAX_RESP_DATA_SIZE) { if (resp_len > HCLGE_MBX_MAX_RESP_DATA_SIZE) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"VF mbx response len(=%d) exceeds maximum(=%d)\n", "VF mbx response len(=%u) exceeds maximum(=%u)\n",
resp_len, resp_len,
HCLGE_MBX_MAX_RESP_DATA_SIZE); HCLGE_MBX_MAX_RESP_DATA_SIZE);
return -EINVAL; return -EINVAL;
...@@ -49,7 +49,7 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1, ...@@ -49,7 +49,7 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1,
if (i >= HCLGEVF_MAX_TRY_TIMES) { if (i >= HCLGEVF_MAX_TRY_TIMES) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"VF could not get mbx(%d,%d) resp(=%d) from PF in %d tries\n", "VF could not get mbx(%u,%u) resp(=%d) from PF in %d tries\n",
code0, code1, hdev->mbx_resp.received_resp, i); code0, code1, hdev->mbx_resp.received_resp, i);
return -EIO; return -EIO;
} }
...@@ -68,10 +68,10 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1, ...@@ -68,10 +68,10 @@ static int hclgevf_get_mbx_resp(struct hclgevf_dev *hdev, u16 code0, u16 code1,
if (!(r_code0 == code0 && r_code1 == code1 && !mbx_resp->resp_status)) { if (!(r_code0 == code0 && r_code1 == code1 && !mbx_resp->resp_status)) {
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"VF could not match resp code(code0=%d,code1=%d), %d\n", "VF could not match resp code(code0=%u,code1=%u), %d\n",
code0, code1, mbx_resp->resp_status); code0, code1, mbx_resp->resp_status);
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"VF could not match resp r_code(r_code0=%d,r_code1=%d)\n", "VF could not match resp r_code(r_code0=%u,r_code1=%u)\n",
r_code0, r_code1); r_code0, r_code1);
return -EIO; return -EIO;
} }
...@@ -168,7 +168,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev) ...@@ -168,7 +168,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
flag = le16_to_cpu(crq->desc[crq->next_to_use].flag); flag = le16_to_cpu(crq->desc[crq->next_to_use].flag);
if (unlikely(!hnae3_get_bit(flag, HCLGEVF_CMDQ_RX_OUTVLD_B))) { if (unlikely(!hnae3_get_bit(flag, HCLGEVF_CMDQ_RX_OUTVLD_B))) {
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"dropped invalid mailbox message, code = %d\n", "dropped invalid mailbox message, code = %u\n",
req->msg[0]); req->msg[0]);
/* dropping/not processing this invalid message */ /* dropping/not processing this invalid message */
...@@ -187,7 +187,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev) ...@@ -187,7 +187,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
case HCLGE_MBX_PF_VF_RESP: case HCLGE_MBX_PF_VF_RESP:
if (resp->received_resp) if (resp->received_resp)
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"VF mbx resp flag not clear(%d)\n", "VF mbx resp flag not clear(%u)\n",
req->msg[1]); req->msg[1]);
resp->received_resp = true; resp->received_resp = true;
...@@ -219,7 +219,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev) ...@@ -219,7 +219,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
if (atomic_read(&hdev->arq.count) >= if (atomic_read(&hdev->arq.count) >=
HCLGE_MBX_MAX_ARQ_MSG_NUM) { HCLGE_MBX_MAX_ARQ_MSG_NUM) {
dev_warn(&hdev->pdev->dev, dev_warn(&hdev->pdev->dev,
"Async Q full, dropping msg(%d)\n", "Async Q full, dropping msg(%u)\n",
req->msg[1]); req->msg[1]);
break; break;
} }
...@@ -236,7 +236,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev) ...@@ -236,7 +236,7 @@ void hclgevf_mbx_handler(struct hclgevf_dev *hdev)
break; break;
default: default:
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"VF received unsupported(%d) mbx msg from PF\n", "VF received unsupported(%u) mbx msg from PF\n",
req->msg[0]); req->msg[0]);
break; break;
} }
...@@ -327,7 +327,7 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev) ...@@ -327,7 +327,7 @@ void hclgevf_mbx_async_handler(struct hclgevf_dev *hdev)
break; break;
default: default:
dev_err(&hdev->pdev->dev, dev_err(&hdev->pdev->dev,
"fetched unsupported(%d) message from arq\n", "fetched unsupported(%u) message from arq\n",
msg_q[0]); msg_q[0]);
break; break;
} }
......
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