Commit 2c4fa29e authored by Arend van Spriel's avatar Arend van Spriel Committed by Kalle Valo

brcmfmac: use different error value for invalid ram base address

The function brcmf_chip_tcm_rambase() returns 0 as invalid ram base
address. However, upcoming chips have ram base address starting at
zero so we have to find a more appropriate invalid value to return.
Reviewed-by: default avatarHante Meuleman <hante.meuleman@broadcom.com>
Reviewed-by: default avatarPieter-Paul Giesberts <pieter-paul.giesberts@broadcom.com>
Reviewed-by: default avatarFranky Lin <franky.lin@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend.vanspriel@broadcom.com>
Signed-off-by: default avatarKalle Valo <kvalo@codeaurora.org>
Link: https://lore.kernel.org/r/1627505434-9544-2-git-send-email-arend.vanspriel@broadcom.com
parent c2dac3d2
...@@ -139,6 +139,8 @@ struct sbconfig { ...@@ -139,6 +139,8 @@ struct sbconfig {
u32 sbidhigh; /* identification */ u32 sbidhigh; /* identification */
}; };
#define INVALID_RAMBASE ((u32)(~0))
/* bankidx and bankinfo reg defines corerev >= 8 */ /* bankidx and bankinfo reg defines corerev >= 8 */
#define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000 #define SOCRAM_BANKINFO_RETNTRAM_MASK 0x00010000
#define SOCRAM_BANKINFO_SZMASK 0x0000007f #define SOCRAM_BANKINFO_SZMASK 0x0000007f
...@@ -731,7 +733,7 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci) ...@@ -731,7 +733,7 @@ static u32 brcmf_chip_tcm_rambase(struct brcmf_chip_priv *ci)
brcmf_err("unknown chip: %s\n", ci->pub.name); brcmf_err("unknown chip: %s\n", ci->pub.name);
break; break;
} }
return 0; return INVALID_RAMBASE;
} }
int brcmf_chip_get_raminfo(struct brcmf_chip *pub) int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
...@@ -746,7 +748,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub) ...@@ -746,7 +748,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
mem_core = container_of(mem, struct brcmf_core_priv, pub); mem_core = container_of(mem, struct brcmf_core_priv, pub);
ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core); ci->pub.ramsize = brcmf_chip_tcm_ramsize(mem_core);
ci->pub.rambase = brcmf_chip_tcm_rambase(ci); ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
if (!ci->pub.rambase) { if (ci->pub.rambase == INVALID_RAMBASE) {
brcmf_err("RAM base not provided with ARM CR4 core\n"); brcmf_err("RAM base not provided with ARM CR4 core\n");
return -EINVAL; return -EINVAL;
} }
...@@ -757,7 +759,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub) ...@@ -757,7 +759,7 @@ int brcmf_chip_get_raminfo(struct brcmf_chip *pub)
pub); pub);
ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core); ci->pub.ramsize = brcmf_chip_sysmem_ramsize(mem_core);
ci->pub.rambase = brcmf_chip_tcm_rambase(ci); ci->pub.rambase = brcmf_chip_tcm_rambase(ci);
if (!ci->pub.rambase) { if (ci->pub.rambase == INVALID_RAMBASE) {
brcmf_err("RAM base not provided with ARM CA7 core\n"); brcmf_err("RAM base not provided with ARM CA7 core\n");
return -EINVAL; return -EINVAL;
} }
......
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