Commit 2d0f07f8 authored by Pandith N's avatar Pandith N Committed by Vinod Koul

dmaengine: dw-axi-dmac: set coherent mask

Add support for setting dma coherent mask, dma mask is set to 64 bit
Signed-off-by: default avatarPandith N <pandith.n@intel.com>
Reviewed-by: default avatarAndy Shevchenko <andriy.shevchenko@linux.intel.com>

Link: https://lore.kernel.org/r/20211001140812.24977-4-pandith.n@intel.comSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 93a7d32e
...@@ -212,12 +212,16 @@ static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan) ...@@ -212,12 +212,16 @@ static inline bool axi_chan_is_hw_enable(struct axi_dma_chan *chan)
static void axi_dma_hw_init(struct axi_dma_chip *chip) static void axi_dma_hw_init(struct axi_dma_chip *chip)
{ {
int ret;
u32 i; u32 i;
for (i = 0; i < chip->dw->hdata->nr_channels; i++) { for (i = 0; i < chip->dw->hdata->nr_channels; i++) {
axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL); axi_chan_irq_disable(&chip->dw->chan[i], DWAXIDMAC_IRQ_ALL);
axi_chan_disable(&chip->dw->chan[i]); axi_chan_disable(&chip->dw->chan[i]);
} }
ret = dma_set_mask_and_coherent(chip->dev, DMA_BIT_MASK(64));
if (ret)
dev_warn(chip->dev, "Unable to set coherent mask\n");
} }
static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src, static u32 axi_chan_get_xfer_width(struct axi_dma_chan *chan, dma_addr_t src,
......
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