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Commit 2d3779dd authored by Teresa Remmet's avatar Teresa Remmet Committed by Shawn Guo
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arm64: dts: imx8mp-phycore-som: Order properties alphabetically 

Rearrange properties in order:
- compatible
- reg
- other generic properties
- device specific properties
- vendor specific properties
- status

And use alphabetical order inside a group.
Signed-off-by: default avatarTeresa Remmet <t.remmet@phytec.de>
Signed-off-by: default avatarShawn Guo <shawnguo@kernel.org>
parent 312ab094
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Showing with 60 additions and 60 deletions
arch/arm64/boot/dts/freescale/imx8mp-phycore-som.dtsi
View file @ 2d3779dd
...@@ -42,8 +42,8 @@ &A53_3 { ...@@ -42,8 +42,8 @@ &A53_3 {
&fec { &fec {
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_fec>; pinctrl-0 = <&pinctrl_fec>;
phy-mode = "rgmii-id";
phy-handle = <&ethphy1>; phy-handle = <&ethphy1>;
phy-mode = "rgmii-id";
fsl,magic-packet; fsl,magic-packet;
status = "okay"; status = "okay";
...@@ -54,12 +54,12 @@ mdio { ...@@ -54,12 +54,12 @@ mdio {
ethphy1: ethernet-phy@0 { ethphy1: ethernet-phy@0 {
compatible = "ethernet-phy-ieee802.3-c22"; compatible = "ethernet-phy-ieee802.3-c22";
reg = <0>; reg = <0>;
ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>; enet-phy-lane-no-swap;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>; ti,clk-output-sel = <DP83867_CLK_O_SEL_OFF>;
ti,fifo-depth = <DP83867_PHYCR_FIFO_DEPTH_4_B_NIB>;
ti,min-output-impedance; ti,min-output-impedance;
enet-phy-lane-no-swap; ti,rx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
ti,tx-internal-delay = <DP83867_RGMIIDCTL_2_00_NS>;
}; };
}; };
}; };
...@@ -73,8 +73,8 @@ som_flash: flash@0 { ...@@ -73,8 +73,8 @@ som_flash: flash@0 {
compatible = "jedec,spi-nor"; compatible = "jedec,spi-nor";
reg = <0>; reg = <0>;
spi-max-frequency = <80000000>; spi-max-frequency = <80000000>;
spi-tx-bus-width = <1>;
spi-rx-bus-width = <4>; spi-rx-bus-width = <4>;
spi-tx-bus-width = <1>;
}; };
}; };
...@@ -83,89 +83,89 @@ &i2c1 { ...@@ -83,89 +83,89 @@ &i2c1 {
pinctrl-names = "default", "gpio"; pinctrl-names = "default", "gpio";
pinctrl-0 = <&pinctrl_i2c1>; pinctrl-0 = <&pinctrl_i2c1>;
pinctrl-1 = <&pinctrl_i2c1_gpio>; pinctrl-1 = <&pinctrl_i2c1_gpio>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>; scl-gpios = <&gpio5 14 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
sda-gpios = <&gpio5 15 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
status = "okay"; status = "okay";
pmic: pmic@25 { pmic: pmic@25 {
reg = <0x25>;
compatible = "nxp,pca9450c"; compatible = "nxp,pca9450c";
reg = <0x25>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
interrupt-parent = <&gpio4>;
pinctrl-names = "default"; pinctrl-names = "default";
pinctrl-0 = <&pinctrl_pmic>; pinctrl-0 = <&pinctrl_pmic>;
interrupt-parent = <&gpio4>;
interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
regulators { regulators {
buck1: BUCK1 { buck1: BUCK1 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>; regulator-ramp-delay = <3125>;
}; };
buck2: BUCK2 { buck2: BUCK2 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <2187500>;
regulator-boot-on;
regulator-always-on;
regulator-ramp-delay = <3125>;
nxp,dvs-run-voltage = <950000>; nxp,dvs-run-voltage = <950000>;
nxp,dvs-standby-voltage = <850000>; nxp,dvs-standby-voltage = <850000>;
regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <2187500>;
regulator-min-microvolt = <600000>;
regulator-ramp-delay = <3125>;
}; };
buck4: BUCK4 { buck4: BUCK4 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
}; };
buck5: BUCK5 { buck5: BUCK5 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
}; };
buck6: BUCK6 { buck6: BUCK6 {
regulator-min-microvolt = <600000>;
regulator-max-microvolt = <3400000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3400000>;
regulator-min-microvolt = <600000>;
}; };
ldo1: LDO1 { ldo1: LDO1 {
regulator-min-microvolt = <1600000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1600000>;
}; };
ldo2: LDO2 { ldo2: LDO2 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <1150000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <1150000>;
regulator-min-microvolt = <800000>;
}; };
ldo3: LDO3 { ldo3: LDO3 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
}; };
ldo4: LDO4 { ldo4: LDO4 {
regulator-min-microvolt = <800000>;
regulator-max-microvolt = <3300000>; regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <800000>;
}; };
ldo5: LDO5 { ldo5: LDO5 {
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
regulator-boot-on;
regulator-always-on; regulator-always-on;
regulator-boot-on;
regulator-max-microvolt = <3300000>;
regulator-min-microvolt = <1800000>;
}; };
}; };
}; };
...@@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91 ...@@ -213,13 +213,13 @@ MX8MP_IOMUXC_SAI1_RXD5__ENET1_RGMII_RD1 0x91
MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91 MX8MP_IOMUXC_SAI1_RXD6__ENET1_RGMII_RD2 0x91
MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91 MX8MP_IOMUXC_SAI1_RXD7__ENET1_RGMII_RD3 0x91
MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91 MX8MP_IOMUXC_SAI1_TXC__ENET1_RGMII_RXC 0x91
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12 MX8MP_IOMUXC_SAI1_TXD0__ENET1_RGMII_TD0 0x12
MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12 MX8MP_IOMUXC_SAI1_TXD1__ENET1_RGMII_TD1 0x12
MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14 MX8MP_IOMUXC_SAI1_TXD2__ENET1_RGMII_TD2 0x14
MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14 MX8MP_IOMUXC_SAI1_TXD3__ENET1_RGMII_TD3 0x14
MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14 MX8MP_IOMUXC_SAI1_TXD4__ENET1_RGMII_TX_CTL 0x14
MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14 MX8MP_IOMUXC_SAI1_TXD5__ENET1_RGMII_TXC 0x14
MX8MP_IOMUXC_SAI1_TXFS__ENET1_RGMII_RX_CTL 0x91
>; >;
}; };
...@@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82 ...@@ -236,8 +236,8 @@ MX8MP_IOMUXC_NAND_DATA03__FLEXSPI_A_DATA03 0x82
pinctrl_i2c1: i2c1grp { pinctrl_i2c1: i2c1grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3 MX8MP_IOMUXC_I2C1_SDA__I2C1_SDA 0x400001c3
MX8MP_IOMUXC_I2C1_SCL__I2C1_SCL 0x400001c3
>; >;
}; };
...@@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141 ...@@ -256,49 +256,49 @@ MX8MP_IOMUXC_SAI1_TXD6__GPIO4_IO18 0x141
pinctrl_usdhc3: usdhc3grp { pinctrl_usdhc3: usdhc3grp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d0
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d0
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d0
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d0
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d0
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d0 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x190
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d0 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d0
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d0
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x190
>; >;
}; };
pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp { pinctrl_usdhc3_100mhz: usdhc3-100mhzgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d4
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d4
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d4
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d4
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d4
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d4 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x194
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d4 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d4
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d4
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x194
>; >;
}; };
pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp { pinctrl_usdhc3_200mhz: usdhc3-200mhzgrp {
fsl,pins = < fsl,pins = <
MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196 MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6 MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2 MX8MP_IOMUXC_NAND_DATA04__USDHC3_DATA0 0x1d2
MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2 MX8MP_IOMUXC_NAND_DATA05__USDHC3_DATA1 0x1d2
MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2 MX8MP_IOMUXC_NAND_DATA06__USDHC3_DATA2 0x1d2
MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2 MX8MP_IOMUXC_NAND_DATA07__USDHC3_DATA3 0x1d2
MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2 MX8MP_IOMUXC_NAND_RE_B__USDHC3_DATA4 0x1d2
MX8MP_IOMUXC_NAND_CE2_B__USDHC3_DATA5 0x1d2 MX8MP_IOMUXC_NAND_WE_B__USDHC3_CLK 0x196
MX8MP_IOMUXC_NAND_CE3_B__USDHC3_DATA6 0x1d2 MX8MP_IOMUXC_NAND_WP_B__USDHC3_CMD 0x1d6
MX8MP_IOMUXC_NAND_CLE__USDHC3_DATA7 0x1d2
MX8MP_IOMUXC_NAND_CE1_B__USDHC3_STROBE 0x196
>; >;
}; };
......
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