Commit 2d889db7 authored by Wei Yongjun's avatar Wei Yongjun Committed by Hyun Kwon

drm: xlnx: Fix typo in parameter description

Fix typo in parameter description.

Fixes: d76271d2 ("drm: xlnx: DRM/KMS driver for Xilinx ZynqMP DisplayPort Subsystem")
Reported-by: default avatarHulk Robot <hulkci@huawei.com>
Signed-off-by: default avatarWei Yongjun <weiyongjun1@huawei.com>
Reviewed-by: default avatarLaurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: default avatarHyun Kwon <hyun.kwon@xilinx.com>
Signed-off-by: default avatarHyun Kwon <hyun.kwon@xilinx.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20200725063429.172139-1-weiyongjun1@huawei.com
parent be13d94b
...@@ -44,7 +44,7 @@ MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)"); ...@@ -44,7 +44,7 @@ MODULE_PARM_DESC(aux_timeout_ms, "DP aux timeout value in msec (default: 50)");
*/ */
static uint zynqmp_dp_power_on_delay_ms = 4; static uint zynqmp_dp_power_on_delay_ms = 4;
module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444); module_param_named(power_on_delay_ms, zynqmp_dp_power_on_delay_ms, uint, 0444);
MODULE_PARM_DESC(aux_timeout_ms, "DP power on delay in msec (default: 4)"); MODULE_PARM_DESC(power_on_delay_ms, "DP power on delay in msec (default: 4)");
/* Link configuration registers */ /* Link configuration registers */
#define ZYNQMP_DP_LINK_BW_SET 0x0 #define ZYNQMP_DP_LINK_BW_SET 0x0
......
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