Commit 2e397c30 authored by Arend van Spriel's avatar Arend van Spriel Committed by John W. Linville

brcm80211: smac: move fields from struct si_pub to struct si_info

The structure si_pub contained couple of fields that were only
used internally in aiutils.c. These have been moved to the
si_info structure.
Reviewed-by: default avatarPieter-Paul Giesberts <pieterpg@broadcom.com>
Reviewed-by: default avatarAlwin Beukers <alwin@broadcom.com>
Reviewed-by: default avatarRoland Vossen <rvossen@broadcom.com>
Signed-off-by: default avatarArend van Spriel <arend@broadcom.com>
Signed-off-by: default avatarFranky Lin <frankyl@broadcom.com>
Signed-off-by: default avatarJohn W. Linville <linville@tuxdriver.com>
parent c9eb65a4
...@@ -928,7 +928,7 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) ...@@ -928,7 +928,7 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
/* get chipcommon chipstatus */ /* get chipcommon chipstatus */
if (sii->pub.ccrev >= 11) if (sii->pub.ccrev >= 11)
sii->pub.chipst = R_REG(&cc->chipstatus); sii->chipst = R_REG(&cc->chipstatus);
/* get chipcommon capabilites */ /* get chipcommon capabilites */
sii->pub.cccaps = R_REG(&cc->capabilities); sii->pub.cccaps = R_REG(&cc->capabilities);
...@@ -942,7 +942,7 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) ...@@ -942,7 +942,7 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
/* figure out bus/orignal core idx */ /* figure out bus/orignal core idx */
sii->pub.buscoretype = NODEV_CORE_ID; sii->pub.buscoretype = NODEV_CORE_ID;
sii->pub.buscorerev = NOREV; sii->pub.buscorerev = NOREV;
sii->pub.buscoreidx = BADIDX; sii->buscoreidx = BADIDX;
pci = pcie = false; pci = pcie = false;
pcirev = pcierev = NOREV; pcirev = pcierev = NOREV;
...@@ -980,11 +980,11 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx) ...@@ -980,11 +980,11 @@ ai_buscore_setup(struct si_info *sii, u32 savewin, uint *origidx)
if (pci) { if (pci) {
sii->pub.buscoretype = PCI_CORE_ID; sii->pub.buscoretype = PCI_CORE_ID;
sii->pub.buscorerev = pcirev; sii->pub.buscorerev = pcirev;
sii->pub.buscoreidx = pciidx; sii->buscoreidx = pciidx;
} else if (pcie) { } else if (pcie) {
sii->pub.buscoretype = PCIE_CORE_ID; sii->pub.buscoretype = PCIE_CORE_ID;
sii->pub.buscorerev = pcierev; sii->pub.buscorerev = pcierev;
sii->pub.buscoreidx = pcieidx; sii->buscoreidx = pcieidx;
} }
/* fixup necessary chip/core configurations */ /* fixup necessary chip/core configurations */
...@@ -1034,7 +1034,7 @@ static struct si_info *ai_doattach(struct si_info *sii, ...@@ -1034,7 +1034,7 @@ static struct si_info *ai_doattach(struct si_info *sii,
savewin = 0; savewin = 0;
sih->buscoreidx = BADIDX; sii->buscoreidx = BADIDX;
sii->curmap = regs; sii->curmap = regs;
sii->pbus = pbus; sii->pbus = pbus;
...@@ -1372,7 +1372,7 @@ uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask, ...@@ -1372,7 +1372,7 @@ uint ai_corereg(struct si_pub *sih, uint coreidx, uint regoff, uint mask,
fast = true; fast = true;
r = (u32 __iomem *)((__iomem char *)sii->curmap + r = (u32 __iomem *)((__iomem char *)sii->curmap +
PCI_16KB0_CCREGS_OFFSET + regoff); PCI_16KB0_CCREGS_OFFSET + regoff);
} else if (sii->pub.buscoreidx == coreidx) { } else if (sii->buscoreidx == coreidx) {
/* /*
* pci registers are at either in the last 2KB of * pci registers are at either in the last 2KB of
* an 8KB window or, in pcie and pci rev 13 at 8KB * an 8KB window or, in pcie and pci rev 13 at 8KB
...@@ -1904,7 +1904,7 @@ void ai_pci_setup(struct si_pub *sih, uint coremask) ...@@ -1904,7 +1904,7 @@ void ai_pci_setup(struct si_pub *sih, uint coremask)
siflag = ai_flag(sih); siflag = ai_flag(sih);
/* switch over to pci core */ /* switch over to pci core */
regs = ai_setcoreidx(sih, sii->pub.buscoreidx); regs = ai_setcoreidx(sih, sii->buscoreidx);
} }
/* /*
...@@ -2035,8 +2035,9 @@ bool ai_deviceremoved(struct si_pub *sih) ...@@ -2035,8 +2035,9 @@ bool ai_deviceremoved(struct si_pub *sih)
bool ai_is_sprom_available(struct si_pub *sih) bool ai_is_sprom_available(struct si_pub *sih)
{ {
struct si_info *sii = (struct si_info *)sih;
if (sih->ccrev >= 31) { if (sih->ccrev >= 31) {
struct si_info *sii;
uint origidx; uint origidx;
struct chipcregs __iomem *cc; struct chipcregs __iomem *cc;
u32 sromctrl; u32 sromctrl;
...@@ -2044,7 +2045,6 @@ bool ai_is_sprom_available(struct si_pub *sih) ...@@ -2044,7 +2045,6 @@ bool ai_is_sprom_available(struct si_pub *sih)
if ((sih->cccaps & CC_CAP_SROM) == 0) if ((sih->cccaps & CC_CAP_SROM) == 0)
return false; return false;
sii = (struct si_info *)sih;
origidx = sii->curidx; origidx = sii->curidx;
cc = ai_setcoreidx(sih, SI_CC_IDX); cc = ai_setcoreidx(sih, SI_CC_IDX);
sromctrl = R_REG(&cc->sromcontrol); sromctrl = R_REG(&cc->sromcontrol);
...@@ -2054,7 +2054,7 @@ bool ai_is_sprom_available(struct si_pub *sih) ...@@ -2054,7 +2054,7 @@ bool ai_is_sprom_available(struct si_pub *sih)
switch (sih->chip) { switch (sih->chip) {
case BCM4313_CHIP_ID: case BCM4313_CHIP_ID:
return (sih->chipst & CST4313_SPROM_PRESENT) != 0; return (sii->chipst & CST4313_SPROM_PRESENT) != 0;
default: default:
return true; return true;
} }
...@@ -2062,9 +2062,11 @@ bool ai_is_sprom_available(struct si_pub *sih) ...@@ -2062,9 +2062,11 @@ bool ai_is_sprom_available(struct si_pub *sih)
bool ai_is_otp_disabled(struct si_pub *sih) bool ai_is_otp_disabled(struct si_pub *sih)
{ {
struct si_info *sii = (struct si_info *)sih;
switch (sih->chip) { switch (sih->chip) {
case BCM4313_CHIP_ID: case BCM4313_CHIP_ID:
return (sih->chipst & CST4313_OTP_PRESENT) == 0; return (sii->chipst & CST4313_OTP_PRESENT) == 0;
/* These chips always have their OTP on */ /* These chips always have their OTP on */
case BCM43224_CHIP_ID: case BCM43224_CHIP_ID:
case BCM43225_CHIP_ID: case BCM43225_CHIP_ID:
......
...@@ -146,7 +146,6 @@ ...@@ -146,7 +146,6 @@
struct si_pub { struct si_pub {
uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */ uint buscoretype; /* PCI_CORE_ID, PCIE_CORE_ID, PCMCIA_CORE_ID */
uint buscorerev; /* buscore rev */ uint buscorerev; /* buscore rev */
uint buscoreidx; /* buscore index */
int ccrev; /* chip common core rev */ int ccrev; /* chip common core rev */
u32 cccaps; /* chip common capabilities */ u32 cccaps; /* chip common capabilities */
int pmurev; /* pmu core rev */ int pmurev; /* pmu core rev */
...@@ -156,7 +155,6 @@ struct si_pub { ...@@ -156,7 +155,6 @@ struct si_pub {
uint chip; /* chip number */ uint chip; /* chip number */
uint chiprev; /* chip revision */ uint chiprev; /* chip revision */
uint chippkg; /* chip package option */ uint chippkg; /* chip package option */
u32 chipst; /* chip status */
}; };
struct pci_dev; struct pci_dev;
...@@ -188,7 +186,9 @@ struct si_info { ...@@ -188,7 +186,9 @@ struct si_info {
void __iomem *curmap; /* current regs va */ void __iomem *curmap; /* current regs va */
void __iomem *regs[SI_MAXCORES]; /* other regs va */ void __iomem *regs[SI_MAXCORES]; /* other regs va */
u32 chipst; /* chip status */
uint curidx; /* current core index */ uint curidx; /* current core index */
uint buscoreidx; /* buscore index */
uint numcores; /* # discovered cores */ uint numcores; /* # discovered cores */
uint coreid[SI_MAXCORES]; /* id of each core */ uint coreid[SI_MAXCORES]; /* id of each core */
u32 coresba[SI_MAXCORES]; /* backplane address of each core */ u32 coresba[SI_MAXCORES]; /* backplane address of each core */
......
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