Commit 2f52e874 authored by Konrad Dybcio's avatar Konrad Dybcio Committed by Bjorn Andersson

arm64: dts: qcom: sm6115: Add mdss_ prefix to mdss nodes

Add a mdss_ prefix to mdss nodes to keep them all near each other
when referencing them by label in device DTs.
Signed-off-by: default avatarKonrad Dybcio <konrad.dybcio@linaro.org>
Signed-off-by: default avatarBjorn Andersson <andersson@kernel.org>
Link: https://lore.kernel.org/r/20230119101644.10711-1-konrad.dybcio@linaro.org
parent faf69431
...@@ -1105,7 +1105,7 @@ ports { ...@@ -1105,7 +1105,7 @@ ports {
port@0 { port@0 {
reg = <0>; reg = <0>;
dpu_intf1_out: endpoint { dpu_intf1_out: endpoint {
remote-endpoint = <&dsi0_in>; remote-endpoint = <&mdss_dsi0_in>;
}; };
}; };
}; };
...@@ -1140,7 +1140,7 @@ opp-384000000 { ...@@ -1140,7 +1140,7 @@ opp-384000000 {
}; };
}; };
dsi0: dsi@5e94000 { mdss_dsi0: dsi@5e94000 {
compatible = "qcom,dsi-ctrl-6g-qcm2290"; compatible = "qcom,dsi-ctrl-6g-qcm2290";
reg = <0x05e94000 0x400>; reg = <0x05e94000 0x400>;
reg-names = "dsi_ctrl"; reg-names = "dsi_ctrl";
...@@ -1163,11 +1163,11 @@ dsi0: dsi@5e94000 { ...@@ -1163,11 +1163,11 @@ dsi0: dsi@5e94000 {
assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>, assigned-clocks = <&dispcc DISP_CC_MDSS_BYTE0_CLK_SRC>,
<&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>; <&dispcc DISP_CC_MDSS_PCLK0_CLK_SRC>;
assigned-clock-parents = <&dsi0_phy 0>, <&dsi0_phy 1>; assigned-clock-parents = <&mdss_dsi0_phy 0>, <&mdss_dsi0_phy 1>;
operating-points-v2 = <&dsi_opp_table>; operating-points-v2 = <&dsi_opp_table>;
power-domains = <&rpmpd SM6115_VDDCX>; power-domains = <&rpmpd SM6115_VDDCX>;
phys = <&dsi0_phy>; phys = <&mdss_dsi0_phy>;
#address-cells = <1>; #address-cells = <1>;
#size-cells = <0>; #size-cells = <0>;
...@@ -1180,14 +1180,14 @@ ports { ...@@ -1180,14 +1180,14 @@ ports {
port@0 { port@0 {
reg = <0>; reg = <0>;
dsi0_in: endpoint { mdss_dsi0_in: endpoint {
remote-endpoint = <&dpu_intf1_out>; remote-endpoint = <&dpu_intf1_out>;
}; };
}; };
port@1 { port@1 {
reg = <1>; reg = <1>;
dsi0_out: endpoint { mdss_dsi0_out: endpoint {
}; };
}; };
}; };
...@@ -1212,7 +1212,7 @@ opp-187500000 { ...@@ -1212,7 +1212,7 @@ opp-187500000 {
}; };
}; };
dsi0_phy: phy@5e94400 { mdss_dsi0_phy: phy@5e94400 {
compatible = "qcom,dsi-phy-14nm-2290"; compatible = "qcom,dsi-phy-14nm-2290";
reg = <0x05e94400 0x100>, reg = <0x05e94400 0x100>,
<0x05e94500 0x300>, <0x05e94500 0x300>,
...@@ -1237,8 +1237,8 @@ dispcc: clock-controller@5f00000 { ...@@ -1237,8 +1237,8 @@ dispcc: clock-controller@5f00000 {
reg = <0x05f00000 0x20000>; reg = <0x05f00000 0x20000>;
clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>,
<&sleep_clk>, <&sleep_clk>,
<&dsi0_phy 0>, <&mdss_dsi0_phy 0>,
<&dsi0_phy 1>, <&mdss_dsi0_phy 1>,
<&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>; <&gcc GCC_DISP_GPLL0_DIV_CLK_SRC>;
#clock-cells = <1>; #clock-cells = <1>;
#reset-cells = <1>; #reset-cells = <1>;
......
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