Commit 2f666bcf authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6

* 'drm-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6:
  drm/radeon/kms: pll tweaks for r7xx
  drm/nouveau: fix allocation of notifier object
  drm/nouveau: fix notifier memory corruption bug
  drm/nouveau: fix pinning of notifier block
  drm/nouveau: populate ttm_alloced with false, when it's not
  drm/nouveau: fix nv30 pcie boards
  drm/nouveau: split ramin_lock into two locks, one hardirq safe
  drm/radeon/kms: adjust evergreen display watermark setup
  drm/radeon/kms: add connectors even if i2c fails
  drm/radeon/kms: fix bad shift in atom iio table parser
parents 6cf54437 5785e53f
...@@ -83,7 +83,7 @@ nouveau_dma_init(struct nouveau_channel *chan) ...@@ -83,7 +83,7 @@ nouveau_dma_init(struct nouveau_channel *chan)
return ret; return ret;
/* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */ /* NV_MEMORY_TO_MEMORY_FORMAT requires a notifier object */
ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfd0, 0x1000, ret = nouveau_notifier_alloc(chan, NvNotify0, 32, 0xfe0, 0x1000,
&chan->m2mf_ntfy); &chan->m2mf_ntfy);
if (ret) if (ret)
return ret; return ret;
......
...@@ -682,6 +682,9 @@ struct drm_nouveau_private { ...@@ -682,6 +682,9 @@ struct drm_nouveau_private {
/* For PFIFO and PGRAPH. */ /* For PFIFO and PGRAPH. */
spinlock_t context_switch_lock; spinlock_t context_switch_lock;
/* VM/PRAMIN flush, legacy PRAMIN aperture */
spinlock_t vm_lock;
/* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */ /* RAMIN configuration, RAMFC, RAMHT and RAMRO offsets */
struct nouveau_ramht *ramht; struct nouveau_ramht *ramht;
struct nouveau_gpuobj *ramfc; struct nouveau_gpuobj *ramfc;
......
...@@ -181,13 +181,13 @@ nouveau_fbcon_sync(struct fb_info *info) ...@@ -181,13 +181,13 @@ nouveau_fbcon_sync(struct fb_info *info)
OUT_RING (chan, 0); OUT_RING (chan, 0);
} }
nouveau_bo_wr32(chan->notifier_bo, chan->m2mf_ntfy + 3, 0xffffffff); nouveau_bo_wr32(chan->notifier_bo, chan->m2mf_ntfy/4 + 3, 0xffffffff);
FIRE_RING(chan); FIRE_RING(chan);
mutex_unlock(&chan->mutex); mutex_unlock(&chan->mutex);
ret = -EBUSY; ret = -EBUSY;
for (i = 0; i < 100000; i++) { for (i = 0; i < 100000; i++) {
if (!nouveau_bo_rd32(chan->notifier_bo, chan->m2mf_ntfy + 3)) { if (!nouveau_bo_rd32(chan->notifier_bo, chan->m2mf_ntfy/4 + 3)) {
ret = 0; ret = 0;
break; break;
} }
......
...@@ -398,7 +398,7 @@ nouveau_mem_vram_init(struct drm_device *dev) ...@@ -398,7 +398,7 @@ nouveau_mem_vram_init(struct drm_device *dev)
dma_bits = 40; dma_bits = 40;
} else } else
if (drm_pci_device_is_pcie(dev) && if (drm_pci_device_is_pcie(dev) &&
dev_priv->chipset != 0x40 && dev_priv->chipset > 0x40 &&
dev_priv->chipset != 0x45) { dev_priv->chipset != 0x45) {
if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39))) if (pci_dma_supported(dev->pdev, DMA_BIT_MASK(39)))
dma_bits = 39; dma_bits = 39;
......
...@@ -35,19 +35,22 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan) ...@@ -35,19 +35,22 @@ nouveau_notifier_init_channel(struct nouveau_channel *chan)
{ {
struct drm_device *dev = chan->dev; struct drm_device *dev = chan->dev;
struct nouveau_bo *ntfy = NULL; struct nouveau_bo *ntfy = NULL;
uint32_t flags; uint32_t flags, ttmpl;
int ret; int ret;
if (nouveau_vram_notify) if (nouveau_vram_notify) {
flags = NOUVEAU_GEM_DOMAIN_VRAM; flags = NOUVEAU_GEM_DOMAIN_VRAM;
else ttmpl = TTM_PL_FLAG_VRAM;
} else {
flags = NOUVEAU_GEM_DOMAIN_GART; flags = NOUVEAU_GEM_DOMAIN_GART;
ttmpl = TTM_PL_FLAG_TT;
}
ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, flags, 0, 0, &ntfy); ret = nouveau_gem_new(dev, NULL, PAGE_SIZE, 0, flags, 0, 0, &ntfy);
if (ret) if (ret)
return ret; return ret;
ret = nouveau_bo_pin(ntfy, flags); ret = nouveau_bo_pin(ntfy, ttmpl);
if (ret) if (ret)
goto out_err; goto out_err;
......
...@@ -1039,19 +1039,20 @@ nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset) ...@@ -1039,19 +1039,20 @@ nv_ro32(struct nouveau_gpuobj *gpuobj, u32 offset)
{ {
struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
struct drm_device *dev = gpuobj->dev; struct drm_device *dev = gpuobj->dev;
unsigned long flags;
if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
u64 ptr = gpuobj->vinst + offset; u64 ptr = gpuobj->vinst + offset;
u32 base = ptr >> 16; u32 base = ptr >> 16;
u32 val; u32 val;
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
if (dev_priv->ramin_base != base) { if (dev_priv->ramin_base != base) {
dev_priv->ramin_base = base; dev_priv->ramin_base = base;
nv_wr32(dev, 0x001700, dev_priv->ramin_base); nv_wr32(dev, 0x001700, dev_priv->ramin_base);
} }
val = nv_rd32(dev, 0x700000 + (ptr & 0xffff)); val = nv_rd32(dev, 0x700000 + (ptr & 0xffff));
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
return val; return val;
} }
...@@ -1063,18 +1064,19 @@ nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val) ...@@ -1063,18 +1064,19 @@ nv_wo32(struct nouveau_gpuobj *gpuobj, u32 offset, u32 val)
{ {
struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private; struct drm_nouveau_private *dev_priv = gpuobj->dev->dev_private;
struct drm_device *dev = gpuobj->dev; struct drm_device *dev = gpuobj->dev;
unsigned long flags;
if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) { if (gpuobj->pinst == ~0 || !dev_priv->ramin_available) {
u64 ptr = gpuobj->vinst + offset; u64 ptr = gpuobj->vinst + offset;
u32 base = ptr >> 16; u32 base = ptr >> 16;
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
if (dev_priv->ramin_base != base) { if (dev_priv->ramin_base != base) {
dev_priv->ramin_base = base; dev_priv->ramin_base = base;
nv_wr32(dev, 0x001700, dev_priv->ramin_base); nv_wr32(dev, 0x001700, dev_priv->ramin_base);
} }
nv_wr32(dev, 0x700000 + (ptr & 0xffff), val); nv_wr32(dev, 0x700000 + (ptr & 0xffff), val);
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
return; return;
} }
......
...@@ -55,6 +55,7 @@ nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages, ...@@ -55,6 +55,7 @@ nouveau_sgdma_populate(struct ttm_backend *be, unsigned long num_pages,
be->func->clear(be); be->func->clear(be);
return -EFAULT; return -EFAULT;
} }
nvbe->ttm_alloced[nvbe->nr_pages] = false;
} }
nvbe->nr_pages++; nvbe->nr_pages++;
...@@ -427,7 +428,7 @@ nouveau_sgdma_init(struct drm_device *dev) ...@@ -427,7 +428,7 @@ nouveau_sgdma_init(struct drm_device *dev)
u32 aper_size, align; u32 aper_size, align;
int ret; int ret;
if (dev_priv->card_type >= NV_50 || drm_pci_device_is_pcie(dev)) if (dev_priv->card_type >= NV_40 && drm_pci_device_is_pcie(dev))
aper_size = 512 * 1024 * 1024; aper_size = 512 * 1024 * 1024;
else else
aper_size = 64 * 1024 * 1024; aper_size = 64 * 1024 * 1024;
...@@ -457,7 +458,7 @@ nouveau_sgdma_init(struct drm_device *dev) ...@@ -457,7 +458,7 @@ nouveau_sgdma_init(struct drm_device *dev)
dev_priv->gart_info.func = &nv50_sgdma_backend; dev_priv->gart_info.func = &nv50_sgdma_backend;
} else } else
if (drm_pci_device_is_pcie(dev) && if (drm_pci_device_is_pcie(dev) &&
dev_priv->chipset != 0x40 && dev_priv->chipset != 0x45) { dev_priv->chipset > 0x40 && dev_priv->chipset != 0x45) {
if (nv44_graph_class(dev)) { if (nv44_graph_class(dev)) {
dev_priv->gart_info.func = &nv44_sgdma_backend; dev_priv->gart_info.func = &nv44_sgdma_backend;
align = 512 * 1024; align = 512 * 1024;
......
...@@ -608,6 +608,7 @@ nouveau_card_init(struct drm_device *dev) ...@@ -608,6 +608,7 @@ nouveau_card_init(struct drm_device *dev)
spin_lock_init(&dev_priv->channels.lock); spin_lock_init(&dev_priv->channels.lock);
spin_lock_init(&dev_priv->tile.lock); spin_lock_init(&dev_priv->tile.lock);
spin_lock_init(&dev_priv->context_switch_lock); spin_lock_init(&dev_priv->context_switch_lock);
spin_lock_init(&dev_priv->vm_lock);
/* Make the CRTCs and I2C buses accessible */ /* Make the CRTCs and I2C buses accessible */
ret = engine->display.early_init(dev); ret = engine->display.early_init(dev);
......
...@@ -404,23 +404,25 @@ void ...@@ -404,23 +404,25 @@ void
nv50_instmem_flush(struct drm_device *dev) nv50_instmem_flush(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
unsigned long flags;
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
nv_wr32(dev, 0x00330c, 0x00000001); nv_wr32(dev, 0x00330c, 0x00000001);
if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000)) if (!nv_wait(dev, 0x00330c, 0x00000002, 0x00000000))
NV_ERROR(dev, "PRAMIN flush timeout\n"); NV_ERROR(dev, "PRAMIN flush timeout\n");
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
} }
void void
nv84_instmem_flush(struct drm_device *dev) nv84_instmem_flush(struct drm_device *dev)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
unsigned long flags;
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
nv_wr32(dev, 0x070000, 0x00000001); nv_wr32(dev, 0x070000, 0x00000001);
if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000)) if (!nv_wait(dev, 0x070000, 0x00000002, 0x00000000))
NV_ERROR(dev, "PRAMIN flush timeout\n"); NV_ERROR(dev, "PRAMIN flush timeout\n");
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
} }
...@@ -174,10 +174,11 @@ void ...@@ -174,10 +174,11 @@ void
nv50_vm_flush_engine(struct drm_device *dev, int engine) nv50_vm_flush_engine(struct drm_device *dev, int engine)
{ {
struct drm_nouveau_private *dev_priv = dev->dev_private; struct drm_nouveau_private *dev_priv = dev->dev_private;
unsigned long flags;
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
nv_wr32(dev, 0x100c80, (engine << 16) | 1); nv_wr32(dev, 0x100c80, (engine << 16) | 1);
if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000)) if (!nv_wait(dev, 0x100c80, 0x00000001, 0x00000000))
NV_ERROR(dev, "vm flush timeout: engine %d\n", engine); NV_ERROR(dev, "vm flush timeout: engine %d\n", engine);
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
} }
...@@ -104,11 +104,12 @@ nvc0_vm_flush(struct nouveau_vm *vm) ...@@ -104,11 +104,12 @@ nvc0_vm_flush(struct nouveau_vm *vm)
struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem; struct nouveau_instmem_engine *pinstmem = &dev_priv->engine.instmem;
struct drm_device *dev = vm->dev; struct drm_device *dev = vm->dev;
struct nouveau_vm_pgd *vpgd; struct nouveau_vm_pgd *vpgd;
unsigned long flags;
u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5; u32 engine = (dev_priv->chan_vm == vm) ? 1 : 5;
pinstmem->flush(vm->dev); pinstmem->flush(vm->dev);
spin_lock(&dev_priv->ramin_lock); spin_lock_irqsave(&dev_priv->vm_lock, flags);
list_for_each_entry(vpgd, &vm->pgd_list, head) { list_for_each_entry(vpgd, &vm->pgd_list, head) {
/* looks like maybe a "free flush slots" counter, the /* looks like maybe a "free flush slots" counter, the
* faster you write to 0x100cbc to more it decreases * faster you write to 0x100cbc to more it decreases
...@@ -125,5 +126,5 @@ nvc0_vm_flush(struct nouveau_vm *vm) ...@@ -125,5 +126,5 @@ nvc0_vm_flush(struct nouveau_vm *vm)
nv_rd32(dev, 0x100c80), engine); nv_rd32(dev, 0x100c80), engine);
} }
} }
spin_unlock(&dev_priv->ramin_lock); spin_unlock_irqrestore(&dev_priv->vm_lock, flags);
} }
...@@ -135,7 +135,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, ...@@ -135,7 +135,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
case ATOM_IIO_MOVE_INDEX: case ATOM_IIO_MOVE_INDEX:
temp &= temp &=
~((0xFFFFFFFF >> (32 - CU8(base + 1))) << ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
CU8(base + 2)); CU8(base + 3));
temp |= temp |=
((index >> CU8(base + 2)) & ((index >> CU8(base + 2)) &
(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
...@@ -145,7 +145,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, ...@@ -145,7 +145,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
case ATOM_IIO_MOVE_DATA: case ATOM_IIO_MOVE_DATA:
temp &= temp &=
~((0xFFFFFFFF >> (32 - CU8(base + 1))) << ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
CU8(base + 2)); CU8(base + 3));
temp |= temp |=
((data >> CU8(base + 2)) & ((data >> CU8(base + 2)) &
(0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base + (0xFFFFFFFF >> (32 - CU8(base + 1)))) << CU8(base +
...@@ -155,7 +155,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base, ...@@ -155,7 +155,7 @@ static uint32_t atom_iio_execute(struct atom_context *ctx, int base,
case ATOM_IIO_MOVE_ATTR: case ATOM_IIO_MOVE_ATTR:
temp &= temp &=
~((0xFFFFFFFF >> (32 - CU8(base + 1))) << ~((0xFFFFFFFF >> (32 - CU8(base + 1))) <<
CU8(base + 2)); CU8(base + 3));
temp |= temp |=
((ctx-> ((ctx->
io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 - io_attr >> CU8(base + 2)) & (0xFFFFFFFF >> (32 -
......
...@@ -532,10 +532,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, ...@@ -532,10 +532,7 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
else else
pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV; pll->flags |= RADEON_PLL_PREFER_LOW_REF_DIV;
if ((rdev->family == CHIP_R600) || if (rdev->family < CHIP_RV770)
(rdev->family == CHIP_RV610) ||
(rdev->family == CHIP_RV630) ||
(rdev->family == CHIP_RV670))
pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP; pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
} else { } else {
pll->flags |= RADEON_PLL_LEGACY; pll->flags |= RADEON_PLL_LEGACY;
...@@ -565,7 +562,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc, ...@@ -565,7 +562,6 @@ static u32 atombios_adjust_pll(struct drm_crtc *crtc,
if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) { if (radeon_encoder->devices & (ATOM_DEVICE_LCD_SUPPORT)) {
if (ss_enabled) { if (ss_enabled) {
if (ss->refdiv) { if (ss->refdiv) {
pll->flags |= RADEON_PLL_PREFER_MINM_OVER_MAXP;
pll->flags |= RADEON_PLL_USE_REF_DIV; pll->flags |= RADEON_PLL_USE_REF_DIV;
pll->reference_div = ss->refdiv; pll->reference_div = ss->refdiv;
if (ASIC_IS_AVIVO(rdev)) if (ASIC_IS_AVIVO(rdev))
......
...@@ -353,7 +353,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, ...@@ -353,7 +353,7 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
struct drm_display_mode *mode, struct drm_display_mode *mode,
struct drm_display_mode *other_mode) struct drm_display_mode *other_mode)
{ {
u32 tmp = 0; u32 tmp;
/* /*
* Line Buffer Setup * Line Buffer Setup
* There are 3 line buffers, each one shared by 2 display controllers. * There are 3 line buffers, each one shared by 2 display controllers.
...@@ -363,64 +363,63 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev, ...@@ -363,64 +363,63 @@ static u32 evergreen_line_buffer_adjust(struct radeon_device *rdev,
* first display controller * first display controller
* 0 - first half of lb (3840 * 2) * 0 - first half of lb (3840 * 2)
* 1 - first 3/4 of lb (5760 * 2) * 1 - first 3/4 of lb (5760 * 2)
* 2 - whole lb (7680 * 2) * 2 - whole lb (7680 * 2), other crtc must be disabled
* 3 - first 1/4 of lb (1920 * 2) * 3 - first 1/4 of lb (1920 * 2)
* second display controller * second display controller
* 4 - second half of lb (3840 * 2) * 4 - second half of lb (3840 * 2)
* 5 - second 3/4 of lb (5760 * 2) * 5 - second 3/4 of lb (5760 * 2)
* 6 - whole lb (7680 * 2) * 6 - whole lb (7680 * 2), other crtc must be disabled
* 7 - last 1/4 of lb (1920 * 2) * 7 - last 1/4 of lb (1920 * 2)
*/ */
if (mode && other_mode) { /* this can get tricky if we have two large displays on a paired group
if (mode->hdisplay > other_mode->hdisplay) { * of crtcs. Ideally for multiple large displays we'd assign them to
if (mode->hdisplay > 2560) * non-linked crtcs for maximum line buffer allocation.
tmp = 1; /* 3/4 */ */
else if (radeon_crtc->base.enabled && mode) {
tmp = 0; /* 1/2 */ if (other_mode)
} else if (other_mode->hdisplay > mode->hdisplay) {
if (other_mode->hdisplay > 2560)
tmp = 3; /* 1/4 */
else
tmp = 0; /* 1/2 */
} else
tmp = 0; /* 1/2 */ tmp = 0; /* 1/2 */
} else if (mode) else
tmp = 2; /* whole */ tmp = 2; /* whole */
else if (other_mode) } else
tmp = 3; /* 1/4 */ tmp = 0;
/* second controller of the pair uses second half of the lb */ /* second controller of the pair uses second half of the lb */
if (radeon_crtc->crtc_id % 2) if (radeon_crtc->crtc_id % 2)
tmp += 4; tmp += 4;
WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp); WREG32(DC_LB_MEMORY_SPLIT + radeon_crtc->crtc_offset, tmp);
switch (tmp) { if (radeon_crtc->base.enabled && mode) {
case 0: switch (tmp) {
case 4: case 0:
default: case 4:
if (ASIC_IS_DCE5(rdev)) default:
return 4096 * 2; if (ASIC_IS_DCE5(rdev))
else return 4096 * 2;
return 3840 * 2; else
case 1: return 3840 * 2;
case 5: case 1:
if (ASIC_IS_DCE5(rdev)) case 5:
return 6144 * 2; if (ASIC_IS_DCE5(rdev))
else return 6144 * 2;
return 5760 * 2; else
case 2: return 5760 * 2;
case 6: case 2:
if (ASIC_IS_DCE5(rdev)) case 6:
return 8192 * 2; if (ASIC_IS_DCE5(rdev))
else return 8192 * 2;
return 7680 * 2; else
case 3: return 7680 * 2;
case 7: case 3:
if (ASIC_IS_DCE5(rdev)) case 7:
return 2048 * 2; if (ASIC_IS_DCE5(rdev))
else return 2048 * 2;
return 1920 * 2; else
return 1920 * 2;
}
} }
/* controller not enabled, so no lb used */
return 0;
} }
static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev) static u32 evergreen_get_number_of_dram_channels(struct radeon_device *rdev)
......
...@@ -1199,7 +1199,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1199,7 +1199,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (router->ddc_valid || router->cd_valid) { if (router->ddc_valid || router->cd_valid) {
radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info); radeon_connector->router_bus = radeon_i2c_lookup(rdev, &router->i2c_info);
if (!radeon_connector->router_bus) if (!radeon_connector->router_bus)
goto failed; DRM_ERROR("Failed to assign router i2c bus! Check dmesg for i2c errors.\n");
} }
switch (connector_type) { switch (connector_type) {
case DRM_MODE_CONNECTOR_VGA: case DRM_MODE_CONNECTOR_VGA:
...@@ -1208,7 +1208,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1208,7 +1208,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
radeon_connector->dac_load_detect = true; radeon_connector->dac_load_detect = true;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1226,7 +1226,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1226,7 +1226,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
radeon_connector->dac_load_detect = true; radeon_connector->dac_load_detect = true;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1249,7 +1249,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1249,7 +1249,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
subpixel_order = SubPixelHorizontalRGB; subpixel_order = SubPixelHorizontalRGB;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1290,7 +1290,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1290,7 +1290,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("HDMI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
rdev->mode_info.coherent_mode_property, rdev->mode_info.coherent_mode_property,
...@@ -1329,10 +1329,10 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1329,10 +1329,10 @@ radeon_add_atom_connector(struct drm_device *dev,
else else
radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch"); radeon_dig_connector->dp_i2c_bus = radeon_i2c_create_dp(dev, i2c_bus, "DP-auxch");
if (!radeon_dig_connector->dp_i2c_bus) if (!radeon_dig_connector->dp_i2c_bus)
goto failed; DRM_ERROR("DP: Failed to assign dp ddc bus! Check dmesg for i2c errors.\n");
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("DP: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
subpixel_order = SubPixelHorizontalRGB; subpixel_order = SubPixelHorizontalRGB;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1381,7 +1381,7 @@ radeon_add_atom_connector(struct drm_device *dev, ...@@ -1381,7 +1381,7 @@ radeon_add_atom_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
dev->mode_config.scaling_mode_property, dev->mode_config.scaling_mode_property,
...@@ -1457,7 +1457,7 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1457,7 +1457,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("VGA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
radeon_connector->dac_load_detect = true; radeon_connector->dac_load_detect = true;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1475,7 +1475,7 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1475,7 +1475,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("DVIA: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
radeon_connector->dac_load_detect = true; radeon_connector->dac_load_detect = true;
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
...@@ -1493,7 +1493,7 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1493,7 +1493,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("DVI: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
if (connector_type == DRM_MODE_CONNECTOR_DVII) { if (connector_type == DRM_MODE_CONNECTOR_DVII) {
radeon_connector->dac_load_detect = true; radeon_connector->dac_load_detect = true;
...@@ -1538,7 +1538,7 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1538,7 +1538,7 @@ radeon_add_legacy_connector(struct drm_device *dev,
if (i2c_bus->valid) { if (i2c_bus->valid) {
radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus); radeon_connector->ddc_bus = radeon_i2c_lookup(rdev, i2c_bus);
if (!radeon_connector->ddc_bus) if (!radeon_connector->ddc_bus)
goto failed; DRM_ERROR("LVDS: Failed to assign ddc bus! Check dmesg for i2c errors.\n");
} }
drm_connector_attach_property(&radeon_connector->base, drm_connector_attach_property(&radeon_connector->base,
dev->mode_config.scaling_mode_property, dev->mode_config.scaling_mode_property,
...@@ -1567,9 +1567,4 @@ radeon_add_legacy_connector(struct drm_device *dev, ...@@ -1567,9 +1567,4 @@ radeon_add_legacy_connector(struct drm_device *dev,
radeon_legacy_backlight_init(radeon_encoder, connector); radeon_legacy_backlight_init(radeon_encoder, connector);
} }
} }
return;
failed:
drm_connector_cleanup(connector);
kfree(connector);
} }
...@@ -1096,6 +1096,9 @@ void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector) ...@@ -1096,6 +1096,9 @@ void radeon_router_select_ddc_port(struct radeon_connector *radeon_connector)
if (!radeon_connector->router.ddc_valid) if (!radeon_connector->router.ddc_valid)
return; return;
if (!radeon_connector->router_bus)
return;
radeon_i2c_get_byte(radeon_connector->router_bus, radeon_i2c_get_byte(radeon_connector->router_bus,
radeon_connector->router.i2c_addr, radeon_connector->router.i2c_addr,
0x3, &val); 0x3, &val);
...@@ -1121,6 +1124,9 @@ void radeon_router_select_cd_port(struct radeon_connector *radeon_connector) ...@@ -1121,6 +1124,9 @@ void radeon_router_select_cd_port(struct radeon_connector *radeon_connector)
if (!radeon_connector->router.cd_valid) if (!radeon_connector->router.cd_valid)
return; return;
if (!radeon_connector->router_bus)
return;
radeon_i2c_get_byte(radeon_connector->router_bus, radeon_i2c_get_byte(radeon_connector->router_bus,
radeon_connector->router.i2c_addr, radeon_connector->router.i2c_addr,
0x3, &val); 0x3, &val);
......
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