Commit 30ec75cc authored by Anton Blanchard's avatar Anton Blanchard

[PATCH] Re: Make sym2 driver use pci_enable_device

> The sym2 driver should use the generic pci_enable_device() and
> pci_set_master() functions.

Sorry, wrong patch. We need to read COMMAND after doing
pci_enable_device/pci_set_master. We should also check the return
valie of pci_enable_device.

Anton

===== drivers/scsi/sym53c8xx_2/sym_glue.c 1.16 vs edited =====
parent a00ad804
...@@ -2558,34 +2558,16 @@ sym53c8xx_pci_init(Scsi_Host_Template *tpnt, pcidev_t pdev, sym_device *device) ...@@ -2558,34 +2558,16 @@ sym53c8xx_pci_init(Scsi_Host_Template *tpnt, pcidev_t pdev, sym_device *device)
bcopy(chip, &device->chip, sizeof(device->chip)); bcopy(chip, &device->chip, sizeof(device->chip));
device->chip.revision_id = revision; device->chip.revision_id = revision;
if (pci_enable_device(pdev))
return -1;
pci_set_master(pdev);
/* /*
* Read additionnal info from the configuration space. * Read additionnal info from the configuration space.
*/ */
pci_read_config_word(pdev, PCI_COMMAND, &command);
pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size); pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cache_line_size);
/*
* Enable missing capabilities in the PCI COMMAND register.
*/
#ifdef SYM_CONF_IOMAPPED
#define PCI_COMMAND_BITS_TO_ENABLE (PCI_COMMAND_IO | \
PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY)
#else
#define PCI_COMMAND_BITS_TO_ENABLE \
(PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | PCI_COMMAND_PARITY)
#endif
if ((command & PCI_COMMAND_BITS_TO_ENABLE)
!= PCI_COMMAND_BITS_TO_ENABLE) {
printf_info("%s: setting%s%s%s%s...\n", sym_name(device),
(command & PCI_COMMAND_IO) ? "" : " PCI_COMMAND_IO",
(command & PCI_COMMAND_MEMORY) ? "" : " PCI_COMMAND_MEMORY",
(command & PCI_COMMAND_MASTER) ? "" : " PCI_COMMAND_MASTER",
(command & PCI_COMMAND_PARITY) ? "" : " PCI_COMMAND_PARITY");
command |= PCI_COMMAND_BITS_TO_ENABLE;
pci_write_config_word(pdev, PCI_COMMAND, command);
}
#undef PCI_COMMAND_BITS_TO_ENABLE
/* /*
* If cache line size is not configured, suggest * If cache line size is not configured, suggest
* a value for well known CPUs. * a value for well known CPUs.
...@@ -2625,6 +2607,7 @@ sym53c8xx_pci_init(Scsi_Host_Template *tpnt, pcidev_t pdev, sym_device *device) ...@@ -2625,6 +2607,7 @@ sym53c8xx_pci_init(Scsi_Host_Template *tpnt, pcidev_t pdev, sym_device *device)
sym_name(device), cache_line_size); sym_name(device), cache_line_size);
} }
pci_read_config_word(pdev, PCI_COMMAND, &command);
if ((pci_fix_up & 2) && cache_line_size && if ((pci_fix_up & 2) && cache_line_size &&
(chip->features & FE_WRIE) && !(command & PCI_COMMAND_INVALIDATE)) { (chip->features & FE_WRIE) && !(command & PCI_COMMAND_INVALIDATE)) {
printf_info("%s: setting PCI_COMMAND_INVALIDATE.\n", printf_info("%s: setting PCI_COMMAND_INVALIDATE.\n",
......
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