Commit 30ee3738 authored by Rander Wang's avatar Rander Wang Committed by Mark Brown

ASoC: SOF: Intel: Add support for tgl-h

SOF will support tgl-h and tgl-lp in different FW binaries due to
hardware difference, so create another dev_desc entry with FW name
of sof-tgl-h.ri and dsp_desc named tglh_chip_info for tgl-h.

Fixes: c8d2e2bf ("ASoC: SOF: Intel: add PCI IDs for ICL-H and TGL-H")
Signed-off-by: default avatarRander Wang <rander.wang@intel.com>
Reviewed-by: default avatarPierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Signed-off-by: default avatarKai Vehmanen <kai.vehmanen@linux.intel.com>
Link: https://lore.kernel.org/r/20200917103609.2559916-1-kai.vehmanen@linux.intel.comSigned-off-by: default avatarMark Brown <broonie@kernel.org>
parent df44bc16
...@@ -737,6 +737,7 @@ extern const struct sof_intel_dsp_desc cnl_chip_info; ...@@ -737,6 +737,7 @@ extern const struct sof_intel_dsp_desc cnl_chip_info;
extern const struct sof_intel_dsp_desc skl_chip_info; extern const struct sof_intel_dsp_desc skl_chip_info;
extern const struct sof_intel_dsp_desc icl_chip_info; extern const struct sof_intel_dsp_desc icl_chip_info;
extern const struct sof_intel_dsp_desc tgl_chip_info; extern const struct sof_intel_dsp_desc tgl_chip_info;
extern const struct sof_intel_dsp_desc tglh_chip_info;
extern const struct sof_intel_dsp_desc ehl_chip_info; extern const struct sof_intel_dsp_desc ehl_chip_info;
extern const struct sof_intel_dsp_desc jsl_chip_info; extern const struct sof_intel_dsp_desc jsl_chip_info;
......
...@@ -135,3 +135,19 @@ const struct sof_intel_dsp_desc tgl_chip_info = { ...@@ -135,3 +135,19 @@ const struct sof_intel_dsp_desc tgl_chip_info = {
.ssp_base_offset = CNL_SSP_BASE_OFFSET, .ssp_base_offset = CNL_SSP_BASE_OFFSET,
}; };
EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON); EXPORT_SYMBOL_NS(tgl_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
const struct sof_intel_dsp_desc tglh_chip_info = {
/* Tigerlake-H */
.cores_num = 2,
.init_core_mask = 1,
.host_managed_cores_mask = BIT(0),
.ipc_req = CNL_DSP_REG_HIPCIDR,
.ipc_req_mask = CNL_DSP_REG_HIPCIDR_BUSY,
.ipc_ack = CNL_DSP_REG_HIPCIDA,
.ipc_ack_mask = CNL_DSP_REG_HIPCIDA_DONE,
.ipc_ctl = CNL_DSP_REG_HIPCCTL,
.rom_init_timeout = 300,
.ssp_count = ICL_SSP_COUNT,
.ssp_base_offset = CNL_SSP_BASE_OFFSET,
};
EXPORT_SYMBOL_NS(tglh_chip_info, SND_SOC_SOF_INTEL_HDA_COMMON);
...@@ -223,6 +223,22 @@ static const struct sof_dev_desc tgl_desc = { ...@@ -223,6 +223,22 @@ static const struct sof_dev_desc tgl_desc = {
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg", .nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
.ops = &sof_tgl_ops, .ops = &sof_tgl_ops,
}; };
static const struct sof_dev_desc tglh_desc = {
.machines = snd_soc_acpi_intel_tgl_machines,
.alt_machines = snd_soc_acpi_intel_tgl_sdw_machines,
.resindex_lpe_base = 0,
.resindex_pcicfg_base = -1,
.resindex_imr_base = -1,
.irqindex_host_ipc = -1,
.resindex_dma_base = -1,
.chip_info = &tglh_chip_info,
.default_fw_path = "intel/sof",
.default_tplg_path = "intel/sof-tplg",
.default_fw_filename = "sof-tgl-h.ri",
.nocodec_tplg_filename = "sof-tgl-nocodec.tplg",
.ops = &sof_tgl_ops,
};
#endif #endif
#if IS_ENABLED(CONFIG_SND_SOC_SOF_ELKHARTLAKE) #if IS_ENABLED(CONFIG_SND_SOC_SOF_ELKHARTLAKE)
...@@ -457,7 +473,7 @@ static const struct pci_device_id sof_pci_ids[] = { ...@@ -457,7 +473,7 @@ static const struct pci_device_id sof_pci_ids[] = {
{ PCI_DEVICE(0x8086, 0xa0c8), /* TGL-LP */ { PCI_DEVICE(0x8086, 0xa0c8), /* TGL-LP */
.driver_data = (unsigned long)&tgl_desc}, .driver_data = (unsigned long)&tgl_desc},
{ PCI_DEVICE(0x8086, 0x43c8), /* TGL-H */ { PCI_DEVICE(0x8086, 0x43c8), /* TGL-H */
.driver_data = (unsigned long)&tgl_desc}, .driver_data = (unsigned long)&tglh_desc},
#endif #endif
#if IS_ENABLED(CONFIG_SND_SOC_SOF_ELKHARTLAKE) #if IS_ENABLED(CONFIG_SND_SOC_SOF_ELKHARTLAKE)
......
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