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Commit 31070e7f authored by David S. Miller's avatar David S. Miller
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Merge branch 'nfp-bpf-ABIv2-and-multi-port' 

Jakub Kicinski says:

====================
nfp: bpf ABIv2 and multi port

This series migrates our eBPF offload from old PoC firmware to
a redesigned, faster and more feature rich FW.  Marking support
is dropped for now.  We have to teach the JIT about encoding
local memory accesses (one of NFP memory types).  There is also
code to populate the ECC of instructions (PoC had ECC protection
on instruction store disabled).  There is also a minor ld_field
fix and all 64 bit shifts can now be encoded.
====================
Signed-off-by: default avatarDavid S. Miller <davem@davemloft.net>
parents 1c3dc891 2de1be1d
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Showing with 640 additions and 378 deletions
drivers/net/ethernet/netronome/nfp/Makefile
View file @ 31070e7f
......@@ -14,6 +14,7 @@ nfp-objs := \
nfpcore/nfp_resource.o \
nfpcore/nfp_rtsym.o \
nfpcore/nfp_target.o \
nfp_asm.o \
nfp_app.o \
nfp_app_nic.o \
nfp_devlink.o \
......
drivers/net/ethernet/netronome/nfp/bpf/jit.c
View file @ 31070e7f
......@@ -110,150 +110,7 @@ nfp_prog_offset_to_index(struct nfp_prog *nfp_prog, unsigned int offset)
return offset - nfp_prog->start_off;
}
/* --- SW reg --- */
struct nfp_insn_ur_regs {
enum alu_dst_ab dst_ab;
u16 dst;
u16 areg, breg;
bool swap;
bool wr_both;
};
struct nfp_insn_re_regs {
enum alu_dst_ab dst_ab;
u8 dst;
u8 areg, breg;
bool swap;
bool wr_both;
bool i8;
};
static u16 nfp_swreg_to_unreg(u32 swreg, bool is_dst)
{
u16 val = FIELD_GET(NN_REG_VAL, swreg);
switch (FIELD_GET(NN_REG_TYPE, swreg)) {
case NN_REG_GPR_A:
case NN_REG_GPR_B:
case NN_REG_GPR_BOTH:
return val;
case NN_REG_NNR:
return UR_REG_NN | val;
case NN_REG_XFER:
return UR_REG_XFR | val;
case NN_REG_IMM:
if (val & ~0xff) {
pr_err("immediate too large\n");
return 0;
}
return UR_REG_IMM_encode(val);
case NN_REG_NONE:
return is_dst ? UR_REG_NO_DST : REG_NONE;
default:
pr_err("unrecognized reg encoding %08x\n", swreg);
return 0;
}
}
static int
swreg_to_unrestricted(u32 dst, u32 lreg, u32 rreg, struct nfp_insn_ur_regs *reg)
{
memset(reg, 0, sizeof(*reg));
/* Decode destination */
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_IMM)
return -EFAULT;
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_GPR_B)
reg->dst_ab = ALU_DST_B;
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_GPR_BOTH)
reg->wr_both = true;
reg->dst = nfp_swreg_to_unreg(dst, true);
/* Decode source operands */
if (FIELD_GET(NN_REG_TYPE, lreg) == FIELD_GET(NN_REG_TYPE, rreg))
return -EFAULT;
if (FIELD_GET(NN_REG_TYPE, lreg) == NN_REG_GPR_B ||
FIELD_GET(NN_REG_TYPE, rreg) == NN_REG_GPR_A) {
reg->areg = nfp_swreg_to_unreg(rreg, false);
reg->breg = nfp_swreg_to_unreg(lreg, false);
reg->swap = true;
} else {
reg->areg = nfp_swreg_to_unreg(lreg, false);
reg->breg = nfp_swreg_to_unreg(rreg, false);
}
return 0;
}
static u16 nfp_swreg_to_rereg(u32 swreg, bool is_dst, bool has_imm8, bool *i8)
{
u16 val = FIELD_GET(NN_REG_VAL, swreg);
switch (FIELD_GET(NN_REG_TYPE, swreg)) {
case NN_REG_GPR_A:
case NN_REG_GPR_B:
case NN_REG_GPR_BOTH:
return val;
case NN_REG_XFER:
return RE_REG_XFR | val;
case NN_REG_IMM:
if (val & ~(0x7f | has_imm8 << 7)) {
pr_err("immediate too large\n");
return 0;
}
*i8 = val & 0x80;
return RE_REG_IMM_encode(val & 0x7f);
case NN_REG_NONE:
return is_dst ? RE_REG_NO_DST : REG_NONE;
default:
pr_err("unrecognized reg encoding\n");
return 0;
}
}
static int
swreg_to_restricted(u32 dst, u32 lreg, u32 rreg, struct nfp_insn_re_regs *reg,
bool has_imm8)
{
memset(reg, 0, sizeof(*reg));
/* Decode destination */
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_IMM)
return -EFAULT;
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_GPR_B)
reg->dst_ab = ALU_DST_B;
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_GPR_BOTH)
reg->wr_both = true;
reg->dst = nfp_swreg_to_rereg(dst, true, false, NULL);
/* Decode source operands */
if (FIELD_GET(NN_REG_TYPE, lreg) == FIELD_GET(NN_REG_TYPE, rreg))
return -EFAULT;
if (FIELD_GET(NN_REG_TYPE, lreg) == NN_REG_GPR_B ||
FIELD_GET(NN_REG_TYPE, rreg) == NN_REG_GPR_A) {
reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
reg->swap = true;
} else {
reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
}
return 0;
}
/* --- Emitters --- */
static const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
[CMD_TGT_WRITE8] = { 0x00, 0x42 },
[CMD_TGT_READ8] = { 0x01, 0x43 },
[CMD_TGT_READ_LE] = { 0x01, 0x40 },
[CMD_TGT_READ_SWAP_LE] = { 0x03, 0x40 },
};
static void
__emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op,
u8 mode, u8 xfer, u8 areg, u8 breg, u8 size, bool sync)
......@@ -281,7 +138,7 @@ __emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op,
static void
emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op,
u8 mode, u8 xfer, u32 lreg, u32 rreg, u8 size, bool sync)
u8 mode, u8 xfer, swreg lreg, swreg rreg, u8 size, bool sync)
{
struct nfp_insn_re_regs reg;
int err;
......@@ -296,6 +153,11 @@ emit_cmd(struct nfp_prog *nfp_prog, enum cmd_tgt_map op,
nfp_prog->error = -EFAULT;
return;
}
if (reg.dst_lmextn || reg.src_lmextn) {
pr_err("cmd can't use LMextn\n");
nfp_prog->error = -EFAULT;
return;
}
__emit_cmd(nfp_prog, op, mode, xfer, reg.areg, reg.breg, size, sync);
}
......@@ -341,7 +203,7 @@ emit_br(struct nfp_prog *nfp_prog, enum br_mask mask, u16 addr, u8 defer)
static void
__emit_br_byte(struct nfp_prog *nfp_prog, u8 areg, u8 breg, bool imm8,
u8 byte, bool equal, u16 addr, u8 defer)
u8 byte, bool equal, u16 addr, u8 defer, bool src_lmextn)
{
u16 addr_lo, addr_hi;
u64 insn;
......@@ -357,32 +219,34 @@ __emit_br_byte(struct nfp_prog *nfp_prog, u8 areg, u8 breg, bool imm8,
FIELD_PREP(OP_BB_EQ, equal) |
FIELD_PREP(OP_BB_DEFBR, defer) |
FIELD_PREP(OP_BB_ADDR_LO, addr_lo) |
FIELD_PREP(OP_BB_ADDR_HI, addr_hi);
FIELD_PREP(OP_BB_ADDR_HI, addr_hi) |
FIELD_PREP(OP_BB_SRC_LMEXTN, src_lmextn);
nfp_prog_push(nfp_prog, insn);
}
static void
emit_br_byte_neq(struct nfp_prog *nfp_prog,
u32 dst, u8 imm, u8 byte, u16 addr, u8 defer)
swreg src, u8 imm, u8 byte, u16 addr, u8 defer)
{
struct nfp_insn_re_regs reg;
int err;
err = swreg_to_restricted(reg_none(), dst, reg_imm(imm), &reg, true);
err = swreg_to_restricted(reg_none(), src, reg_imm(imm), &reg, true);
if (err) {
nfp_prog->error = err;
return;
}
__emit_br_byte(nfp_prog, reg.areg, reg.breg, reg.i8, byte, false, addr,
defer);
defer, reg.src_lmextn);
}
static void
__emit_immed(struct nfp_prog *nfp_prog, u16 areg, u16 breg, u16 imm_hi,
enum immed_width width, bool invert,
enum immed_shift shift, bool wr_both)
enum immed_shift shift, bool wr_both,
bool dst_lmextn, bool src_lmextn)
{
u64 insn;
......@@ -393,19 +257,21 @@ __emit_immed(struct nfp_prog *nfp_prog, u16 areg, u16 breg, u16 imm_hi,
FIELD_PREP(OP_IMMED_WIDTH, width) |
FIELD_PREP(OP_IMMED_INV, invert) |
FIELD_PREP(OP_IMMED_SHIFT, shift) |
FIELD_PREP(OP_IMMED_WR_AB, wr_both);
FIELD_PREP(OP_IMMED_WR_AB, wr_both) |
FIELD_PREP(OP_IMMED_SRC_LMEXTN, src_lmextn) |
FIELD_PREP(OP_IMMED_DST_LMEXTN, dst_lmextn);
nfp_prog_push(nfp_prog, insn);
}
static void
emit_immed(struct nfp_prog *nfp_prog, u32 dst, u16 imm,
emit_immed(struct nfp_prog *nfp_prog, swreg dst, u16 imm,
enum immed_width width, bool invert, enum immed_shift shift)
{
struct nfp_insn_ur_regs reg;
int err;
if (FIELD_GET(NN_REG_TYPE, dst) == NN_REG_IMM) {
if (swreg_type(dst) == NN_REG_IMM) {
nfp_prog->error = -EFAULT;
return;
}
......@@ -417,13 +283,15 @@ emit_immed(struct nfp_prog *nfp_prog, u32 dst, u16 imm,
}
__emit_immed(nfp_prog, reg.areg, reg.breg, imm >> 8, width,
invert, shift, reg.wr_both);
invert, shift, reg.wr_both,
reg.dst_lmextn, reg.src_lmextn);
}
static void
__emit_shf(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab,
enum shf_sc sc, u8 shift,
u16 areg, enum shf_op op, u16 breg, bool i8, bool sw, bool wr_both)
u16 areg, enum shf_op op, u16 breg, bool i8, bool sw, bool wr_both,
bool dst_lmextn, bool src_lmextn)
{
u64 insn;
......@@ -445,14 +313,16 @@ __emit_shf(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab,
FIELD_PREP(OP_SHF_SHIFT, shift) |
FIELD_PREP(OP_SHF_OP, op) |
FIELD_PREP(OP_SHF_DST_AB, dst_ab) |
FIELD_PREP(OP_SHF_WR_AB, wr_both);
FIELD_PREP(OP_SHF_WR_AB, wr_both) |
FIELD_PREP(OP_SHF_SRC_LMEXTN, src_lmextn) |
FIELD_PREP(OP_SHF_DST_LMEXTN, dst_lmextn);
nfp_prog_push(nfp_prog, insn);
}
static void
emit_shf(struct nfp_prog *nfp_prog, u32 dst, u32 lreg, enum shf_op op, u32 rreg,
enum shf_sc sc, u8 shift)
emit_shf(struct nfp_prog *nfp_prog, swreg dst,
swreg lreg, enum shf_op op, swreg rreg, enum shf_sc sc, u8 shift)
{
struct nfp_insn_re_regs reg;
int err;
......@@ -464,12 +334,14 @@ emit_shf(struct nfp_prog *nfp_prog, u32 dst, u32 lreg, enum shf_op op, u32 rreg,
}
__emit_shf(nfp_prog, reg.dst, reg.dst_ab, sc, shift,
reg.areg, op, reg.breg, reg.i8, reg.swap, reg.wr_both);
reg.areg, op, reg.breg, reg.i8, reg.swap, reg.wr_both,
reg.dst_lmextn, reg.src_lmextn);
}
static void
__emit_alu(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab,
u16 areg, enum alu_op op, u16 breg, bool swap, bool wr_both)
u16 areg, enum alu_op op, u16 breg, bool swap, bool wr_both,
bool dst_lmextn, bool src_lmextn)
{
u64 insn;
......@@ -480,13 +352,16 @@ __emit_alu(struct nfp_prog *nfp_prog, u16 dst, enum alu_dst_ab dst_ab,
FIELD_PREP(OP_ALU_SW, swap) |
FIELD_PREP(OP_ALU_OP, op) |
FIELD_PREP(OP_ALU_DST_AB, dst_ab) |
FIELD_PREP(OP_ALU_WR_AB, wr_both);
FIELD_PREP(OP_ALU_WR_AB, wr_both) |
FIELD_PREP(OP_ALU_SRC_LMEXTN, src_lmextn) |
FIELD_PREP(OP_ALU_DST_LMEXTN, dst_lmextn);
nfp_prog_push(nfp_prog, insn);
}
static void
emit_alu(struct nfp_prog *nfp_prog, u32 dst, u32 lreg, enum alu_op op, u32 rreg)
emit_alu(struct nfp_prog *nfp_prog, swreg dst,
swreg lreg, enum alu_op op, swreg rreg)
{
struct nfp_insn_ur_regs reg;
int err;
......@@ -498,13 +373,15 @@ emit_alu(struct nfp_prog *nfp_prog, u32 dst, u32 lreg, enum alu_op op, u32 rreg)
}
__emit_alu(nfp_prog, reg.dst, reg.dst_ab,
reg.areg, op, reg.breg, reg.swap, reg.wr_both);
reg.areg, op, reg.breg, reg.swap, reg.wr_both,
reg.dst_lmextn, reg.src_lmextn);
}
static void
__emit_ld_field(struct nfp_prog *nfp_prog, enum shf_sc sc,
u8 areg, u8 bmask, u8 breg, u8 shift, bool imm8,
bool zero, bool swap, bool wr_both)
bool zero, bool swap, bool wr_both,
bool dst_lmextn, bool src_lmextn)
{
u64 insn;
......@@ -517,35 +394,44 @@ __emit_ld_field(struct nfp_prog *nfp_prog, enum shf_sc sc,
FIELD_PREP(OP_LDF_ZF, zero) |
FIELD_PREP(OP_LDF_BMASK, bmask) |
FIELD_PREP(OP_LDF_SHF, shift) |
FIELD_PREP(OP_LDF_WR_AB, wr_both);
FIELD_PREP(OP_LDF_WR_AB, wr_both) |
FIELD_PREP(OP_LDF_SRC_LMEXTN, src_lmextn) |
FIELD_PREP(OP_LDF_DST_LMEXTN, dst_lmextn);
nfp_prog_push(nfp_prog, insn);
}
static void
emit_ld_field_any(struct nfp_prog *nfp_prog, enum shf_sc sc, u8 shift,
u32 dst, u8 bmask, u32 src, bool zero)
swreg dst, u8 bmask, swreg src, bool zero)
{
struct nfp_insn_re_regs reg;
int err;
err = swreg_to_restricted(reg_none(), dst, src, &reg, true);
/* Note: ld_field is special as it uses one of the src regs as dst */
err = swreg_to_restricted(dst, dst, src, &reg, true);
if (err) {
nfp_prog->error = err;
return;
}
__emit_ld_field(nfp_prog, sc, reg.areg, bmask, reg.breg, shift,
reg.i8, zero, reg.swap, reg.wr_both);
reg.i8, zero, reg.swap, reg.wr_both,
reg.dst_lmextn, reg.src_lmextn);
}
static void
emit_ld_field(struct nfp_prog *nfp_prog, u32 dst, u8 bmask, u32 src,
emit_ld_field(struct nfp_prog *nfp_prog, swreg dst, u8 bmask, swreg src,
enum shf_sc sc, u8 shift)
{
emit_ld_field_any(nfp_prog, sc, shift, dst, bmask, src, false);
}
static void emit_nop(struct nfp_prog *nfp_prog)
{
__emit_immed(nfp_prog, UR_REG_IMM, UR_REG_IMM, 0, 0, 0, 0, 0, 0, 0);
}
/* --- Wrappers --- */
static bool pack_immed(u32 imm, u16 *val, enum immed_shift *shift)
{
......@@ -565,7 +451,7 @@ static bool pack_immed(u32 imm, u16 *val, enum immed_shift *shift)
return true;
}
static void wrp_immed(struct nfp_prog *nfp_prog, u32 dst, u32 imm)
static void wrp_immed(struct nfp_prog *nfp_prog, swreg dst, u32 imm)
{
enum immed_shift shift;
u16 val;
......@@ -586,7 +472,7 @@ static void wrp_immed(struct nfp_prog *nfp_prog, u32 dst, u32 imm)
* If the @imm is small enough encode it directly in operand and return
* otherwise load @imm to a spare register and return its encoding.
*/
static u32 ur_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, u32 tmp_reg)
static swreg ur_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, swreg tmp_reg)
{
if (FIELD_FIT(UR_REG_IMM_MAX, imm))
return reg_imm(imm);
......@@ -599,7 +485,7 @@ static u32 ur_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, u32 tmp_reg)
* If the @imm is small enough encode it directly in operand and return
* otherwise load @imm to a spare register and return its encoding.
*/
static u32 re_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, u32 tmp_reg)
static swreg re_load_imm_any(struct nfp_prog *nfp_prog, u32 imm, swreg tmp_reg)
{
if (FIELD_FIT(RE_REG_IMM_MAX, imm))
return reg_imm(imm);
......@@ -629,7 +515,7 @@ construct_data_ind_ld(struct nfp_prog *nfp_prog, u16 offset,
{
unsigned int i;
u16 shift, sz;
u32 tmp_reg;
swreg tmp_reg;
/* We load the value from the address indicated in @offset and then
* shift out the data we don't need. Note: this is big endian!
......@@ -646,22 +532,22 @@ construct_data_ind_ld(struct nfp_prog *nfp_prog, u16 offset,
emit_alu(nfp_prog, imm_a(nfp_prog),
imm_a(nfp_prog), ALU_OP_ADD, reg_imm(size));
emit_alu(nfp_prog, reg_none(),
NFP_BPF_ABI_LEN, ALU_OP_SUB, imm_a(nfp_prog));
plen_reg(nfp_prog), ALU_OP_SUB, imm_a(nfp_prog));
wrp_br_special(nfp_prog, BR_BLO, OP_BR_GO_ABORT);
/* Load data */
emit_cmd(nfp_prog, CMD_TGT_READ8, CMD_MODE_32b, 0,
pkt_reg(nfp_prog), imm_b(nfp_prog), sz - 1, true);
pptr_reg(nfp_prog), imm_b(nfp_prog), sz - 1, true);
} else {
/* Check packet length */
tmp_reg = ur_load_imm_any(nfp_prog, offset + size,
imm_a(nfp_prog));
emit_alu(nfp_prog, reg_none(),
NFP_BPF_ABI_LEN, ALU_OP_SUB, tmp_reg);
plen_reg(nfp_prog), ALU_OP_SUB, tmp_reg);
wrp_br_special(nfp_prog, BR_BLO, OP_BR_GO_ABORT);
/* Load data */
tmp_reg = re_load_imm_any(nfp_prog, offset, imm_b(nfp_prog));
emit_cmd(nfp_prog, CMD_TGT_READ8, CMD_MODE_32b, 0,
pkt_reg(nfp_prog), tmp_reg, sz - 1, true);
pptr_reg(nfp_prog), tmp_reg, sz - 1, true);
}
i = 0;
......@@ -684,20 +570,10 @@ static int construct_data_ld(struct nfp_prog *nfp_prog, u16 offset, u8 size)
return construct_data_ind_ld(nfp_prog, offset, 0, false, size);
}
static int wrp_set_mark(struct nfp_prog *nfp_prog, u8 src)
{
emit_alu(nfp_prog, NFP_BPF_ABI_MARK,
reg_none(), ALU_OP_NONE, reg_b(src));
emit_alu(nfp_prog, NFP_BPF_ABI_FLAGS,
NFP_BPF_ABI_FLAGS, ALU_OP_OR, reg_imm(NFP_BPF_ABI_FLAG_MARK));
return 0;
}
static void
wrp_alu_imm(struct nfp_prog *nfp_prog, u8 dst, enum alu_op alu_op, u32 imm)
{
u32 tmp_reg;
swreg tmp_reg;
if (alu_op == ALU_OP_AND) {
if (!imm)
......@@ -815,7 +691,7 @@ wrp_cmp_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta,
const struct bpf_insn *insn = &meta->insn;
u64 imm = insn->imm; /* sign extend */
u8 reg = insn->dst_reg * 2;
u32 tmp_reg;
swreg tmp_reg;
if (insn->off < 0) /* TODO */
return -EOPNOTSUPP;
......@@ -967,12 +843,24 @@ static int sub_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
static int shl_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
const struct bpf_insn *insn = &meta->insn;
if (insn->imm != 32)
return 1; /* TODO */
wrp_reg_mov(nfp_prog, insn->dst_reg * 2 + 1, insn->dst_reg * 2);
wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2), 0);
u8 dst = insn->dst_reg * 2;
if (insn->imm < 32) {
emit_shf(nfp_prog, reg_both(dst + 1),
reg_a(dst + 1), SHF_OP_NONE, reg_b(dst),
SHF_SC_R_DSHF, 32 - insn->imm);
emit_shf(nfp_prog, reg_both(dst),
reg_none(), SHF_OP_NONE, reg_b(dst),
SHF_SC_L_SHF, insn->imm);
} else if (insn->imm == 32) {
wrp_reg_mov(nfp_prog, dst + 1, dst);
wrp_immed(nfp_prog, reg_both(dst), 0);
} else if (insn->imm > 32) {
emit_shf(nfp_prog, reg_both(dst + 1),
reg_none(), SHF_OP_NONE, reg_b(dst),
SHF_SC_L_SHF, insn->imm - 32);
wrp_immed(nfp_prog, reg_both(dst), 0);
}
return 0;
}
......@@ -980,12 +868,24 @@ static int shl_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
static int shr_imm64(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
const struct bpf_insn *insn = &meta->insn;
if (insn->imm != 32)
return 1; /* TODO */
wrp_reg_mov(nfp_prog, insn->dst_reg * 2, insn->dst_reg * 2 + 1);
wrp_immed(nfp_prog, reg_both(insn->dst_reg * 2 + 1), 0);
u8 dst = insn->dst_reg * 2;
if (insn->imm < 32) {
emit_shf(nfp_prog, reg_both(dst),
reg_a(dst + 1), SHF_OP_NONE, reg_b(dst),
SHF_SC_R_DSHF, insn->imm);
emit_shf(nfp_prog, reg_both(dst + 1),
reg_none(), SHF_OP_NONE, reg_b(dst + 1),
SHF_SC_R_SHF, insn->imm);
} else if (insn->imm == 32) {
wrp_reg_mov(nfp_prog, dst, dst + 1);
wrp_immed(nfp_prog, reg_both(dst + 1), 0);
} else if (insn->imm > 32) {
emit_shf(nfp_prog, reg_both(dst),
reg_none(), SHF_OP_NONE, reg_b(dst + 1),
SHF_SC_R_SHF, insn->imm - 32);
wrp_immed(nfp_prog, reg_both(dst + 1), 0);
}
return 0;
}
......@@ -1130,7 +1030,7 @@ static int mem_ldx4_skb(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
if (meta->insn.off == offsetof(struct sk_buff, len))
emit_alu(nfp_prog, reg_both(meta->insn.dst_reg * 2),
reg_none(), ALU_OP_NONE, NFP_BPF_ABI_LEN);
reg_none(), ALU_OP_NONE, plen_reg(nfp_prog));
else
return -EOPNOTSUPP;
......@@ -1139,18 +1039,18 @@ static int mem_ldx4_skb(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
static int mem_ldx4_xdp(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
u32 dst = reg_both(meta->insn.dst_reg * 2);
swreg dst = reg_both(meta->insn.dst_reg * 2);
if (meta->insn.off != offsetof(struct xdp_md, data) &&
meta->insn.off != offsetof(struct xdp_md, data_end))
return -EOPNOTSUPP;
emit_alu(nfp_prog, dst, reg_none(), ALU_OP_NONE, NFP_BPF_ABI_PKT);
emit_alu(nfp_prog, dst, reg_none(), ALU_OP_NONE, pptr_reg(nfp_prog));
if (meta->insn.off == offsetof(struct xdp_md, data))
return 0;
emit_alu(nfp_prog, dst, dst, ALU_OP_ADD, NFP_BPF_ABI_LEN);
emit_alu(nfp_prog, dst, dst, ALU_OP_ADD, plen_reg(nfp_prog));
return 0;
}
......@@ -1171,9 +1071,6 @@ static int mem_ldx4(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
static int mem_stx4_skb(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
if (meta->insn.off == offsetof(struct sk_buff, mark))
return wrp_set_mark(nfp_prog, meta->insn.src_reg * 2);
return -EOPNOTSUPP;
}
......@@ -1202,8 +1099,10 @@ static int jeq_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
const struct bpf_insn *insn = &meta->insn;
u64 imm = insn->imm; /* sign extend */
u32 or1 = reg_a(insn->dst_reg * 2), or2 = reg_b(insn->dst_reg * 2 + 1);
u32 tmp_reg;
swreg or1, or2, tmp_reg;
or1 = reg_a(insn->dst_reg * 2);
or2 = reg_b(insn->dst_reg * 2 + 1);
if (insn->off < 0) /* TODO */
return -EOPNOTSUPP;
......@@ -1252,7 +1151,7 @@ static int jset_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
const struct bpf_insn *insn = &meta->insn;
u64 imm = insn->imm; /* sign extend */
u32 tmp_reg;
swreg tmp_reg;
if (insn->off < 0) /* TODO */
return -EOPNOTSUPP;
......@@ -1283,7 +1182,7 @@ static int jne_imm(struct nfp_prog *nfp_prog, struct nfp_insn_meta *meta)
{
const struct bpf_insn *insn = &meta->insn;
u64 imm = insn->imm; /* sign extend */
u32 tmp_reg;
swreg tmp_reg;
if (insn->off < 0) /* TODO */
return -EOPNOTSUPP;
......@@ -1510,8 +1409,9 @@ static int nfp_fixup_branches(struct nfp_prog *nfp_prog)
static void nfp_intro(struct nfp_prog *nfp_prog)
{
emit_alu(nfp_prog, pkt_reg(nfp_prog),
reg_none(), ALU_OP_NONE, NFP_BPF_ABI_PKT);
wrp_immed(nfp_prog, plen_reg(nfp_prog), GENMASK(13, 0));
emit_alu(nfp_prog, plen_reg(nfp_prog),
plen_reg(nfp_prog), ALU_OP_AND, pv_len(nfp_prog));
}
static void nfp_outro_tc_legacy(struct nfp_prog *nfp_prog)
......@@ -1656,7 +1556,7 @@ static void nfp_outro(struct nfp_prog *nfp_prog)
static int nfp_translate(struct nfp_prog *nfp_prog)
{
struct nfp_insn_meta *meta;
int err;
int i, err;
nfp_intro(nfp_prog);
if (nfp_prog->error)
......@@ -1688,6 +1588,11 @@ static int nfp_translate(struct nfp_prog *nfp_prog)
if (nfp_prog->error)
return nfp_prog->error;
for (i = 0; i < NFP_USTORE_PREFETCH_WINDOW; i++)
emit_nop(nfp_prog);
if (nfp_prog->error)
return nfp_prog->error;
return nfp_fixup_branches(nfp_prog);
}
......@@ -1737,38 +1642,6 @@ static void nfp_bpf_opt_reg_init(struct nfp_prog *nfp_prog)
}
}
/* Try to rename registers so that program uses only low ones */
static int nfp_bpf_opt_reg_rename(struct nfp_prog *nfp_prog)
{
bool reg_used[MAX_BPF_REG] = {};
u8 tgt_reg[MAX_BPF_REG] = {};
struct nfp_insn_meta *meta;
unsigned int i, j;
list_for_each_entry(meta, &nfp_prog->insns, l) {
if (meta->skip)
continue;
reg_used[meta->insn.src_reg] = true;
reg_used[meta->insn.dst_reg] = true;
}
for (i = 0, j = 0; i < ARRAY_SIZE(tgt_reg); i++) {
if (!reg_used[i])
continue;
tgt_reg[i] = j++;
}
nfp_prog->num_regs = j;
list_for_each_entry(meta, &nfp_prog->insns, l) {
meta->insn.src_reg = tgt_reg[meta->insn.src_reg];
meta->insn.dst_reg = tgt_reg[meta->insn.dst_reg];
}
return 0;
}
/* Remove masking after load since our load guarantees this is not needed */
static void nfp_bpf_opt_ld_mask(struct nfp_prog *nfp_prog)
{
......@@ -1845,20 +1718,33 @@ static void nfp_bpf_opt_ld_shift(struct nfp_prog *nfp_prog)
static int nfp_bpf_optimize(struct nfp_prog *nfp_prog)
{
int ret;
nfp_bpf_opt_reg_init(nfp_prog);
ret = nfp_bpf_opt_reg_rename(nfp_prog);
if (ret)
return ret;
nfp_bpf_opt_ld_mask(nfp_prog);
nfp_bpf_opt_ld_shift(nfp_prog);
return 0;
}
static int nfp_bpf_ustore_calc(struct nfp_prog *nfp_prog, __le64 *ustore)
{
int i;
for (i = 0; i < nfp_prog->prog_len; i++) {
int err;
err = nfp_ustore_check_valid_no_ecc(nfp_prog->prog[i]);
if (err)
return err;
nfp_prog->prog[i] = nfp_ustore_calc_ecc_insn(nfp_prog->prog[i]);
ustore[i] = cpu_to_le64(nfp_prog->prog[i]);
}
return 0;
}
/**
* nfp_bpf_jit() - translate BPF code into NFP assembly
* @filter: kernel BPF filter struct
......@@ -1899,10 +1785,8 @@ nfp_bpf_jit(struct bpf_prog *filter, void *prog_mem,
if (ret)
goto out;
if (nfp_prog->num_regs <= 7)
nfp_prog->regs_per_thread = 16;
else
nfp_prog->regs_per_thread = 32;
nfp_prog->num_regs = MAX_BPF_REG;
nfp_prog->regs_per_thread = 32;
nfp_prog->prog = prog_mem;
nfp_prog->__prog_alloc_len = prog_sz;
......@@ -1912,10 +1796,13 @@ nfp_bpf_jit(struct bpf_prog *filter, void *prog_mem,
pr_err("Translation failed with error %d (translated: %u)\n",
ret, nfp_prog->n_translated);
ret = -EINVAL;
goto out;
}
ret = nfp_bpf_ustore_calc(nfp_prog, (__force __le64 *)prog_mem);
res->n_instr = nfp_prog->prog_len;
res->dense_mode = nfp_prog->num_regs <= 7;
res->dense_mode = false;
out:
nfp_prog_free(nfp_prog);
......
drivers/net/ethernet/netronome/nfp/bpf/main.c
View file @ 31070e7f
......@@ -89,14 +89,6 @@ nfp_bpf_vnic_alloc(struct nfp_app *app, struct nfp_net *nn, unsigned int id)
struct nfp_net_bpf_priv *priv;
int ret;
/* Limit to single port, otherwise it's just a NIC */
if (id > 0) {
nfp_warn(app->cpp,
"BPF NIC doesn't support more than one port right now\n");
nn->port = nfp_port_alloc(app, NFP_PORT_INVALID, nn->dp.netdev);
return PTR_ERR_OR_ZERO(nn->port);
}
priv = kmalloc(sizeof(*priv), GFP_KERNEL);
if (!priv)
return -ENOMEM;
......
drivers/net/ethernet/netronome/nfp/bpf/main.h
View file @ 31070e7f
......@@ -39,6 +39,7 @@
#include <linux/list.h>
#include <linux/types.h>
#include "../nfp_asm.h"
#include "../nfp_net.h"
/* For branch fixup logic use up-most byte of branch instruction as scratch
......@@ -53,9 +54,13 @@ enum br_special {
};
enum static_regs {
STATIC_REG_PKT = 1,
#define REG_PKT_BANK ALU_DST_A
STATIC_REG_IMM = 2, /* Bank AB */
STATIC_REG_IMM = 21, /* Bank AB */
STATIC_REG_PKT_LEN = 22, /* Bank B */
};
enum pkt_vec {
PKT_VEC_PKT_LEN = 0,
PKT_VEC_PKT_PTR = 2,
};
enum nfp_bpf_action_type {
......@@ -65,39 +70,17 @@ enum nfp_bpf_action_type {
NN_ACT_XDP,
};
/* Software register representation, hardware encoding in asm.h */
#define NN_REG_TYPE GENMASK(31, 24)
#define NN_REG_VAL GENMASK(7, 0)
enum nfp_bpf_reg_type {
NN_REG_GPR_A = BIT(0),
NN_REG_GPR_B = BIT(1),
NN_REG_NNR = BIT(2),
NN_REG_XFER = BIT(3),
NN_REG_IMM = BIT(4),
NN_REG_NONE = BIT(5),
};
#define NN_REG_GPR_BOTH (NN_REG_GPR_A | NN_REG_GPR_B)
#define reg_both(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_GPR_BOTH))
#define reg_a(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_GPR_A))
#define reg_b(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_GPR_B))
#define reg_nnr(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_NNR))
#define reg_xfer(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_XFER))
#define reg_imm(x) ((x) | FIELD_PREP(NN_REG_TYPE, NN_REG_IMM))
#define reg_none() (FIELD_PREP(NN_REG_TYPE, NN_REG_NONE))
#define pv_len(np) reg_lm(1, PKT_VEC_PKT_LEN)
#define pv_ctm_ptr(np) reg_lm(1, PKT_VEC_PKT_PTR)
#define pkt_reg(np) reg_a((np)->regs_per_thread - STATIC_REG_PKT)
#define imm_a(np) reg_a((np)->regs_per_thread - STATIC_REG_IMM)
#define imm_b(np) reg_b((np)->regs_per_thread - STATIC_REG_IMM)
#define imm_both(np) reg_both((np)->regs_per_thread - STATIC_REG_IMM)
#define plen_reg(np) reg_b(STATIC_REG_PKT_LEN)
#define pptr_reg(np) pv_ctm_ptr(np)
#define imm_a(np) reg_a(STATIC_REG_IMM)
#define imm_b(np) reg_b(STATIC_REG_IMM)
#define imm_both(np) reg_both(STATIC_REG_IMM)
#define NFP_BPF_ABI_FLAGS reg_nnr(0)
#define NFP_BPF_ABI_FLAGS reg_imm(0)
#define NFP_BPF_ABI_FLAG_MARK 1
#define NFP_BPF_ABI_MARK reg_nnr(1)
#define NFP_BPF_ABI_PKT reg_nnr(2)
#define NFP_BPF_ABI_LEN reg_nnr(3)
struct nfp_prog;
struct nfp_insn_meta;
......
drivers/net/ethernet/netronome/nfp/nfp_app.h
View file @ 31070e7f
......@@ -36,6 +36,8 @@
#include <net/devlink.h>
#include <trace/events/devlink.h>
#include "nfp_net_repr.h"
struct bpf_prog;
......@@ -271,11 +273,17 @@ static inline int nfp_app_xdp_offload(struct nfp_app *app, struct nfp_net *nn,
static inline bool nfp_app_ctrl_tx(struct nfp_app *app, struct sk_buff *skb)
{
trace_devlink_hwmsg(priv_to_devlink(app->pf), false, 0,
skb->data, skb->len);
return nfp_ctrl_tx(app->ctrl, skb);
}
static inline void nfp_app_ctrl_rx(struct nfp_app *app, struct sk_buff *skb)
{
trace_devlink_hwmsg(priv_to_devlink(app->pf), true, 0,
skb->data, skb->len);
app->type->ctrl_msg_rx(app, skb);
}
......
drivers/net/ethernet/netronome/nfp/nfp_asm.c 0 → 100644
View file @ 31070e7f
/*
* Copyright (C) 2016-2017 Netronome Systems, Inc.
*
* This software is dual licensed under the GNU General License Version 2,
* June 1991 as shown in the file COPYING in the top-level directory of this
* source tree or the BSD 2-Clause License provided below. You have the
* option to license this software under the complete terms of either license.
*
* The BSD 2-Clause License:
*
* Redistribution and use in source and binary forms, with or
* without modification, are permitted provided that the following
* conditions are met:
*
* 1. Redistributions of source code must retain the above
* copyright notice, this list of conditions and the following
* disclaimer.
*
* 2. Redistributions in binary form must reproduce the above
* copyright notice, this list of conditions and the following
* disclaimer in the documentation and/or other materials
* provided with the distribution.
*
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
* SOFTWARE.
*/
#include <linux/bitops.h>
#include <linux/errno.h>
#include <linux/kernel.h>
#include <linux/string.h>
#include <linux/types.h>
#include "nfp_asm.h"
const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE] = {
[CMD_TGT_WRITE8] = { 0x00, 0x42 },
[CMD_TGT_READ8] = { 0x01, 0x43 },
[CMD_TGT_READ_LE] = { 0x01, 0x40 },
[CMD_TGT_READ_SWAP_LE] = { 0x03, 0x40 },
};
static u16 nfp_swreg_to_unreg(swreg reg, bool is_dst)
{
bool lm_id, lm_dec = false;
u16 val = swreg_value(reg);
switch (swreg_type(reg)) {
case NN_REG_GPR_A:
case NN_REG_GPR_B:
case NN_REG_GPR_BOTH:
return val;
case NN_REG_NNR:
return UR_REG_NN | val;
case NN_REG_XFER:
return UR_REG_XFR | val;
case NN_REG_LMEM:
lm_id = swreg_lm_idx(reg);
switch (swreg_lm_mode(reg)) {
case NN_LM_MOD_NONE:
if (val & ~UR_REG_LM_IDX_MAX) {
pr_err("LM offset too large\n");
return 0;
}
return UR_REG_LM | FIELD_PREP(UR_REG_LM_IDX, lm_id) |
val;
case NN_LM_MOD_DEC:
lm_dec = true;
/* fall through */
case NN_LM_MOD_INC:
if (val) {
pr_err("LM offset in inc/dev mode\n");
return 0;
}
return UR_REG_LM | UR_REG_LM_POST_MOD |
FIELD_PREP(UR_REG_LM_IDX, lm_id) |
FIELD_PREP(UR_REG_LM_POST_MOD_DEC, lm_dec);
default:
pr_err("bad LM mode for unrestricted operands %d\n",
swreg_lm_mode(reg));
return 0;
}
case NN_REG_IMM:
if (val & ~0xff) {
pr_err("immediate too large\n");
return 0;
}
return UR_REG_IMM_encode(val);
case NN_REG_NONE:
return is_dst ? UR_REG_NO_DST : REG_NONE;
}
pr_err("unrecognized reg encoding %08x\n", reg);
return 0;
}
int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
struct nfp_insn_ur_regs *reg)
{
memset(reg, 0, sizeof(*reg));
/* Decode destination */
if (swreg_type(dst) == NN_REG_IMM)
return -EFAULT;
if (swreg_type(dst) == NN_REG_GPR_B)
reg->dst_ab = ALU_DST_B;
if (swreg_type(dst) == NN_REG_GPR_BOTH)
reg->wr_both = true;
reg->dst = nfp_swreg_to_unreg(dst, true);
/* Decode source operands */
if (swreg_type(lreg) == swreg_type(rreg))
return -EFAULT;
if (swreg_type(lreg) == NN_REG_GPR_B ||
swreg_type(rreg) == NN_REG_GPR_A) {
reg->areg = nfp_swreg_to_unreg(rreg, false);
reg->breg = nfp_swreg_to_unreg(lreg, false);
reg->swap = true;
} else {
reg->areg = nfp_swreg_to_unreg(lreg, false);
reg->breg = nfp_swreg_to_unreg(rreg, false);
}
reg->dst_lmextn = swreg_lmextn(dst);
reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg);
return 0;
}
static u16 nfp_swreg_to_rereg(swreg reg, bool is_dst, bool has_imm8, bool *i8)
{
u16 val = swreg_value(reg);
bool lm_id;
switch (swreg_type(reg)) {
case NN_REG_GPR_A:
case NN_REG_GPR_B:
case NN_REG_GPR_BOTH:
return val;
case NN_REG_XFER:
return RE_REG_XFR | val;
case NN_REG_LMEM:
lm_id = swreg_lm_idx(reg);
if (swreg_lm_mode(reg) != NN_LM_MOD_NONE) {
pr_err("bad LM mode for restricted operands %d\n",
swreg_lm_mode(reg));
return 0;
}
if (val & ~RE_REG_LM_IDX_MAX) {
pr_err("LM offset too large\n");
return 0;
}
return RE_REG_LM | FIELD_PREP(RE_REG_LM_IDX, lm_id) | val;
case NN_REG_IMM:
if (val & ~(0x7f | has_imm8 << 7)) {
pr_err("immediate too large\n");
return 0;
}
*i8 = val & 0x80;
return RE_REG_IMM_encode(val & 0x7f);
case NN_REG_NONE:
return is_dst ? RE_REG_NO_DST : REG_NONE;
case NN_REG_NNR:
pr_err("NNRs used with restricted encoding\n");
return 0;
}
pr_err("unrecognized reg encoding\n");
return 0;
}
int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
struct nfp_insn_re_regs *reg, bool has_imm8)
{
memset(reg, 0, sizeof(*reg));
/* Decode destination */
if (swreg_type(dst) == NN_REG_IMM)
return -EFAULT;
if (swreg_type(dst) == NN_REG_GPR_B)
reg->dst_ab = ALU_DST_B;
if (swreg_type(dst) == NN_REG_GPR_BOTH)
reg->wr_both = true;
reg->dst = nfp_swreg_to_rereg(dst, true, false, NULL);
/* Decode source operands */
if (swreg_type(lreg) == swreg_type(rreg))
return -EFAULT;
if (swreg_type(lreg) == NN_REG_GPR_B ||
swreg_type(rreg) == NN_REG_GPR_A) {
reg->areg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
reg->breg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
reg->swap = true;
} else {
reg->areg = nfp_swreg_to_rereg(lreg, false, has_imm8, &reg->i8);
reg->breg = nfp_swreg_to_rereg(rreg, false, has_imm8, &reg->i8);
}
reg->dst_lmextn = swreg_lmextn(dst);
reg->src_lmextn = swreg_lmextn(lreg) | swreg_lmextn(rreg);
return 0;
}
#define NFP_USTORE_ECC_POLY_WORDS 7
#define NFP_USTORE_OP_BITS 45
static const u64 nfp_ustore_ecc_polynomials[NFP_USTORE_ECC_POLY_WORDS] = {
0x0ff800007fffULL,
0x11f801ff801fULL,
0x1e387e0781e1ULL,
0x17cb8e388e22ULL,
0x1af5b2c93244ULL,
0x1f56d5525488ULL,
0x0daf69a46910ULL,
};
static bool parity(u64 value)
{
return hweight64(value) & 1;
}
int nfp_ustore_check_valid_no_ecc(u64 insn)
{
if (insn & ~GENMASK_ULL(NFP_USTORE_OP_BITS, 0))
return -EINVAL;
return 0;
}
u64 nfp_ustore_calc_ecc_insn(u64 insn)
{
u8 ecc = 0;
int i;
for (i = 0; i < NFP_USTORE_ECC_POLY_WORDS; i++)
ecc |= parity(nfp_ustore_ecc_polynomials[i] & insn) << i;
return insn | (u64)ecc << NFP_USTORE_OP_BITS;
}
drivers/net/ethernet/netronome/nfp/nfp_asm.h
View file @ 31070e7f
......@@ -34,6 +34,7 @@
#ifndef __NFP_ASM_H__
#define __NFP_ASM_H__ 1
#include <linux/bitfield.h>
#include <linux/types.h>
#define REG_NONE 0
......@@ -43,23 +44,31 @@
#define RE_REG_IMM_encode(x) \
(RE_REG_IMM | ((x) & 0x1f) | (((x) & 0x60) << 1))
#define RE_REG_IMM_MAX 0x07fULL
#define RE_REG_LM 0x050
#define RE_REG_LM_IDX 0x008
#define RE_REG_LM_IDX_MAX 0x7
#define RE_REG_XFR 0x080
#define UR_REG_XFR 0x180
#define UR_REG_LM 0x200
#define UR_REG_LM_IDX 0x020
#define UR_REG_LM_POST_MOD 0x010
#define UR_REG_LM_POST_MOD_DEC 0x001
#define UR_REG_LM_IDX_MAX 0xf
#define UR_REG_NN 0x280
#define UR_REG_NO_DST 0x300
#define UR_REG_IMM UR_REG_NO_DST
#define UR_REG_IMM_encode(x) (UR_REG_IMM | (x))
#define UR_REG_IMM_MAX 0x0ffULL
#define OP_BR_BASE 0x0d800000020ULL
#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
#define OP_BR_MASK 0x0000000001fULL
#define OP_BR_EV_PIP 0x00000000300ULL
#define OP_BR_CSS 0x0000003c000ULL
#define OP_BR_DEFBR 0x00000300000ULL
#define OP_BR_ADDR_LO 0x007ffc00000ULL
#define OP_BR_ADDR_HI 0x10000000000ULL
#define OP_BR_BASE 0x0d800000020ULL
#define OP_BR_BASE_MASK 0x0f8000c3ce0ULL
#define OP_BR_MASK 0x0000000001fULL
#define OP_BR_EV_PIP 0x00000000300ULL
#define OP_BR_CSS 0x0000003c000ULL
#define OP_BR_DEFBR 0x00000300000ULL
#define OP_BR_ADDR_LO 0x007ffc00000ULL
#define OP_BR_ADDR_HI 0x10000000000ULL
#define nfp_is_br(_insn) \
(((_insn) & OP_BR_BASE_MASK) == OP_BR_BASE)
......@@ -82,30 +91,33 @@ enum br_ctx_signal_state {
BR_CSS_NONE = 2,
};
#define OP_BBYTE_BASE 0x0c800000000ULL
#define OP_BB_A_SRC 0x000000000ffULL
#define OP_BB_BYTE 0x00000000300ULL
#define OP_BB_B_SRC 0x0000003fc00ULL
#define OP_BB_I8 0x00000040000ULL
#define OP_BB_EQ 0x00000080000ULL
#define OP_BB_DEFBR 0x00000300000ULL
#define OP_BB_ADDR_LO 0x007ffc00000ULL
#define OP_BB_ADDR_HI 0x10000000000ULL
#define OP_BALU_BASE 0x0e800000000ULL
#define OP_BA_A_SRC 0x000000003ffULL
#define OP_BA_B_SRC 0x000000ffc00ULL
#define OP_BA_DEFBR 0x00000300000ULL
#define OP_BA_ADDR_HI 0x0007fc00000ULL
#define OP_IMMED_A_SRC 0x000000003ffULL
#define OP_IMMED_B_SRC 0x000000ffc00ULL
#define OP_IMMED_IMM 0x0000ff00000ULL
#define OP_IMMED_WIDTH 0x00060000000ULL
#define OP_IMMED_INV 0x00080000000ULL
#define OP_IMMED_SHIFT 0x00600000000ULL
#define OP_IMMED_BASE 0x0f000000000ULL
#define OP_IMMED_WR_AB 0x20000000000ULL
#define OP_BBYTE_BASE 0x0c800000000ULL
#define OP_BB_A_SRC 0x000000000ffULL
#define OP_BB_BYTE 0x00000000300ULL
#define OP_BB_B_SRC 0x0000003fc00ULL
#define OP_BB_I8 0x00000040000ULL
#define OP_BB_EQ 0x00000080000ULL
#define OP_BB_DEFBR 0x00000300000ULL
#define OP_BB_ADDR_LO 0x007ffc00000ULL
#define OP_BB_ADDR_HI 0x10000000000ULL
#define OP_BB_SRC_LMEXTN 0x40000000000ULL
#define OP_BALU_BASE 0x0e800000000ULL
#define OP_BA_A_SRC 0x000000003ffULL
#define OP_BA_B_SRC 0x000000ffc00ULL
#define OP_BA_DEFBR 0x00000300000ULL
#define OP_BA_ADDR_HI 0x0007fc00000ULL
#define OP_IMMED_A_SRC 0x000000003ffULL
#define OP_IMMED_B_SRC 0x000000ffc00ULL
#define OP_IMMED_IMM 0x0000ff00000ULL
#define OP_IMMED_WIDTH 0x00060000000ULL
#define OP_IMMED_INV 0x00080000000ULL
#define OP_IMMED_SHIFT 0x00600000000ULL
#define OP_IMMED_BASE 0x0f000000000ULL
#define OP_IMMED_WR_AB 0x20000000000ULL
#define OP_IMMED_SRC_LMEXTN 0x40000000000ULL
#define OP_IMMED_DST_LMEXTN 0x80000000000ULL
enum immed_width {
IMMED_WIDTH_ALL = 0,
......@@ -119,17 +131,19 @@ enum immed_shift {
IMMED_SHIFT_2B = 2,
};
#define OP_SHF_BASE 0x08000000000ULL
#define OP_SHF_A_SRC 0x000000000ffULL
#define OP_SHF_SC 0x00000000300ULL
#define OP_SHF_B_SRC 0x0000003fc00ULL
#define OP_SHF_I8 0x00000040000ULL
#define OP_SHF_SW 0x00000080000ULL
#define OP_SHF_DST 0x0000ff00000ULL
#define OP_SHF_SHIFT 0x001f0000000ULL
#define OP_SHF_OP 0x00e00000000ULL
#define OP_SHF_DST_AB 0x01000000000ULL
#define OP_SHF_WR_AB 0x20000000000ULL
#define OP_SHF_BASE 0x08000000000ULL
#define OP_SHF_A_SRC 0x000000000ffULL
#define OP_SHF_SC 0x00000000300ULL
#define OP_SHF_B_SRC 0x0000003fc00ULL
#define OP_SHF_I8 0x00000040000ULL
#define OP_SHF_SW 0x00000080000ULL
#define OP_SHF_DST 0x0000ff00000ULL
#define OP_SHF_SHIFT 0x001f0000000ULL
#define OP_SHF_OP 0x00e00000000ULL
#define OP_SHF_DST_AB 0x01000000000ULL
#define OP_SHF_WR_AB 0x20000000000ULL
#define OP_SHF_SRC_LMEXTN 0x40000000000ULL
#define OP_SHF_DST_LMEXTN 0x80000000000ULL
enum shf_op {
SHF_OP_NONE = 0,
......@@ -144,14 +158,16 @@ enum shf_sc {
SHF_SC_R_DSHF = 3,
};
#define OP_ALU_A_SRC 0x000000003ffULL
#define OP_ALU_B_SRC 0x000000ffc00ULL
#define OP_ALU_DST 0x0003ff00000ULL
#define OP_ALU_SW 0x00040000000ULL
#define OP_ALU_OP 0x00f80000000ULL
#define OP_ALU_DST_AB 0x01000000000ULL
#define OP_ALU_BASE 0x0a000000000ULL
#define OP_ALU_WR_AB 0x20000000000ULL
#define OP_ALU_A_SRC 0x000000003ffULL
#define OP_ALU_B_SRC 0x000000ffc00ULL
#define OP_ALU_DST 0x0003ff00000ULL
#define OP_ALU_SW 0x00040000000ULL
#define OP_ALU_OP 0x00f80000000ULL
#define OP_ALU_DST_AB 0x01000000000ULL
#define OP_ALU_BASE 0x0a000000000ULL
#define OP_ALU_WR_AB 0x20000000000ULL
#define OP_ALU_SRC_LMEXTN 0x40000000000ULL
#define OP_ALU_DST_LMEXTN 0x80000000000ULL
enum alu_op {
ALU_OP_NONE = 0x00,
......@@ -170,26 +186,28 @@ enum alu_dst_ab {
ALU_DST_B = 1,
};
#define OP_LDF_BASE 0x0c000000000ULL
#define OP_LDF_A_SRC 0x000000000ffULL
#define OP_LDF_SC 0x00000000300ULL
#define OP_LDF_B_SRC 0x0000003fc00ULL
#define OP_LDF_I8 0x00000040000ULL
#define OP_LDF_SW 0x00000080000ULL
#define OP_LDF_ZF 0x00000100000ULL
#define OP_LDF_BMASK 0x0000f000000ULL
#define OP_LDF_SHF 0x001f0000000ULL
#define OP_LDF_WR_AB 0x20000000000ULL
#define OP_CMD_A_SRC 0x000000000ffULL
#define OP_CMD_CTX 0x00000000300ULL
#define OP_CMD_B_SRC 0x0000003fc00ULL
#define OP_CMD_TOKEN 0x000000c0000ULL
#define OP_CMD_XFER 0x00001f00000ULL
#define OP_CMD_CNT 0x0000e000000ULL
#define OP_CMD_SIG 0x000f0000000ULL
#define OP_CMD_TGT_CMD 0x07f00000000ULL
#define OP_CMD_MODE 0x1c0000000000ULL
#define OP_LDF_BASE 0x0c000000000ULL
#define OP_LDF_A_SRC 0x000000000ffULL
#define OP_LDF_SC 0x00000000300ULL
#define OP_LDF_B_SRC 0x0000003fc00ULL
#define OP_LDF_I8 0x00000040000ULL
#define OP_LDF_SW 0x00000080000ULL
#define OP_LDF_ZF 0x00000100000ULL
#define OP_LDF_BMASK 0x0000f000000ULL
#define OP_LDF_SHF 0x001f0000000ULL
#define OP_LDF_WR_AB 0x20000000000ULL
#define OP_LDF_SRC_LMEXTN 0x40000000000ULL
#define OP_LDF_DST_LMEXTN 0x80000000000ULL
#define OP_CMD_A_SRC 0x000000000ffULL
#define OP_CMD_CTX 0x00000000300ULL
#define OP_CMD_B_SRC 0x0000003fc00ULL
#define OP_CMD_TOKEN 0x000000c0000ULL
#define OP_CMD_XFER 0x00001f00000ULL
#define OP_CMD_CNT 0x0000e000000ULL
#define OP_CMD_SIG 0x000f0000000ULL
#define OP_CMD_TGT_CMD 0x07f00000000ULL
#define OP_CMD_MODE 0x1c0000000000ULL
struct cmd_tgt_act {
u8 token;
......@@ -204,6 +222,8 @@ enum cmd_tgt_map {
__CMD_TGT_MAP_SIZE,
};
extern const struct cmd_tgt_act cmd_tgt_act[__CMD_TGT_MAP_SIZE];
enum cmd_mode {
CMD_MODE_40b_AB = 0,
CMD_MODE_40b_BA = 1,
......@@ -215,11 +235,13 @@ enum cmd_ctx_swap {
CMD_CTX_NO_SWAP = 3,
};
#define OP_LCSR_BASE 0x0fc00000000ULL
#define OP_LCSR_A_SRC 0x000000003ffULL
#define OP_LCSR_B_SRC 0x000000ffc00ULL
#define OP_LCSR_WRITE 0x00000200000ULL
#define OP_LCSR_ADDR 0x001ffc00000ULL
#define OP_LCSR_BASE 0x0fc00000000ULL
#define OP_LCSR_A_SRC 0x000000003ffULL
#define OP_LCSR_B_SRC 0x000000ffc00ULL
#define OP_LCSR_WRITE 0x00000200000ULL
#define OP_LCSR_ADDR 0x001ffc00000ULL
#define OP_LCSR_SRC_LMEXTN 0x40000000000ULL
#define OP_LCSR_DST_LMEXTN 0x80000000000ULL
enum lcsr_wr_src {
LCSR_WR_AREG,
......@@ -227,7 +249,122 @@ enum lcsr_wr_src {
LCSR_WR_IMM,
};
#define OP_CARB_BASE 0x0e000000000ULL
#define OP_CARB_OR 0x00000010000ULL
#define OP_CARB_BASE 0x0e000000000ULL
#define OP_CARB_OR 0x00000010000ULL
/* Software register representation, independent of operand type */
#define NN_REG_TYPE GENMASK(31, 24)
#define NN_REG_LM_IDX GENMASK(23, 22)
#define NN_REG_LM_IDX_HI BIT(23)
#define NN_REG_LM_IDX_LO BIT(22)
#define NN_REG_LM_MOD GENMASK(21, 20)
#define NN_REG_VAL GENMASK(7, 0)
enum nfp_bpf_reg_type {
NN_REG_GPR_A = BIT(0),
NN_REG_GPR_B = BIT(1),
NN_REG_GPR_BOTH = NN_REG_GPR_A | NN_REG_GPR_B,
NN_REG_NNR = BIT(2),
NN_REG_XFER = BIT(3),
NN_REG_IMM = BIT(4),
NN_REG_NONE = BIT(5),
NN_REG_LMEM = BIT(6),
};
enum nfp_bpf_lm_mode {
NN_LM_MOD_NONE = 0,
NN_LM_MOD_INC,
NN_LM_MOD_DEC,
};
#define reg_both(x) __enc_swreg((x), NN_REG_GPR_BOTH)
#define reg_a(x) __enc_swreg((x), NN_REG_GPR_A)
#define reg_b(x) __enc_swreg((x), NN_REG_GPR_B)
#define reg_nnr(x) __enc_swreg((x), NN_REG_NNR)
#define reg_xfer(x) __enc_swreg((x), NN_REG_XFER)
#define reg_imm(x) __enc_swreg((x), NN_REG_IMM)
#define reg_none() __enc_swreg(0, NN_REG_NONE)
#define reg_lm(x, off) __enc_swreg_lm((x), NN_LM_MOD_NONE, (off))
#define reg_lm_inc(x) __enc_swreg_lm((x), NN_LM_MOD_INC, 0)
#define reg_lm_dec(x) __enc_swreg_lm((x), NN_LM_MOD_DEC, 0)
#define __reg_lm(x, mod, off) __enc_swreg_lm((x), (mod), (off))
typedef __u32 __bitwise swreg;
static inline swreg __enc_swreg(u16 id, u8 type)
{
return (__force swreg)(id | FIELD_PREP(NN_REG_TYPE, type));
}
static inline swreg __enc_swreg_lm(u8 id, enum nfp_bpf_lm_mode mode, u8 off)
{
WARN_ON(id > 3 || (off && mode != NN_LM_MOD_NONE));
return (__force swreg)(FIELD_PREP(NN_REG_TYPE, NN_REG_LMEM) |
FIELD_PREP(NN_REG_LM_IDX, id) |
FIELD_PREP(NN_REG_LM_MOD, mode) |
off);
}
static inline u32 swreg_raw(swreg reg)
{
return (__force u32)reg;
}
static inline enum nfp_bpf_reg_type swreg_type(swreg reg)
{
return FIELD_GET(NN_REG_TYPE, swreg_raw(reg));
}
static inline u16 swreg_value(swreg reg)
{
return FIELD_GET(NN_REG_VAL, swreg_raw(reg));
}
static inline bool swreg_lm_idx(swreg reg)
{
return FIELD_GET(NN_REG_LM_IDX_LO, swreg_raw(reg));
}
static inline bool swreg_lmextn(swreg reg)
{
return FIELD_GET(NN_REG_LM_IDX_HI, swreg_raw(reg));
}
static inline enum nfp_bpf_lm_mode swreg_lm_mode(swreg reg)
{
return FIELD_GET(NN_REG_LM_MOD, swreg_raw(reg));
}
struct nfp_insn_ur_regs {
enum alu_dst_ab dst_ab;
u16 dst;
u16 areg, breg;
bool swap;
bool wr_both;
bool dst_lmextn;
bool src_lmextn;
};
struct nfp_insn_re_regs {
enum alu_dst_ab dst_ab;
u8 dst;
u8 areg, breg;
bool swap;
bool wr_both;
bool i8;
bool dst_lmextn;
bool src_lmextn;
};
int swreg_to_unrestricted(swreg dst, swreg lreg, swreg rreg,
struct nfp_insn_ur_regs *reg);
int swreg_to_restricted(swreg dst, swreg lreg, swreg rreg,
struct nfp_insn_re_regs *reg, bool has_imm8);
#define NFP_USTORE_PREFETCH_WINDOW 8
int nfp_ustore_check_valid_no_ecc(u64 insn);
u64 nfp_ustore_calc_ecc_insn(u64 insn);
#endif
drivers/net/ethernet/netronome/nfp/nfp_net_ctrl.h
View file @ 31070e7f
......@@ -255,7 +255,7 @@
* @NFP_NET_CFG_BPF_ADDR: DMA address of the buffer with JITed BPF code
*/
#define NFP_NET_CFG_BPF_ABI 0x0080
#define NFP_NET_BPF_ABI 1
#define NFP_NET_BPF_ABI 2
#define NFP_NET_CFG_BPF_CAP 0x0081
#define NFP_NET_BPF_CAP_RELO (1 << 0) /* seamless reload */
#define NFP_NET_CFG_BPF_MAX_LEN 0x0082
......
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