Skip to content

L
linux
Commit 31af04cd authored by Rob Herring's avatar Rob Herring Committed by Arnd Bergmann
Browse files
Options

arm64: dts: Remove inconsistent use of 'arm,armv8' compatible string 

The 'arm,armv8' compatible string is only for software models. It adds
little value otherwise and is inconsistently used as a fallback on some
platforms. Remove it from those platforms.

This fixes warnings generated by the DT schema.
Reported-by: default avatarMichal Simek <michal.simek@xilinx.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: default avatarAntoine Tenart <antoine.tenart@bootlin.com>
Acked-by: default avatarNishanth Menon <nm@ti.com>
Acked-by: default avatarMaxime Ripard <maxime.ripard@bootlin.com>
Acked-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Acked-by: default avatarChanho Min <chanho.min@lge.com>
Acked-by: default avatarKrzysztof Kozlowski <krzk@kernel.org>
Acked-by: default avatarMasahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: default avatarGregory CLEMENT <gregory.clement@bootlin.com>
Acked-by: default avatarThierry Reding <treding@nvidia.com>
Acked-by: default avatarHeiko Stuebner <heiko@sntech.de>
Acked-by: default avatarSimon Horman <horms+renesas@verge.net.au>
Acked-by: default avatarTero Kristo <t-kristo@ti.com>
Acked-by: default avatarWei Xu <xuwei5@hisilicon.com>
Acked-by: default avatarLiviu Dudau <liviu.dudau@arm.com>
Acked-by: default avatarMatthias Brugger <matthias.bgg@gmail.com>
Acked-by: default avatarMichal Simek <michal.simek@xilinx.com>
Acked-by: default avatarScott Branden <scott.branden@broadcom.com>
Acked-by: default avatarKevin Hilman <khilman@baylibre.com>
Acked-by: default avatarChunyan Zhang <zhang.lyra@gmail.com>
Acked-by: default avatarRobert Richter <rrichter@cavium.com>
Acked-by: default avatarJisheng Zhang <Jisheng.Zhang@synaptics.com>
Acked-by: default avatarDinh Nguyen <dinguyen@kernel.org>
Signed-off-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarArnd Bergmann <arnd@arndb.de>
parent abe60a3a
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 427 additions and 427 deletions
arch/arm64/boot/dts/actions/s700.dtsi
View file @ 31af04cd
......@@ -18,28 +18,28 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/actions/s900.dtsi
View file @ 31af04cd
......@@ -18,28 +18,28 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/al/alpine-v2.dtsi
View file @ 31af04cd
......@@ -47,28 +47,28 @@ cpus {
#size-cells = <0>;
cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
......
arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
View file @ 31af04cd
......@@ -84,7 +84,7 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
......@@ -92,7 +92,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
......@@ -100,7 +100,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
......@@ -108,7 +108,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
......
arch/arm64/boot/dts/allwinner/sun50i-h5.dtsi
View file @ 31af04cd
......@@ -48,28 +48,28 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
......
arch/arm64/boot/dts/allwinner/sun50i-h6.dtsi
View file @ 31af04cd
......@@ -22,28 +22,28 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <3>;
enable-method = "psci";
......
arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi
View file @ 31af04cd
......@@ -42,28 +42,28 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x0>;
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
......
arch/arm64/boot/dts/amlogic/meson-axg.dtsi
View file @ 31af04cd
......@@ -68,7 +68,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -77,7 +77,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -86,7 +86,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -95,7 +95,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
......
arch/arm64/boot/dts/amlogic/meson-g12a.dtsi
View file @ 31af04cd
......@@ -20,7 +20,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -28,7 +28,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -36,7 +36,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -44,7 +44,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
......
arch/arm64/boot/dts/amlogic/meson-gx.dtsi
View file @ 31af04cd
......@@ -56,7 +56,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -65,7 +65,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -74,7 +74,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -83,7 +83,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&l2>;
......
arch/arm64/boot/dts/amlogic/meson-gxm.dtsi
View file @ 31af04cd
......@@ -44,7 +44,7 @@ core3 {
cpu4: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -53,7 +53,7 @@ cpu4: cpu@100 {
cpu5: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -62,7 +62,7 @@ cpu5: cpu@101 {
cpu6: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
next-level-cache = <&l2>;
......@@ -71,7 +71,7 @@ cpu6: cpu@102 {
cpu7: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
next-level-cache = <&l2>;
......
arch/arm64/boot/dts/apm/apm-shadowcat.dtsi
View file @ 31af04cd
......@@ -21,7 +21,7 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -31,7 +31,7 @@ cpu@0 {
};
cpu@1 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -41,7 +41,7 @@ cpu@1 {
};
cpu@100 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -51,7 +51,7 @@ cpu@100 {
};
cpu@101 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -61,7 +61,7 @@ cpu@101 {
};
cpu@200 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -71,7 +71,7 @@ cpu@200 {
};
cpu@201 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x201>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -81,7 +81,7 @@ cpu@201 {
};
cpu@300 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -91,7 +91,7 @@ cpu@300 {
};
cpu@301 {
device_type = "cpu";
compatible = "apm,strega", "arm,armv8";
compatible = "apm,strega";
reg = <0x0 0x301>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......
arch/arm64/boot/dts/apm/apm-storm.dtsi
View file @ 31af04cd
......@@ -21,7 +21,7 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x000>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -29,7 +29,7 @@ cpu@0 {
};
cpu@1 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x001>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -37,7 +37,7 @@ cpu@1 {
};
cpu@100 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x100>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -45,7 +45,7 @@ cpu@100 {
};
cpu@101 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x101>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -53,7 +53,7 @@ cpu@101 {
};
cpu@200 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x200>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -61,7 +61,7 @@ cpu@200 {
};
cpu@201 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x201>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -69,7 +69,7 @@ cpu@201 {
};
cpu@300 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x300>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......@@ -77,7 +77,7 @@ cpu@300 {
};
cpu@301 {
device_type = "cpu";
compatible = "apm,potenza", "arm,armv8";
compatible = "apm,potenza";
reg = <0x0 0x301>;
enable-method = "spin-table";
cpu-release-addr = <0x1 0x0000fff8>;
......
arch/arm64/boot/dts/arm/juno-r1.dts
View file @ 31af04cd
......@@ -85,7 +85,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
......@@ -102,7 +102,7 @@ A57_0: cpu@0 {
};
A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
......@@ -119,7 +119,7 @@ A57_1: cpu@1 {
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
......@@ -136,7 +136,7 @@ A53_0: cpu@100 {
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
......@@ -153,7 +153,7 @@ A53_1: cpu@101 {
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
......@@ -170,7 +170,7 @@ A53_2: cpu@102 {
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
......
arch/arm64/boot/dts/arm/juno-r2.dts
View file @ 31af04cd
......@@ -85,7 +85,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
A72_0: cpu@0 {
compatible = "arm,cortex-a72","arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
......@@ -102,7 +102,7 @@ A72_0: cpu@0 {
};
A72_1: cpu@1 {
compatible = "arm,cortex-a72","arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
......@@ -119,7 +119,7 @@ A72_1: cpu@1 {
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
......@@ -136,7 +136,7 @@ A53_0: cpu@100 {
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
......@@ -153,7 +153,7 @@ A53_1: cpu@101 {
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
......@@ -170,7 +170,7 @@ A53_2: cpu@102 {
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
......
arch/arm64/boot/dts/arm/juno.dts
View file @ 31af04cd
......@@ -84,7 +84,7 @@ CLUSTER_SLEEP_0: cluster-sleep-0 {
};
A57_0: cpu@0 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x0>;
device_type = "cpu";
enable-method = "psci";
......@@ -101,7 +101,7 @@ A57_0: cpu@0 {
};
A57_1: cpu@1 {
compatible = "arm,cortex-a57","arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0 0x1>;
device_type = "cpu";
enable-method = "psci";
......@@ -118,7 +118,7 @@ A57_1: cpu@1 {
};
A53_0: cpu@100 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
device_type = "cpu";
enable-method = "psci";
......@@ -135,7 +135,7 @@ A53_0: cpu@100 {
};
A53_1: cpu@101 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
device_type = "cpu";
enable-method = "psci";
......@@ -152,7 +152,7 @@ A53_1: cpu@101 {
};
A53_2: cpu@102 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
device_type = "cpu";
enable-method = "psci";
......@@ -169,7 +169,7 @@ A53_2: cpu@102 {
};
A53_3: cpu@103 {
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
device_type = "cpu";
enable-method = "psci";
......
arch/arm64/boot/dts/arm/vexpress-v2f-1xv7-ca53x2.dts
View file @ 31af04cd
......@@ -43,14 +43,14 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0>;
next-level-cache = <&L2_0>;
};
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 1>;
next-level-cache = <&L2_0>;
};
......
arch/arm64/boot/dts/broadcom/northstar2/ns2.dtsi
View file @ 31af04cd
......@@ -47,7 +47,7 @@ cpus {
A57_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0 0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......@@ -55,7 +55,7 @@ A57_0: cpu@0 {
A57_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0 1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......@@ -63,7 +63,7 @@ A57_1: cpu@1 {
A57_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0 2>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......@@ -71,7 +71,7 @@ A57_2: cpu@2 {
A57_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0 3>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......
arch/arm64/boot/dts/broadcom/stingray/stingray.dtsi
View file @ 31af04cd
......@@ -44,7 +44,7 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x0>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......@@ -52,7 +52,7 @@ cpu@0 {
cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&CLUSTER0_L2>;
......@@ -60,7 +60,7 @@ cpu@1 {
cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
......@@ -68,7 +68,7 @@ cpu@100 {
cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
next-level-cache = <&CLUSTER1_L2>;
......@@ -76,7 +76,7 @@ cpu@101 {
cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x200>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
......@@ -84,7 +84,7 @@ cpu@200 {
cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x201>;
enable-method = "psci";
next-level-cache = <&CLUSTER2_L2>;
......@@ -92,7 +92,7 @@ cpu@201 {
cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x300>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
......@@ -100,7 +100,7 @@ cpu@300 {
cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x301>;
enable-method = "psci";
next-level-cache = <&CLUSTER3_L2>;
......
arch/arm64/boot/dts/cavium/thunder-88xx.dtsi
View file @ 31af04cd
......@@ -64,289 +64,289 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x000>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x001>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x002>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x003>;
enable-method = "psci";
};
cpu@4 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x004>;
enable-method = "psci";
};
cpu@5 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x005>;
enable-method = "psci";
};
cpu@6 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x006>;
enable-method = "psci";
};
cpu@7 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x007>;
enable-method = "psci";
};
cpu@8 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x008>;
enable-method = "psci";
};
cpu@9 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x009>;
enable-method = "psci";
};
cpu@a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00a>;
enable-method = "psci";
};
cpu@b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00b>;
enable-method = "psci";
};
cpu@c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00c>;
enable-method = "psci";
};
cpu@d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00d>;
enable-method = "psci";
};
cpu@e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00e>;
enable-method = "psci";
};
cpu@f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x00f>;
enable-method = "psci";
};
cpu@100 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu@101 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu@102 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu@103 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x103>;
enable-method = "psci";
};
cpu@104 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x104>;
enable-method = "psci";
};
cpu@105 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x105>;
enable-method = "psci";
};
cpu@106 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x106>;
enable-method = "psci";
};
cpu@107 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x107>;
enable-method = "psci";
};
cpu@108 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x108>;
enable-method = "psci";
};
cpu@109 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x109>;
enable-method = "psci";
};
cpu@10a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10a>;
enable-method = "psci";
};
cpu@10b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10b>;
enable-method = "psci";
};
cpu@10c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10c>;
enable-method = "psci";
};
cpu@10d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10d>;
enable-method = "psci";
};
cpu@10e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10e>;
enable-method = "psci";
};
cpu@10f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x10f>;
enable-method = "psci";
};
cpu@200 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x200>;
enable-method = "psci";
};
cpu@201 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x201>;
enable-method = "psci";
};
cpu@202 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x202>;
enable-method = "psci";
};
cpu@203 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x203>;
enable-method = "psci";
};
cpu@204 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x204>;
enable-method = "psci";
};
cpu@205 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x205>;
enable-method = "psci";
};
cpu@206 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x206>;
enable-method = "psci";
};
cpu@207 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x207>;
enable-method = "psci";
};
cpu@208 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x208>;
enable-method = "psci";
};
cpu@209 {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x209>;
enable-method = "psci";
};
cpu@20a {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20a>;
enable-method = "psci";
};
cpu@20b {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20b>;
enable-method = "psci";
};
cpu@20c {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20c>;
enable-method = "psci";
};
cpu@20d {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20d>;
enable-method = "psci";
};
cpu@20e {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20e>;
enable-method = "psci";
};
cpu@20f {
device_type = "cpu";
compatible = "cavium,thunder", "arm,armv8";
compatible = "cavium,thunder";
reg = <0x0 0x20f>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/cavium/thunder2-99xx.dtsi
View file @ 31af04cd
......@@ -27,28 +27,28 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu@1 {
device_type = "cpu";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu@2 {
device_type = "cpu";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu@3 {
device_type = "cpu";
compatible = "cavium,thunder2", "brcm,vulcan", "arm,armv8";
compatible = "cavium,thunder2", "brcm,vulcan";
reg = <0x0 0x3>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/exynos/exynos5433.dtsi
View file @ 31af04cd
......@@ -29,7 +29,7 @@ cpus {
cpu0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x100>;
clock-frequency = <1300000000>;
......@@ -41,7 +41,7 @@ cpu0: cpu@100 {
cpu1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x101>;
clock-frequency = <1300000000>;
......@@ -51,7 +51,7 @@ cpu1: cpu@101 {
cpu2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x102>;
clock-frequency = <1300000000>;
......@@ -61,7 +61,7 @@ cpu2: cpu@102 {
cpu3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x103>;
clock-frequency = <1300000000>;
......@@ -71,7 +71,7 @@ cpu3: cpu@103 {
cpu4: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x0>;
clock-frequency = <1900000000>;
......@@ -83,7 +83,7 @@ cpu4: cpu@0 {
cpu5: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x1>;
clock-frequency = <1900000000>;
......@@ -93,7 +93,7 @@ cpu5: cpu@1 {
cpu6: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x2>;
clock-frequency = <1900000000>;
......@@ -103,7 +103,7 @@ cpu6: cpu@2 {
cpu7: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
enable-method = "psci";
reg = <0x3>;
clock-frequency = <1900000000>;
......
arch/arm64/boot/dts/exynos/exynos7.dtsi
View file @ 31af04cd
......@@ -34,28 +34,28 @@ cpus {
cpu_atlas0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0>;
enable-method = "psci";
};
cpu_atlas1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x1>;
enable-method = "psci";
};
cpu_atlas2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x2>;
enable-method = "psci";
};
cpu_atlas3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x3>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/hisilicon/hi3660.dtsi
View file @ 31af04cd
......@@ -56,7 +56,7 @@ core3 {
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
......@@ -70,7 +70,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
......@@ -83,7 +83,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
......@@ -96,7 +96,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
......@@ -109,7 +109,7 @@ cpu3: cpu@3 {
};
cpu4: cpu@100 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
......@@ -123,7 +123,7 @@ cpu4: cpu@100 {
};
cpu5: cpu@101 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
......@@ -136,7 +136,7 @@ cpu5: cpu@101 {
};
cpu6: cpu@102 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
......@@ -149,7 +149,7 @@ cpu6: cpu@102 {
};
cpu7: cpu@103 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
......
arch/arm64/boot/dts/hisilicon/hi3670.dtsi
View file @ 31af04cd
......@@ -56,56 +56,56 @@ core3 {
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
};
cpu4: cpu@100 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
};
cpu5: cpu@101 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
};
cpu6: cpu@102 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
};
cpu7: cpu@103 {
compatible = "arm,cortex-a73", "arm,armv8";
compatible = "arm,cortex-a73";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
......
arch/arm64/boot/dts/hisilicon/hi6220.dtsi
View file @ 31af04cd
......@@ -81,7 +81,7 @@ CLUSTER_SLEEP: cluster-sleep {
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x0>;
enable-method = "psci";
......@@ -94,7 +94,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x1>;
enable-method = "psci";
......@@ -107,7 +107,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x2>;
enable-method = "psci";
......@@ -120,7 +120,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x3>;
enable-method = "psci";
......@@ -133,7 +133,7 @@ cpu3: cpu@3 {
};
cpu4: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x100>;
enable-method = "psci";
......@@ -146,7 +146,7 @@ cpu4: cpu@100 {
};
cpu5: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x101>;
enable-method = "psci";
......@@ -159,7 +159,7 @@ cpu5: cpu@101 {
};
cpu6: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x102>;
enable-method = "psci";
......@@ -172,7 +172,7 @@ cpu6: cpu@102 {
};
cpu7: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0 0x103>;
enable-method = "psci";
......
arch/arm64/boot/dts/hisilicon/hip05.dtsi
View file @ 31af04cd
......@@ -87,7 +87,7 @@ core3 {
cpu0: cpu@20000 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20000>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -95,7 +95,7 @@ cpu0: cpu@20000 {
cpu1: cpu@20001 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20001>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -103,7 +103,7 @@ cpu1: cpu@20001 {
cpu2: cpu@20002 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20002>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -111,7 +111,7 @@ cpu2: cpu@20002 {
cpu3: cpu@20003 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20003>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -119,7 +119,7 @@ cpu3: cpu@20003 {
cpu4: cpu@20100 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -127,7 +127,7 @@ cpu4: cpu@20100 {
cpu5: cpu@20101 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -135,7 +135,7 @@ cpu5: cpu@20101 {
cpu6: cpu@20102 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20102>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -143,7 +143,7 @@ cpu6: cpu@20102 {
cpu7: cpu@20103 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20103>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -151,7 +151,7 @@ cpu7: cpu@20103 {
cpu8: cpu@20200 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20200>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -159,7 +159,7 @@ cpu8: cpu@20200 {
cpu9: cpu@20201 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20201>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -167,7 +167,7 @@ cpu9: cpu@20201 {
cpu10: cpu@20202 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20202>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -175,7 +175,7 @@ cpu10: cpu@20202 {
cpu11: cpu@20203 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20203>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -183,7 +183,7 @@ cpu11: cpu@20203 {
cpu12: cpu@20300 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20300>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -191,7 +191,7 @@ cpu12: cpu@20300 {
cpu13: cpu@20301 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20301>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -199,7 +199,7 @@ cpu13: cpu@20301 {
cpu14: cpu@20302 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20302>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -207,7 +207,7 @@ cpu14: cpu@20302 {
cpu15: cpu@20303 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x20303>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......
arch/arm64/boot/dts/hisilicon/hip06.dtsi
View file @ 31af04cd
......@@ -87,7 +87,7 @@ core3 {
cpu0: cpu@10000 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10000>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -95,7 +95,7 @@ cpu0: cpu@10000 {
cpu1: cpu@10001 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10001>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -103,7 +103,7 @@ cpu1: cpu@10001 {
cpu2: cpu@10002 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10002>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -111,7 +111,7 @@ cpu2: cpu@10002 {
cpu3: cpu@10003 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10003>;
enable-method = "psci";
next-level-cache = <&cluster0_l2>;
......@@ -119,7 +119,7 @@ cpu3: cpu@10003 {
cpu4: cpu@10100 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10100>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -127,7 +127,7 @@ cpu4: cpu@10100 {
cpu5: cpu@10101 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10101>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -135,7 +135,7 @@ cpu5: cpu@10101 {
cpu6: cpu@10102 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10102>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -143,7 +143,7 @@ cpu6: cpu@10102 {
cpu7: cpu@10103 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10103>;
enable-method = "psci";
next-level-cache = <&cluster1_l2>;
......@@ -151,7 +151,7 @@ cpu7: cpu@10103 {
cpu8: cpu@10200 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10200>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -159,7 +159,7 @@ cpu8: cpu@10200 {
cpu9: cpu@10201 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10201>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -167,7 +167,7 @@ cpu9: cpu@10201 {
cpu10: cpu@10202 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10202>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -175,7 +175,7 @@ cpu10: cpu@10202 {
cpu11: cpu@10203 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10203>;
enable-method = "psci";
next-level-cache = <&cluster2_l2>;
......@@ -183,7 +183,7 @@ cpu11: cpu@10203 {
cpu12: cpu@10300 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10300>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -191,7 +191,7 @@ cpu12: cpu@10300 {
cpu13: cpu@10301 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10301>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -199,7 +199,7 @@ cpu13: cpu@10301 {
cpu14: cpu@10302 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10302>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......@@ -207,7 +207,7 @@ cpu14: cpu@10302 {
cpu15: cpu@10303 {
device_type = "cpu";
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x10303>;
enable-method = "psci";
next-level-cache = <&cluster3_l2>;
......
arch/arm64/boot/dts/hisilicon/hip07.dtsi
View file @ 31af04cd
This diff is collapsed.
arch/arm64/boot/dts/lg/lg1312.dtsi
View file @ 31af04cd
......@@ -21,27 +21,27 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
......
arch/arm64/boot/dts/lg/lg1313.dtsi
View file @ 31af04cd
......@@ -21,27 +21,27 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
next-level-cache = <&L2_0>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
next-level-cache = <&L2_0>;
......
arch/arm64/boot/dts/marvell/armada-372x.dtsi
View file @ 31af04cd
......@@ -18,7 +18,7 @@ / {
cpus {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x1>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
......
arch/arm64/boot/dts/marvell/armada-37xx.dtsi
View file @ 31af04cd
......@@ -42,7 +42,7 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0>;
clocks = <&nb_periph_clk 16>;
enable-method = "psci";
......
arch/arm64/boot/dts/marvell/armada-ap806-dual.dtsi
View file @ 31af04cd
......@@ -17,13 +17,13 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x000>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x001>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/marvell/armada-ap806-quad.dtsi
View file @ 31af04cd
......@@ -17,25 +17,25 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x000>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x001>;
enable-method = "psci";
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/marvell/armada-ap810-ap0-octa-core.dtsi
View file @ 31af04cd
......@@ -15,49 +15,49 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x000>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x001>;
enable-method = "psci";
};
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x100>;
enable-method = "psci";
};
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x101>;
enable-method = "psci";
};
cpu4: cpu@200 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x200>;
enable-method = "psci";
};
cpu5: cpu@201 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x201>;
enable-method = "psci";
};
cpu6: cpu@300 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x300>;
enable-method = "psci";
};
cpu7: cpu@301 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x301>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/mediatek/mt7622.dtsi
View file @ 31af04cd
......@@ -70,7 +70,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
......@@ -84,7 +84,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&infracfg CLK_INFRA_MUX1_SEL>,
<&apmixedsys CLK_APMIXED_MAIN_CORE_EN>;
......
arch/arm64/boot/dts/nvidia/tegra132.dtsi
View file @ 31af04cd
......@@ -1082,13 +1082,13 @@ cpus {
cpu@0 {
device_type = "cpu";
compatible = "nvidia,denver", "arm,armv8";
compatible = "nvidia,denver";
reg = <0>;
};
cpu@1 {
device_type = "cpu";
compatible = "nvidia,denver", "arm,armv8";
compatible = "nvidia,denver";
reg = <1>;
};
};
......
arch/arm64/boot/dts/nvidia/tegra186.dtsi
View file @ 31af04cd
......@@ -982,37 +982,37 @@ cpus {
#size-cells = <0>;
cpu@0 {
compatible = "nvidia,tegra186-denver", "arm,armv8";
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
reg = <0x000>;
};
cpu@1 {
compatible = "nvidia,tegra186-denver", "arm,armv8";
compatible = "nvidia,tegra186-denver";
device_type = "cpu";
reg = <0x001>;
};
cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x100>;
};
cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x101>;
};
cpu@4 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x102>;
};
cpu@5 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
device_type = "cpu";
reg = <0x103>;
};
......
arch/arm64/boot/dts/nvidia/tegra194.dtsi
View file @ 31af04cd
......@@ -871,56 +871,56 @@ cpus {
#size-cells = <0>;
cpu@0 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x10000>;
enable-method = "psci";
};
cpu@1 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x10001>;
enable-method = "psci";
};
cpu@2 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x100>;
enable-method = "psci";
};
cpu@3 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x101>;
enable-method = "psci";
};
cpu@4 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x200>;
enable-method = "psci";
};
cpu@5 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x201>;
enable-method = "psci";
};
cpu@6 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x10300>;
enable-method = "psci";
};
cpu@7 {
compatible = "nvidia,tegra194-carmel", "arm,armv8";
compatible = "nvidia,tegra194-carmel";
device_type = "cpu";
reg = <0x10301>;
enable-method = "psci";
......
arch/arm64/boot/dts/qcom/ipq8074.dtsi
View file @ 31af04cd
......@@ -441,7 +441,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
......@@ -449,7 +449,7 @@ CPU0: cpu@0 {
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x1>;
next-level-cache = <&L2_0>;
......@@ -457,7 +457,7 @@ CPU1: cpu@1 {
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x2>;
next-level-cache = <&L2_0>;
......@@ -465,7 +465,7 @@ CPU2: cpu@2 {
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
enable-method = "psci";
reg = <0x3>;
next-level-cache = <&L2_0>;
......
arch/arm64/boot/dts/qcom/msm8916.dtsi
View file @ 31af04cd
......@@ -106,7 +106,7 @@ cpus {
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
enable-method = "psci";
......@@ -118,7 +118,7 @@ CPU0: cpu@0 {
CPU1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x1>;
next-level-cache = <&L2_0>;
enable-method = "psci";
......@@ -130,7 +130,7 @@ CPU1: cpu@1 {
CPU2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x2>;
next-level-cache = <&L2_0>;
enable-method = "psci";
......@@ -142,7 +142,7 @@ CPU2: cpu@2 {
CPU3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x3>;
next-level-cache = <&L2_0>;
enable-method = "psci";
......
arch/arm64/boot/dts/qcom/msm8992.dtsi
View file @ 31af04cd
......@@ -38,7 +38,7 @@ core0 {
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
......
arch/arm64/boot/dts/qcom/msm8994.dtsi
View file @ 31af04cd
......@@ -40,7 +40,7 @@ core0 {
CPU0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0>;
next-level-cache = <&L2_0>;
L2_0: l2-cache {
......
arch/arm64/boot/dts/realtek/rtd1295.dtsi
View file @ 31af04cd
......@@ -17,28 +17,28 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
next-level-cache = <&l2>;
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
next-level-cache = <&l2>;
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
next-level-cache = <&l2>;
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
next-level-cache = <&l2>;
};
......
arch/arm64/boot/dts/renesas/r8a774a1.dtsi
View file @ 31af04cd
......@@ -61,7 +61,7 @@ cpus {
#size-cells = <0>;
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU0>;
......@@ -71,7 +71,7 @@ a57_0: cpu@0 {
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA57_CPU1>;
......@@ -81,7 +81,7 @@ a57_1: cpu@1 {
};
a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU0>;
......@@ -91,7 +91,7 @@ a53_0: cpu@100 {
};
a53_1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU1>;
......@@ -101,7 +101,7 @@ a53_1: cpu@101 {
};
a53_2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU2>;
......@@ -111,7 +111,7 @@ a53_2: cpu@102 {
};
a53_3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A774A1_PD_CA53_CPU3>;
......
arch/arm64/boot/dts/renesas/r8a7795.dtsi
View file @ 31af04cd
......@@ -149,7 +149,7 @@ core3 {
};
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU0>;
......@@ -162,7 +162,7 @@ a57_0: cpu@0 {
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU1>;
......@@ -175,7 +175,7 @@ a57_1: cpu@1 {
};
a57_2: cpu@2 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x2>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU2>;
......@@ -188,7 +188,7 @@ a57_2: cpu@2 {
};
a57_3: cpu@3 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x3>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA57_CPU3>;
......@@ -201,7 +201,7 @@ a57_3: cpu@3 {
};
a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU0>;
......@@ -213,7 +213,7 @@ a53_0: cpu@100 {
};
a53_1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU1>;
......@@ -225,7 +225,7 @@ a53_1: cpu@101 {
};
a53_2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU2>;
......@@ -237,7 +237,7 @@ a53_2: cpu@102 {
};
a53_3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A7795_PD_CA53_CPU3>;
......
arch/arm64/boot/dts/renesas/r8a7796.dtsi
View file @ 31af04cd
......@@ -154,7 +154,7 @@ core3 {
};
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU0>;
......@@ -167,7 +167,7 @@ a57_0: cpu@0 {
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA57_CPU1>;
......@@ -180,7 +180,7 @@ a57_1: cpu@1 {
};
a53_0: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU0>;
......@@ -192,7 +192,7 @@ a53_0: cpu@100 {
};
a53_1: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU1>;
......@@ -204,7 +204,7 @@ a53_1: cpu@101 {
};
a53_2: cpu@102 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x102>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU2>;
......@@ -216,7 +216,7 @@ a53_2: cpu@102 {
};
a53_3: cpu@103 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x103>;
device_type = "cpu";
power-domains = <&sysc R8A7796_PD_CA53_CPU3>;
......
arch/arm64/boot/dts/renesas/r8a77965.dtsi
View file @ 31af04cd
......@@ -105,7 +105,7 @@ cpus {
#size-cells = <0>;
a57_0: cpu@0 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A77965_PD_CA57_CPU0>;
......@@ -116,7 +116,7 @@ a57_0: cpu@0 {
};
a57_1: cpu@1 {
compatible = "arm,cortex-a57", "arm,armv8";
compatible = "arm,cortex-a57";
reg = <0x1>;
device_type = "cpu";
power-domains = <&sysc R8A77965_PD_CA57_CPU1>;
......
arch/arm64/boot/dts/renesas/r8a77970.dtsi
View file @ 31af04cd
......@@ -37,7 +37,7 @@ cpus {
a53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU0>;
......@@ -47,7 +47,7 @@ a53_0: cpu@0 {
a53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <1>;
clocks = <&cpg CPG_CORE R8A77970_CLK_Z2>;
power-domains = <&sysc R8A77970_PD_CA53_CPU1>;
......
arch/arm64/boot/dts/renesas/r8a77980.dtsi
View file @ 31af04cd
......@@ -38,7 +38,7 @@ cpus {
a53_0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0>;
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc R8A77980_PD_CA53_CPU0>;
......@@ -48,7 +48,7 @@ a53_0: cpu@0 {
a53_1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <1>;
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc R8A77980_PD_CA53_CPU1>;
......@@ -58,7 +58,7 @@ a53_1: cpu@1 {
a53_2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <2>;
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc R8A77980_PD_CA53_CPU2>;
......@@ -68,7 +68,7 @@ a53_2: cpu@2 {
a53_3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <3>;
clocks = <&cpg CPG_CORE R8A77980_CLK_Z2>;
power-domains = <&sysc R8A77980_PD_CA53_CPU3>;
......
arch/arm64/boot/dts/renesas/r8a77990.dtsi
View file @ 31af04cd
......@@ -60,7 +60,7 @@ cpus {
#size-cells = <0>;
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0>;
device_type = "cpu";
power-domains = <&sysc R8A77990_PD_CA53_CPU0>;
......@@ -69,7 +69,7 @@ a53_0: cpu@0 {
};
a53_1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <1>;
device_type = "cpu";
power-domains = <&sysc R8A77990_PD_CA53_CPU1>;
......
arch/arm64/boot/dts/renesas/r8a77995.dtsi
View file @ 31af04cd
......@@ -27,7 +27,7 @@ cpus {
#size-cells = <0>;
a53_0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0>;
device_type = "cpu";
power-domains = <&sysc R8A77995_PD_CA53_CPU0>;
......
arch/arm64/boot/dts/rockchip/px30.dtsi
View file @ 31af04cd
......@@ -40,7 +40,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
......@@ -52,7 +52,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
......@@ -64,7 +64,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
......@@ -76,7 +76,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a35", "arm,armv8";
compatible = "arm,cortex-a35";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLK>;
......
arch/arm64/boot/dts/rockchip/rk3328.dtsi
View file @ 31af04cd
......@@ -37,7 +37,7 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
......@@ -49,7 +49,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
......@@ -61,7 +61,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
......@@ -73,7 +73,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
clocks = <&cru ARMCLK>;
#cooling-cells = <2>;
......
arch/arm64/boot/dts/rockchip/rk3368.dtsi
View file @ 31af04cd
......@@ -73,7 +73,7 @@ core3 {
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -81,7 +81,7 @@ cpu_l0: cpu@0 {
cpu_l1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -89,7 +89,7 @@ cpu_l1: cpu@1 {
cpu_l2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -97,7 +97,7 @@ cpu_l2: cpu@2 {
cpu_l3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -105,7 +105,7 @@ cpu_l3: cpu@3 {
cpu_b0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x100>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -113,7 +113,7 @@ cpu_b0: cpu@100 {
cpu_b1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x101>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -121,7 +121,7 @@ cpu_b1: cpu@101 {
cpu_b2: cpu@102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x102>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......@@ -129,7 +129,7 @@ cpu_b2: cpu@102 {
cpu_b3: cpu@103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x103>;
enable-method = "psci";
#cooling-cells = <2>; /* min followed by max */
......
arch/arm64/boot/dts/rockchip/rk3399.dtsi
View file @ 31af04cd
......@@ -68,7 +68,7 @@ core1 {
cpu_l0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
......@@ -79,7 +79,7 @@ cpu_l0: cpu@0 {
cpu_l1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
......@@ -90,7 +90,7 @@ cpu_l1: cpu@1 {
cpu_l2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
......@@ -101,7 +101,7 @@ cpu_l2: cpu@2 {
cpu_l3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&cru ARMCLKL>;
......@@ -112,7 +112,7 @@ cpu_l3: cpu@3 {
cpu_b0: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x100>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
......@@ -123,7 +123,7 @@ cpu_b0: cpu@100 {
cpu_b1: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0x0 0x101>;
enable-method = "psci";
clocks = <&cru ARMCLKB>;
......
arch/arm64/boot/dts/socionext/uniphier-ld11.dtsi
View file @ 31af04cd
......@@ -33,7 +33,7 @@ core1 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......@@ -42,7 +42,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......
arch/arm64/boot/dts/socionext/uniphier-ld20.dtsi
View file @ 31af04cd
......@@ -43,7 +43,7 @@ core1 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0 0x000>;
clocks = <&sys_clk 32>;
enable-method = "psci";
......@@ -53,7 +53,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a72", "arm,armv8";
compatible = "arm,cortex-a72";
reg = <0 0x001>;
clocks = <&sys_clk 32>;
enable-method = "psci";
......@@ -63,7 +63,7 @@ cpu1: cpu@1 {
cpu2: cpu@100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x100>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......@@ -73,7 +73,7 @@ cpu2: cpu@100 {
cpu3: cpu@101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x101>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......
arch/arm64/boot/dts/socionext/uniphier-pxs3.dtsi
View file @ 31af04cd
......@@ -39,7 +39,7 @@ core3 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x000>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......@@ -48,7 +48,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x001>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......@@ -57,7 +57,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x002>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......@@ -66,7 +66,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0 0x003>;
clocks = <&sys_clk 33>;
enable-method = "psci";
......
arch/arm64/boot/dts/sprd/sc9836.dtsi
View file @ 31af04cd
......@@ -18,28 +18,28 @@ cpus {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
};
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
};
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
};
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
};
......
arch/arm64/boot/dts/sprd/sc9860.dtsi
View file @ 31af04cd
......@@ -50,7 +50,7 @@ core3 {
CPU0: cpu@530000 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530000>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -58,7 +58,7 @@ CPU0: cpu@530000 {
CPU1: cpu@530001 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530001>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -66,7 +66,7 @@ CPU1: cpu@530001 {
CPU2: cpu@530002 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530002>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -74,7 +74,7 @@ CPU2: cpu@530002 {
CPU3: cpu@530003 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530003>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -82,7 +82,7 @@ CPU3: cpu@530003 {
CPU4: cpu@530100 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530100>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -90,7 +90,7 @@ CPU4: cpu@530100 {
CPU5: cpu@530101 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530101>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -98,7 +98,7 @@ CPU5: cpu@530101 {
CPU6: cpu@530102 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530102>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......@@ -106,7 +106,7 @@ CPU6: cpu@530102 {
CPU7: cpu@530103 {
device_type = "cpu";
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x530103>;
enable-method = "psci";
cpu-idle-states = <&CORE_PD &CLUSTER_PD>;
......
arch/arm64/boot/dts/synaptics/as370.dtsi
View file @ 31af04cd
......@@ -23,7 +23,7 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
......@@ -32,7 +32,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
......@@ -41,7 +41,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
......@@ -50,7 +50,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
......
arch/arm64/boot/dts/synaptics/berlin4ct.dtsi
View file @ 31af04cd
......@@ -27,7 +27,7 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x0>;
enable-method = "psci";
......@@ -36,7 +36,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x1>;
enable-method = "psci";
......@@ -45,7 +45,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x2>;
enable-method = "psci";
......@@ -54,7 +54,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
reg = <0x3>;
enable-method = "psci";
......
arch/arm64/boot/dts/ti/k3-am654.dtsi
View file @ 31af04cd
......@@ -34,7 +34,7 @@ core1 {
};
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x000>;
device_type = "cpu";
enable-method = "psci";
......@@ -48,7 +48,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x001>;
device_type = "cpu";
enable-method = "psci";
......@@ -62,7 +62,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@100 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x100>;
device_type = "cpu";
enable-method = "psci";
......@@ -76,7 +76,7 @@ cpu2: cpu@100 {
};
cpu3: cpu@101 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x101>;
device_type = "cpu";
enable-method = "psci";
......
arch/arm64/boot/dts/xilinx/zynqmp.dtsi
View file @ 31af04cd
......@@ -22,7 +22,7 @@ cpus {
#size-cells = <0>;
cpu0: cpu@0 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
operating-points-v2 = <&cpu_opp_table>;
......@@ -31,7 +31,7 @@ cpu0: cpu@0 {
};
cpu1: cpu@1 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x1>;
......@@ -40,7 +40,7 @@ cpu1: cpu@1 {
};
cpu2: cpu@2 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x2>;
......@@ -49,7 +49,7 @@ cpu2: cpu@2 {
};
cpu3: cpu@3 {
compatible = "arm,cortex-a53", "arm,armv8";
compatible = "arm,cortex-a53";
device_type = "cpu";
enable-method = "psci";
reg = <0x3>;
......
arch/arm64/boot/dts/zte/zx296718.dtsi
View file @ 31af04cd
......@@ -86,7 +86,7 @@ core3 {
cpu0: cpu@0 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x0>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
......@@ -95,7 +95,7 @@ cpu0: cpu@0 {
cpu1: cpu@1 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x1>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
......@@ -104,7 +104,7 @@ cpu1: cpu@1 {
cpu2: cpu@2 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x2>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
......@@ -113,7 +113,7 @@ cpu2: cpu@2 {
cpu3: cpu@3 {
device_type = "cpu";
compatible = "arm,cortex-a53","arm,armv8";
compatible = "arm,cortex-a53";
reg = <0x0 0x3>;
enable-method = "psci";
clocks = <&topcrm A53_GATE>;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment
GitLab Nexedi Edition | About GitLab | About Nexedi | 沪ICP备2021021310号-2 | 沪ICP备2021021310号-7