Commit 322aafa6 authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'x86-mrst-for-linus' of...

Merge branch 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip

* 'x86-mrst-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/linux-2.6-tip: (30 commits)
  x86, mrst: Fix whitespace breakage in apb_timer.c
  x86, mrst: Fix APB timer per cpu clockevent
  x86, mrst: Remove X86_MRST dependency on PCI_IOAPIC
  x86, olpc: Use pci subarch init for OLPC
  x86, pci: Add arch_init to x86_init abstraction
  x86, mrst: Add Kconfig dependencies for Moorestown
  x86, pci: Exclude Moorestown PCI code if CONFIG_X86_MRST=n
  x86, numaq: Make CONFIG_X86_NUMAQ depend on CONFIG_PCI
  x86, pci: Add sanity check for PCI fixed bar probing
  x86, legacy_irq: Remove duplicate vector assigment
  x86, legacy_irq: Remove left over nr_legacy_irqs
  x86, mrst: Platform clock setup code
  x86, apbt: Moorestown APB system timer driver
  x86, mrst: Add vrtc platform data setup code
  x86, mrst: Add platform timer info parsing code
  x86, mrst: Fill in PCI functions in x86_init layer
  x86, mrst: Add dummy legacy pic to platform setup
  x86/PCI: Moorestown PCI support
  x86, ioapic: Add dummy ioapic functions
  x86, ioapic: Early enable ioapic for timer irq
  ...

Fixed up semantic conflict of new clocksources due to commit
17622339 ("clocksource: add argument to resume callback").
parents dd04265b c7bbf52a
...@@ -2834,6 +2834,12 @@ and is between 256 and 4096 characters. It is defined in the file ...@@ -2834,6 +2834,12 @@ and is between 256 and 4096 characters. It is defined in the file
default x2apic cluster mode on platforms default x2apic cluster mode on platforms
supporting x2apic. supporting x2apic.
x86_mrst_timer= [X86-32,APBT]
Choose timer option for x86 Moorestown MID platform.
Two valid options are apbt timer only and lapic timer
plus one apbt timer for broadcast timer.
x86_mrst_timer=apbt_only | lapic_and_apbt
xd= [HW,XT] Original XT pre-IDE (RLL encoded) disks. xd= [HW,XT] Original XT pre-IDE (RLL encoded) disks.
xd_geo= See header of drivers/block/xd.c. xd_geo= See header of drivers/block/xd.c.
......
...@@ -393,8 +393,12 @@ config X86_ELAN ...@@ -393,8 +393,12 @@ config X86_ELAN
config X86_MRST config X86_MRST
bool "Moorestown MID platform" bool "Moorestown MID platform"
depends on PCI
depends on PCI_GOANY
depends on X86_32 depends on X86_32
depends on X86_EXTENDED_PLATFORM depends on X86_EXTENDED_PLATFORM
depends on X86_IO_APIC
select APB_TIMER
---help--- ---help---
Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin Moorestown is Intel's Low Power Intel Architecture (LPIA) based Moblin
Internet Device(MID) platform. Moorestown consists of two chips: Internet Device(MID) platform. Moorestown consists of two chips:
...@@ -429,6 +433,7 @@ config X86_32_NON_STANDARD ...@@ -429,6 +433,7 @@ config X86_32_NON_STANDARD
config X86_NUMAQ config X86_NUMAQ
bool "NUMAQ (IBM/Sequent)" bool "NUMAQ (IBM/Sequent)"
depends on X86_32_NON_STANDARD depends on X86_32_NON_STANDARD
depends on PCI
select NUMA select NUMA
select X86_MPPARSE select X86_MPPARSE
---help--- ---help---
...@@ -629,6 +634,16 @@ config HPET_EMULATE_RTC ...@@ -629,6 +634,16 @@ config HPET_EMULATE_RTC
def_bool y def_bool y
depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y) depends on HPET_TIMER && (RTC=y || RTC=m || RTC_DRV_CMOS=m || RTC_DRV_CMOS=y)
config APB_TIMER
def_bool y if MRST
prompt "Langwell APB Timer Support" if X86_MRST
help
APB timer is the replacement for 8254, HPET on X86 MID platforms.
The APBT provides a stable time base on SMP
systems, unlike the TSC, but it is more expensive to access,
as it is off-chip. APB timers are always running regardless of CPU
C states, they are used as per CPU clockevent device when possible.
# Mark as embedded because too many people got it wrong. # Mark as embedded because too many people got it wrong.
# The code disables itself when not needed. # The code disables itself when not needed.
config DMI config DMI
......
/*
* apb_timer.h: Driver for Langwell APB timer based on Synopsis DesignWare
*
* (C) Copyright 2009 Intel Corporation
* Author: Jacob Pan (jacob.jun.pan@intel.com)
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*
* Note:
*/
#ifndef ASM_X86_APBT_H
#define ASM_X86_APBT_H
#include <linux/sfi.h>
#ifdef CONFIG_APB_TIMER
/* Langwell DW APB timer registers */
#define APBTMR_N_LOAD_COUNT 0x00
#define APBTMR_N_CURRENT_VALUE 0x04
#define APBTMR_N_CONTROL 0x08
#define APBTMR_N_EOI 0x0c
#define APBTMR_N_INT_STATUS 0x10
#define APBTMRS_INT_STATUS 0xa0
#define APBTMRS_EOI 0xa4
#define APBTMRS_RAW_INT_STATUS 0xa8
#define APBTMRS_COMP_VERSION 0xac
#define APBTMRS_REG_SIZE 0x14
/* register bits */
#define APBTMR_CONTROL_ENABLE (1<<0)
#define APBTMR_CONTROL_MODE_PERIODIC (1<<1) /*1: periodic 0:free running */
#define APBTMR_CONTROL_INT (1<<2)
/* default memory mapped register base */
#define LNW_SCU_ADDR 0xFF100000
#define LNW_EXT_TIMER_OFFSET 0x1B800
#define APBT_DEFAULT_BASE (LNW_SCU_ADDR+LNW_EXT_TIMER_OFFSET)
#define LNW_EXT_TIMER_PGOFFSET 0x800
/* APBT clock speed range from PCLK to fabric base, 25-100MHz */
#define APBT_MAX_FREQ 50
#define APBT_MIN_FREQ 1
#define APBT_MMAP_SIZE 1024
#define APBT_DEV_USED 1
extern void apbt_time_init(void);
extern struct clock_event_device *global_clock_event;
extern unsigned long apbt_quick_calibrate(void);
extern int arch_setup_apbt_irqs(int irq, int trigger, int mask, int cpu);
extern void apbt_setup_secondary_clock(void);
extern unsigned int boot_cpu_id;
extern int disable_apbt_percpu;
extern struct sfi_timer_table_entry *sfi_get_mtmr(int hint);
extern void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr);
extern int sfi_mtimer_num;
#else /* CONFIG_APB_TIMER */
static inline unsigned long apbt_quick_calibrate(void) {return 0; }
static inline void apbt_time_init(void) {return 0; }
#endif
#endif /* ASM_X86_APBT_H */
...@@ -53,13 +53,6 @@ extern void threshold_interrupt(void); ...@@ -53,13 +53,6 @@ extern void threshold_interrupt(void);
extern void call_function_interrupt(void); extern void call_function_interrupt(void);
extern void call_function_single_interrupt(void); extern void call_function_single_interrupt(void);
/* PIC specific functions */
extern void disable_8259A_irq(unsigned int irq);
extern void enable_8259A_irq(unsigned int irq);
extern int i8259A_irq_pending(unsigned int irq);
extern void make_8259A_irq(unsigned int irq);
extern void init_8259A(int aeoi);
/* IOAPIC */ /* IOAPIC */
#define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs)) #define IO_APIC_IRQ(x) (((x) >= NR_IRQS_LEGACY) || ((1<<(x)) & io_apic_irqs))
extern unsigned long io_apic_irqs; extern unsigned long io_apic_irqs;
......
...@@ -26,11 +26,6 @@ extern unsigned int cached_irq_mask; ...@@ -26,11 +26,6 @@ extern unsigned int cached_irq_mask;
extern raw_spinlock_t i8259A_lock; extern raw_spinlock_t i8259A_lock;
extern void init_8259A(int auto_eoi);
extern void enable_8259A_irq(unsigned int irq);
extern void disable_8259A_irq(unsigned int irq);
extern unsigned int startup_8259A_irq(unsigned int irq);
/* the PIC may need a careful delay on some platforms, hence specific calls */ /* the PIC may need a careful delay on some platforms, hence specific calls */
static inline unsigned char inb_pic(unsigned int port) static inline unsigned char inb_pic(unsigned int port)
{ {
...@@ -57,7 +52,17 @@ static inline void outb_pic(unsigned char value, unsigned int port) ...@@ -57,7 +52,17 @@ static inline void outb_pic(unsigned char value, unsigned int port)
extern struct irq_chip i8259A_chip; extern struct irq_chip i8259A_chip;
extern void mask_8259A(void); struct legacy_pic {
extern void unmask_8259A(void); int nr_legacy_irqs;
struct irq_chip *chip;
void (*mask_all)(void);
void (*restore_mask)(void);
void (*init)(int auto_eoi);
int (*irq_pending)(unsigned int irq);
void (*make_irq)(unsigned int irq);
};
extern struct legacy_pic *legacy_pic;
extern struct legacy_pic null_legacy_pic;
#endif /* _ASM_X86_I8259_H */ #endif /* _ASM_X86_I8259_H */
...@@ -143,8 +143,6 @@ extern int noioapicreroute; ...@@ -143,8 +143,6 @@ extern int noioapicreroute;
/* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */ /* 1 if the timer IRQ uses the '8259A Virtual Wire' mode */
extern int timer_through_8259; extern int timer_through_8259;
extern void io_apic_disable_legacy(void);
/* /*
* If we use the IO-APIC for IRQ routing, disable automatic * If we use the IO-APIC for IRQ routing, disable automatic
* assignment of PCI IRQ's. * assignment of PCI IRQ's.
...@@ -189,6 +187,7 @@ extern struct mp_ioapic_gsi mp_gsi_routing[]; ...@@ -189,6 +187,7 @@ extern struct mp_ioapic_gsi mp_gsi_routing[];
int mp_find_ioapic(int gsi); int mp_find_ioapic(int gsi);
int mp_find_ioapic_pin(int ioapic, int gsi); int mp_find_ioapic_pin(int ioapic, int gsi);
void __init mp_register_ioapic(int id, u32 address, u32 gsi_base); void __init mp_register_ioapic(int id, u32 address, u32 gsi_base);
extern void __init pre_init_apic_IRQ0(void);
#else /* !CONFIG_X86_IO_APIC */ #else /* !CONFIG_X86_IO_APIC */
...@@ -198,7 +197,11 @@ static const int timer_through_8259 = 0; ...@@ -198,7 +197,11 @@ static const int timer_through_8259 = 0;
static inline void ioapic_init_mappings(void) { } static inline void ioapic_init_mappings(void) { }
static inline void ioapic_insert_resources(void) { } static inline void ioapic_insert_resources(void) { }
static inline void probe_nr_irqs_gsi(void) { } static inline void probe_nr_irqs_gsi(void) { }
static inline int mp_find_ioapic(int gsi) { return 0; }
struct io_apic_irq_attr;
static inline int io_apic_set_pci_routing(struct device *dev, int irq,
struct io_apic_irq_attr *irq_attr) { return 0; }
#endif #endif
#endif /* _ASM_X86_IO_APIC_H */ #endif /* _ASM_X86_IO_APIC_H */
...@@ -48,6 +48,5 @@ extern DECLARE_BITMAP(used_vectors, NR_VECTORS); ...@@ -48,6 +48,5 @@ extern DECLARE_BITMAP(used_vectors, NR_VECTORS);
extern int vector_used_by_percpu_irq(unsigned int vector); extern int vector_used_by_percpu_irq(unsigned int vector);
extern void init_ISA_irqs(void); extern void init_ISA_irqs(void);
extern int nr_legacy_irqs;
#endif /* _ASM_X86_IRQ_H */ #endif /* _ASM_X86_IRQ_H */
/*
* mrst.h: Intel Moorestown platform specific setup code
*
* (C) Copyright 2009 Intel Corporation
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* as published by the Free Software Foundation; version 2
* of the License.
*/
#ifndef _ASM_X86_MRST_H
#define _ASM_X86_MRST_H
extern int pci_mrst_init(void);
int __init sfi_parse_mrtc(struct sfi_table_header *table);
#define SFI_MTMR_MAX_NUM 8
#define SFI_MRTC_MAX 8
#endif /* _ASM_X86_MRST_H */
...@@ -30,6 +30,7 @@ ...@@ -30,6 +30,7 @@
extern int found_numaq; extern int found_numaq;
extern int get_memcfg_numaq(void); extern int get_memcfg_numaq(void);
extern int pci_numaq_init(void);
extern void *xquad_portio; extern void *xquad_portio;
......
...@@ -13,7 +13,6 @@ struct olpc_platform_t { ...@@ -13,7 +13,6 @@ struct olpc_platform_t {
#define OLPC_F_PRESENT 0x01 #define OLPC_F_PRESENT 0x01
#define OLPC_F_DCON 0x02 #define OLPC_F_DCON 0x02
#define OLPC_F_VSA 0x04
#ifdef CONFIG_OLPC #ifdef CONFIG_OLPC
...@@ -50,18 +49,6 @@ static inline int olpc_has_dcon(void) ...@@ -50,18 +49,6 @@ static inline int olpc_has_dcon(void)
return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0; return (olpc_platform_info.flags & OLPC_F_DCON) ? 1 : 0;
} }
/*
* The VSA is software from AMD that typical Geode bioses will include.
* It is used to emulate the PCI bus, VGA, etc. OLPC's Open Firmware does
* not include the VSA; instead, PCI is emulated by the kernel.
*
* The VSA is described further in arch/x86/pci/olpc.c.
*/
static inline int olpc_has_vsa(void)
{
return (olpc_platform_info.flags & OLPC_F_VSA) ? 1 : 0;
}
/* /*
* The "Mass Production" version of OLPC's XO is identified as being model * The "Mass Production" version of OLPC's XO is identified as being model
* C2. During the prototype phase, the following models (in chronological * C2. During the prototype phase, the following models (in chronological
...@@ -87,13 +74,10 @@ static inline int olpc_has_dcon(void) ...@@ -87,13 +74,10 @@ static inline int olpc_has_dcon(void)
return 0; return 0;
} }
static inline int olpc_has_vsa(void)
{
return 0;
}
#endif #endif
extern int pci_olpc_init(void);
/* EC related functions */ /* EC related functions */
extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen, extern int olpc_ec_cmd(unsigned char cmd, unsigned char *inbuf, size_t inlen,
......
...@@ -45,8 +45,15 @@ static inline int pci_proc_domain(struct pci_bus *bus) ...@@ -45,8 +45,15 @@ static inline int pci_proc_domain(struct pci_bus *bus)
#ifdef CONFIG_PCI #ifdef CONFIG_PCI
extern unsigned int pcibios_assign_all_busses(void); extern unsigned int pcibios_assign_all_busses(void);
extern int pci_legacy_init(void);
# ifdef CONFIG_ACPI
# define x86_default_pci_init pci_acpi_init
# else
# define x86_default_pci_init pci_legacy_init
# endif
#else #else
#define pcibios_assign_all_busses() 0 # define pcibios_assign_all_busses() 0
# define x86_default_pci_init NULL
#endif #endif
extern unsigned long pci_mem_start; extern unsigned long pci_mem_start;
......
...@@ -83,7 +83,6 @@ struct irq_routing_table { ...@@ -83,7 +83,6 @@ struct irq_routing_table {
extern unsigned int pcibios_irq_mask; extern unsigned int pcibios_irq_mask;
extern int pcibios_scanned;
extern spinlock_t pci_config_lock; extern spinlock_t pci_config_lock;
extern int (*pcibios_enable_irq)(struct pci_dev *dev); extern int (*pcibios_enable_irq)(struct pci_dev *dev);
...@@ -106,16 +105,15 @@ extern bool port_cf9_safe; ...@@ -106,16 +105,15 @@ extern bool port_cf9_safe;
extern int pci_direct_probe(void); extern int pci_direct_probe(void);
extern void pci_direct_init(int type); extern void pci_direct_init(int type);
extern void pci_pcbios_init(void); extern void pci_pcbios_init(void);
extern int pci_olpc_init(void);
extern void __init dmi_check_pciprobe(void); extern void __init dmi_check_pciprobe(void);
extern void __init dmi_check_skip_isa_align(void); extern void __init dmi_check_skip_isa_align(void);
/* some common used subsys_initcalls */ /* some common used subsys_initcalls */
extern int __init pci_acpi_init(void); extern int __init pci_acpi_init(void);
extern int __init pcibios_irq_init(void); extern void __init pcibios_irq_init(void);
extern int __init pci_visws_init(void);
extern int __init pci_numaq_init(void);
extern int __init pcibios_init(void); extern int __init pcibios_init(void);
extern int pci_legacy_init(void);
extern void pcibios_fixup_irqs(void);
/* pci-mmconfig.c */ /* pci-mmconfig.c */
...@@ -183,3 +181,17 @@ static inline void mmio_config_writel(void __iomem *pos, u32 val) ...@@ -183,3 +181,17 @@ static inline void mmio_config_writel(void __iomem *pos, u32 val)
{ {
asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory"); asm volatile("movl %%eax,(%1)" : : "a" (val), "r" (pos) : "memory");
} }
#ifdef CONFIG_PCI
# ifdef CONFIG_ACPI
# define x86_default_pci_init pci_acpi_init
# else
# define x86_default_pci_init pci_legacy_init
# endif
# define x86_default_pci_init_irq pcibios_irq_init
# define x86_default_pci_fixup_irqs pcibios_fixup_irqs
#else
# define x86_default_pci_init NULL
# define x86_default_pci_init_irq NULL
# define x86_default_pci_fixup_irqs NULL
#endif
...@@ -37,10 +37,8 @@ void setup_bios_corruption_check(void); ...@@ -37,10 +37,8 @@ void setup_bios_corruption_check(void);
#ifdef CONFIG_X86_VISWS #ifdef CONFIG_X86_VISWS
extern void visws_early_detect(void); extern void visws_early_detect(void);
extern int is_visws_box(void);
#else #else
static inline void visws_early_detect(void) { } static inline void visws_early_detect(void) { }
static inline int is_visws_box(void) { return 0; }
#endif #endif
extern unsigned long saved_video_mode; extern unsigned long saved_video_mode;
......
...@@ -122,4 +122,6 @@ extern char visws_board_type; ...@@ -122,4 +122,6 @@ extern char visws_board_type;
extern char visws_board_rev; extern char visws_board_rev;
extern int pci_visws_init(void);
#endif /* _ASM_X86_VISWS_COBALT_H */ #endif /* _ASM_X86_VISWS_COBALT_H */
...@@ -98,6 +98,20 @@ struct x86_init_iommu { ...@@ -98,6 +98,20 @@ struct x86_init_iommu {
int (*iommu_init)(void); int (*iommu_init)(void);
}; };
/**
* struct x86_init_pci - platform specific pci init functions
* @arch_init: platform specific pci arch init call
* @init: platform specific pci subsystem init
* @init_irq: platform specific pci irq init
* @fixup_irqs: platform specific pci irq fixup
*/
struct x86_init_pci {
int (*arch_init)(void);
int (*init)(void);
void (*init_irq)(void);
void (*fixup_irqs)(void);
};
/** /**
* struct x86_init_ops - functions for platform specific setup * struct x86_init_ops - functions for platform specific setup
* *
...@@ -110,6 +124,7 @@ struct x86_init_ops { ...@@ -110,6 +124,7 @@ struct x86_init_ops {
struct x86_init_paging paging; struct x86_init_paging paging;
struct x86_init_timers timers; struct x86_init_timers timers;
struct x86_init_iommu iommu; struct x86_init_iommu iommu;
struct x86_init_pci pci;
}; };
/** /**
......
...@@ -87,6 +87,7 @@ obj-$(CONFIG_VM86) += vm86_32.o ...@@ -87,6 +87,7 @@ obj-$(CONFIG_VM86) += vm86_32.o
obj-$(CONFIG_EARLY_PRINTK) += early_printk.o obj-$(CONFIG_EARLY_PRINTK) += early_printk.o
obj-$(CONFIG_HPET_TIMER) += hpet.o obj-$(CONFIG_HPET_TIMER) += hpet.o
obj-$(CONFIG_APB_TIMER) += apb_timer.o
obj-$(CONFIG_K8_NB) += k8.o obj-$(CONFIG_K8_NB) += k8.o
obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o obj-$(CONFIG_DEBUG_RODATA_TEST) += test_rodata.o
......
...@@ -35,6 +35,7 @@ ...@@ -35,6 +35,7 @@
#include <linux/ioport.h> #include <linux/ioport.h>
#include <linux/pci.h> #include <linux/pci.h>
#include <asm/pci_x86.h>
#include <asm/pgtable.h> #include <asm/pgtable.h>
#include <asm/io_apic.h> #include <asm/io_apic.h>
#include <asm/apic.h> #include <asm/apic.h>
...@@ -1624,6 +1625,9 @@ int __init acpi_boot_init(void) ...@@ -1624,6 +1625,9 @@ int __init acpi_boot_init(void)
acpi_table_parse(ACPI_SIG_HPET, acpi_parse_hpet); acpi_table_parse(ACPI_SIG_HPET, acpi_parse_hpet);
if (!acpi_noirq)
x86_init.pci.init = pci_acpi_init;
return 0; return 0;
} }
......
This diff is collapsed.
...@@ -1390,7 +1390,7 @@ void __init enable_IR_x2apic(void) ...@@ -1390,7 +1390,7 @@ void __init enable_IR_x2apic(void)
} }
local_irq_save(flags); local_irq_save(flags);
mask_8259A(); legacy_pic->mask_all();
mask_IO_APIC_setup(ioapic_entries); mask_IO_APIC_setup(ioapic_entries);
if (dmar_table_init_ret) if (dmar_table_init_ret)
...@@ -1422,7 +1422,7 @@ void __init enable_IR_x2apic(void) ...@@ -1422,7 +1422,7 @@ void __init enable_IR_x2apic(void)
nox2apic: nox2apic:
if (!ret) /* IR enabling failed */ if (!ret) /* IR enabling failed */
restore_IO_APIC_setup(ioapic_entries); restore_IO_APIC_setup(ioapic_entries);
unmask_8259A(); legacy_pic->restore_mask();
local_irq_restore(flags); local_irq_restore(flags);
out: out:
...@@ -2018,7 +2018,7 @@ static int lapic_resume(struct sys_device *dev) ...@@ -2018,7 +2018,7 @@ static int lapic_resume(struct sys_device *dev)
} }
mask_IO_APIC_setup(ioapic_entries); mask_IO_APIC_setup(ioapic_entries);
mask_8259A(); legacy_pic->mask_all();
} }
if (x2apic_mode) if (x2apic_mode)
...@@ -2062,7 +2062,7 @@ static int lapic_resume(struct sys_device *dev) ...@@ -2062,7 +2062,7 @@ static int lapic_resume(struct sys_device *dev)
if (intr_remapping_enabled) { if (intr_remapping_enabled) {
reenable_intr_remapping(x2apic_mode); reenable_intr_remapping(x2apic_mode);
unmask_8259A(); legacy_pic->restore_mask();
restore_IO_APIC_setup(ioapic_entries); restore_IO_APIC_setup(ioapic_entries);
free_ioapic_entries(ioapic_entries); free_ioapic_entries(ioapic_entries);
} }
......
...@@ -143,12 +143,6 @@ static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY]; ...@@ -143,12 +143,6 @@ static struct irq_cfg irq_cfgx[NR_IRQS_LEGACY];
static struct irq_cfg irq_cfgx[NR_IRQS]; static struct irq_cfg irq_cfgx[NR_IRQS];
#endif #endif
void __init io_apic_disable_legacy(void)
{
nr_legacy_irqs = 0;
nr_irqs_gsi = 0;
}
int __init arch_early_irq_init(void) int __init arch_early_irq_init(void)
{ {
struct irq_cfg *cfg; struct irq_cfg *cfg;
...@@ -157,6 +151,11 @@ int __init arch_early_irq_init(void) ...@@ -157,6 +151,11 @@ int __init arch_early_irq_init(void)
int node; int node;
int i; int i;
if (!legacy_pic->nr_legacy_irqs) {
nr_irqs_gsi = 0;
io_apic_irqs = ~0UL;
}
cfg = irq_cfgx; cfg = irq_cfgx;
count = ARRAY_SIZE(irq_cfgx); count = ARRAY_SIZE(irq_cfgx);
node= cpu_to_node(boot_cpu_id); node= cpu_to_node(boot_cpu_id);
...@@ -170,7 +169,7 @@ int __init arch_early_irq_init(void) ...@@ -170,7 +169,7 @@ int __init arch_early_irq_init(void)
* For legacy IRQ's, start with assigning irq0 to irq15 to * For legacy IRQ's, start with assigning irq0 to irq15 to
* IRQ0_VECTOR to IRQ15_VECTOR on cpu 0. * IRQ0_VECTOR to IRQ15_VECTOR on cpu 0.
*/ */
if (i < nr_legacy_irqs) { if (i < legacy_pic->nr_legacy_irqs) {
cfg[i].vector = IRQ0_VECTOR + i; cfg[i].vector = IRQ0_VECTOR + i;
cpumask_set_cpu(0, cfg[i].domain); cpumask_set_cpu(0, cfg[i].domain);
} }
...@@ -852,7 +851,7 @@ static int __init find_isa_irq_apic(int irq, int type) ...@@ -852,7 +851,7 @@ static int __init find_isa_irq_apic(int irq, int type)
*/ */
static int EISA_ELCR(unsigned int irq) static int EISA_ELCR(unsigned int irq)
{ {
if (irq < nr_legacy_irqs) { if (irq < legacy_pic->nr_legacy_irqs) {
unsigned int port = 0x4d0 + (irq >> 3); unsigned int port = 0x4d0 + (irq >> 3);
return (inb(port) >> (irq & 7)) & 1; return (inb(port) >> (irq & 7)) & 1;
} }
...@@ -1439,7 +1438,7 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq ...@@ -1439,7 +1438,7 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq
* controllers like 8259. Now that IO-APIC can handle this irq, update * controllers like 8259. Now that IO-APIC can handle this irq, update
* the cfg->domain. * the cfg->domain.
*/ */
if (irq < nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain)) if (irq < legacy_pic->nr_legacy_irqs && cpumask_test_cpu(0, cfg->domain))
apic->vector_allocation_domain(0, cfg->domain); apic->vector_allocation_domain(0, cfg->domain);
if (assign_irq_vector(irq, cfg, apic->target_cpus())) if (assign_irq_vector(irq, cfg, apic->target_cpus()))
...@@ -1463,8 +1462,8 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq ...@@ -1463,8 +1462,8 @@ static void setup_IO_APIC_irq(int apic_id, int pin, unsigned int irq, struct irq
} }
ioapic_register_intr(irq, desc, trigger); ioapic_register_intr(irq, desc, trigger);
if (irq < nr_legacy_irqs) if (irq < legacy_pic->nr_legacy_irqs)
disable_8259A_irq(irq); legacy_pic->chip->mask(irq);
ioapic_write_entry(apic_id, pin, entry); ioapic_write_entry(apic_id, pin, entry);
} }
...@@ -1873,7 +1872,7 @@ __apicdebuginit(void) print_PIC(void) ...@@ -1873,7 +1872,7 @@ __apicdebuginit(void) print_PIC(void)
unsigned int v; unsigned int v;
unsigned long flags; unsigned long flags;
if (!nr_legacy_irqs) if (!legacy_pic->nr_legacy_irqs)
return; return;
printk(KERN_DEBUG "\nprinting PIC contents\n"); printk(KERN_DEBUG "\nprinting PIC contents\n");
...@@ -1957,7 +1956,7 @@ void __init enable_IO_APIC(void) ...@@ -1957,7 +1956,7 @@ void __init enable_IO_APIC(void)
nr_ioapic_registers[apic] = reg_01.bits.entries+1; nr_ioapic_registers[apic] = reg_01.bits.entries+1;
} }
if (!nr_legacy_irqs) if (!legacy_pic->nr_legacy_irqs)
return; return;
for(apic = 0; apic < nr_ioapics; apic++) { for(apic = 0; apic < nr_ioapics; apic++) {
...@@ -2014,7 +2013,7 @@ void disable_IO_APIC(void) ...@@ -2014,7 +2013,7 @@ void disable_IO_APIC(void)
*/ */
clear_IO_APIC(); clear_IO_APIC();
if (!nr_legacy_irqs) if (!legacy_pic->nr_legacy_irqs)
return; return;
/* /*
...@@ -2247,9 +2246,9 @@ static unsigned int startup_ioapic_irq(unsigned int irq) ...@@ -2247,9 +2246,9 @@ static unsigned int startup_ioapic_irq(unsigned int irq)
struct irq_cfg *cfg; struct irq_cfg *cfg;
raw_spin_lock_irqsave(&ioapic_lock, flags); raw_spin_lock_irqsave(&ioapic_lock, flags);
if (irq < nr_legacy_irqs) { if (irq < legacy_pic->nr_legacy_irqs) {
disable_8259A_irq(irq); legacy_pic->chip->mask(irq);
if (i8259A_irq_pending(irq)) if (legacy_pic->irq_pending(irq))
was_pending = 1; was_pending = 1;
} }
cfg = irq_cfg(irq); cfg = irq_cfg(irq);
...@@ -2782,8 +2781,8 @@ static inline void init_IO_APIC_traps(void) ...@@ -2782,8 +2781,8 @@ static inline void init_IO_APIC_traps(void)
* so default to an old-fashioned 8259 * so default to an old-fashioned 8259
* interrupt if we can.. * interrupt if we can..
*/ */
if (irq < nr_legacy_irqs) if (irq < legacy_pic->nr_legacy_irqs)
make_8259A_irq(irq); legacy_pic->make_irq(irq);
else else
/* Strange. Oh, well.. */ /* Strange. Oh, well.. */
desc->chip = &no_irq_chip; desc->chip = &no_irq_chip;
...@@ -2940,7 +2939,7 @@ static inline void __init check_timer(void) ...@@ -2940,7 +2939,7 @@ static inline void __init check_timer(void)
/* /*
* get/set the timer IRQ vector: * get/set the timer IRQ vector:
*/ */
disable_8259A_irq(0); legacy_pic->chip->mask(0);
assign_irq_vector(0, cfg, apic->target_cpus()); assign_irq_vector(0, cfg, apic->target_cpus());
/* /*
...@@ -2953,7 +2952,7 @@ static inline void __init check_timer(void) ...@@ -2953,7 +2952,7 @@ static inline void __init check_timer(void)
* automatically. * automatically.
*/ */
apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_EXTINT);
init_8259A(1); legacy_pic->init(1);
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
{ {
unsigned int ver; unsigned int ver;
...@@ -3012,7 +3011,7 @@ static inline void __init check_timer(void) ...@@ -3012,7 +3011,7 @@ static inline void __init check_timer(void)
if (timer_irq_works()) { if (timer_irq_works()) {
if (nmi_watchdog == NMI_IO_APIC) { if (nmi_watchdog == NMI_IO_APIC) {
setup_nmi(); setup_nmi();
enable_8259A_irq(0); legacy_pic->chip->unmask(0);
} }
if (disable_timer_pin_1 > 0) if (disable_timer_pin_1 > 0)
clear_IO_APIC_pin(0, pin1); clear_IO_APIC_pin(0, pin1);
...@@ -3035,14 +3034,14 @@ static inline void __init check_timer(void) ...@@ -3035,14 +3034,14 @@ static inline void __init check_timer(void)
*/ */
replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2); replace_pin_at_irq_node(cfg, node, apic1, pin1, apic2, pin2);
setup_timer_IRQ0_pin(apic2, pin2, cfg->vector); setup_timer_IRQ0_pin(apic2, pin2, cfg->vector);
enable_8259A_irq(0); legacy_pic->chip->unmask(0);
if (timer_irq_works()) { if (timer_irq_works()) {
apic_printk(APIC_QUIET, KERN_INFO "....... works.\n"); apic_printk(APIC_QUIET, KERN_INFO "....... works.\n");
timer_through_8259 = 1; timer_through_8259 = 1;
if (nmi_watchdog == NMI_IO_APIC) { if (nmi_watchdog == NMI_IO_APIC) {
disable_8259A_irq(0); legacy_pic->chip->mask(0);
setup_nmi(); setup_nmi();
enable_8259A_irq(0); legacy_pic->chip->unmask(0);
} }
goto out; goto out;
} }
...@@ -3050,7 +3049,7 @@ static inline void __init check_timer(void) ...@@ -3050,7 +3049,7 @@ static inline void __init check_timer(void)
* Cleanup, just in case ... * Cleanup, just in case ...
*/ */
local_irq_disable(); local_irq_disable();
disable_8259A_irq(0); legacy_pic->chip->mask(0);
clear_IO_APIC_pin(apic2, pin2); clear_IO_APIC_pin(apic2, pin2);
apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n"); apic_printk(APIC_QUIET, KERN_INFO "....... failed.\n");
} }
...@@ -3069,22 +3068,22 @@ static inline void __init check_timer(void) ...@@ -3069,22 +3068,22 @@ static inline void __init check_timer(void)
lapic_register_intr(0, desc); lapic_register_intr(0, desc);
apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */ apic_write(APIC_LVT0, APIC_DM_FIXED | cfg->vector); /* Fixed mode */
enable_8259A_irq(0); legacy_pic->chip->unmask(0);
if (timer_irq_works()) { if (timer_irq_works()) {
apic_printk(APIC_QUIET, KERN_INFO "..... works.\n"); apic_printk(APIC_QUIET, KERN_INFO "..... works.\n");
goto out; goto out;
} }
local_irq_disable(); local_irq_disable();
disable_8259A_irq(0); legacy_pic->chip->mask(0);
apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector); apic_write(APIC_LVT0, APIC_LVT_MASKED | APIC_DM_FIXED | cfg->vector);
apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n"); apic_printk(APIC_QUIET, KERN_INFO "..... failed.\n");
apic_printk(APIC_QUIET, KERN_INFO apic_printk(APIC_QUIET, KERN_INFO
"...trying to set up timer as ExtINT IRQ...\n"); "...trying to set up timer as ExtINT IRQ...\n");
init_8259A(0); legacy_pic->init(0);
make_8259A_irq(0); legacy_pic->make_irq(0);
apic_write(APIC_LVT0, APIC_DM_EXTINT); apic_write(APIC_LVT0, APIC_DM_EXTINT);
unlock_ExtINT_logic(); unlock_ExtINT_logic();
...@@ -3126,7 +3125,7 @@ void __init setup_IO_APIC(void) ...@@ -3126,7 +3125,7 @@ void __init setup_IO_APIC(void)
/* /*
* calling enable_IO_APIC() is moved to setup_local_APIC for BP * calling enable_IO_APIC() is moved to setup_local_APIC for BP
*/ */
io_apic_irqs = nr_legacy_irqs ? ~PIC_IRQS : ~0UL; io_apic_irqs = legacy_pic->nr_legacy_irqs ? ~PIC_IRQS : ~0UL;
apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n"); apic_printk(APIC_VERBOSE, "ENABLING IO-APIC IRQs\n");
/* /*
...@@ -3137,7 +3136,7 @@ void __init setup_IO_APIC(void) ...@@ -3137,7 +3136,7 @@ void __init setup_IO_APIC(void)
sync_Arb_IDs(); sync_Arb_IDs();
setup_IO_APIC_irqs(); setup_IO_APIC_irqs();
init_IO_APIC_traps(); init_IO_APIC_traps();
if (nr_legacy_irqs) if (legacy_pic->nr_legacy_irqs)
check_timer(); check_timer();
} }
...@@ -3928,7 +3927,7 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq, ...@@ -3928,7 +3927,7 @@ static int __io_apic_set_pci_routing(struct device *dev, int irq,
/* /*
* IRQs < 16 are already in the irq_2_pin[] map * IRQs < 16 are already in the irq_2_pin[] map
*/ */
if (irq >= nr_legacy_irqs) { if (irq >= legacy_pic->nr_legacy_irqs) {
cfg = desc->chip_data; cfg = desc->chip_data;
if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) { if (add_pin_to_irq_node_nopanic(cfg, node, ioapic, pin)) {
printk(KERN_INFO "can not add pin %d for irq %d\n", printk(KERN_INFO "can not add pin %d for irq %d\n",
...@@ -4302,3 +4301,24 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base) ...@@ -4302,3 +4301,24 @@ void __init mp_register_ioapic(int id, u32 address, u32 gsi_base)
nr_ioapics++; nr_ioapics++;
} }
/* Enable IOAPIC early just for system timer */
void __init pre_init_apic_IRQ0(void)
{
struct irq_cfg *cfg;
struct irq_desc *desc;
printk(KERN_INFO "Early APIC setup for system timer0\n");
#ifndef CONFIG_SMP
phys_cpu_present_map = physid_mask_of_physid(boot_cpu_physical_apicid);
#endif
desc = irq_to_desc_alloc_node(0, 0);
setup_local_APIC();
cfg = irq_cfg(0);
add_pin_to_irq_node(cfg, 0, 0, 0);
set_irq_chip_and_handler_name(0, &ioapic_chip, handle_edge_irq, "edge");
setup_IO_APIC_irq(0, 0, 0, desc, 0, 0);
}
...@@ -177,7 +177,7 @@ int __init check_nmi_watchdog(void) ...@@ -177,7 +177,7 @@ int __init check_nmi_watchdog(void)
error: error:
if (nmi_watchdog == NMI_IO_APIC) { if (nmi_watchdog == NMI_IO_APIC) {
if (!timer_through_8259) if (!timer_through_8259)
disable_8259A_irq(0); legacy_pic->chip->mask(0);
on_each_cpu(__acpi_nmi_disable, NULL, 1); on_each_cpu(__acpi_nmi_disable, NULL, 1);
} }
......
...@@ -277,6 +277,7 @@ static __init void early_check_numaq(void) ...@@ -277,6 +277,7 @@ static __init void early_check_numaq(void)
x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus; x86_init.mpparse.mpc_oem_pci_bus = mpc_oem_pci_bus;
x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info; x86_init.mpparse.mpc_oem_bus_info = mpc_oem_bus_info;
x86_init.timers.tsc_pre_init = numaq_tsc_init; x86_init.timers.tsc_pre_init = numaq_tsc_init;
x86_init.pci.init = pci_numaq_init;
} }
} }
......
...@@ -34,6 +34,12 @@ ...@@ -34,6 +34,12 @@
static int i8259A_auto_eoi; static int i8259A_auto_eoi;
DEFINE_RAW_SPINLOCK(i8259A_lock); DEFINE_RAW_SPINLOCK(i8259A_lock);
static void mask_and_ack_8259A(unsigned int); static void mask_and_ack_8259A(unsigned int);
static void mask_8259A(void);
static void unmask_8259A(void);
static void disable_8259A_irq(unsigned int irq);
static void enable_8259A_irq(unsigned int irq);
static void init_8259A(int auto_eoi);
static int i8259A_irq_pending(unsigned int irq);
struct irq_chip i8259A_chip = { struct irq_chip i8259A_chip = {
.name = "XT-PIC", .name = "XT-PIC",
...@@ -63,7 +69,7 @@ unsigned int cached_irq_mask = 0xffff; ...@@ -63,7 +69,7 @@ unsigned int cached_irq_mask = 0xffff;
*/ */
unsigned long io_apic_irqs; unsigned long io_apic_irqs;
void disable_8259A_irq(unsigned int irq) static void disable_8259A_irq(unsigned int irq)
{ {
unsigned int mask = 1 << irq; unsigned int mask = 1 << irq;
unsigned long flags; unsigned long flags;
...@@ -77,7 +83,7 @@ void disable_8259A_irq(unsigned int irq) ...@@ -77,7 +83,7 @@ void disable_8259A_irq(unsigned int irq)
raw_spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags);
} }
void enable_8259A_irq(unsigned int irq) static void enable_8259A_irq(unsigned int irq)
{ {
unsigned int mask = ~(1 << irq); unsigned int mask = ~(1 << irq);
unsigned long flags; unsigned long flags;
...@@ -91,7 +97,7 @@ void enable_8259A_irq(unsigned int irq) ...@@ -91,7 +97,7 @@ void enable_8259A_irq(unsigned int irq)
raw_spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags);
} }
int i8259A_irq_pending(unsigned int irq) static int i8259A_irq_pending(unsigned int irq)
{ {
unsigned int mask = 1<<irq; unsigned int mask = 1<<irq;
unsigned long flags; unsigned long flags;
...@@ -107,7 +113,7 @@ int i8259A_irq_pending(unsigned int irq) ...@@ -107,7 +113,7 @@ int i8259A_irq_pending(unsigned int irq)
return ret; return ret;
} }
void make_8259A_irq(unsigned int irq) static void make_8259A_irq(unsigned int irq)
{ {
disable_irq_nosync(irq); disable_irq_nosync(irq);
io_apic_irqs &= ~(1<<irq); io_apic_irqs &= ~(1<<irq);
...@@ -281,7 +287,7 @@ static int __init i8259A_init_sysfs(void) ...@@ -281,7 +287,7 @@ static int __init i8259A_init_sysfs(void)
device_initcall(i8259A_init_sysfs); device_initcall(i8259A_init_sysfs);
void mask_8259A(void) static void mask_8259A(void)
{ {
unsigned long flags; unsigned long flags;
...@@ -293,7 +299,7 @@ void mask_8259A(void) ...@@ -293,7 +299,7 @@ void mask_8259A(void)
raw_spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags);
} }
void unmask_8259A(void) static void unmask_8259A(void)
{ {
unsigned long flags; unsigned long flags;
...@@ -305,7 +311,7 @@ void unmask_8259A(void) ...@@ -305,7 +311,7 @@ void unmask_8259A(void)
raw_spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags);
} }
void init_8259A(int auto_eoi) static void init_8259A(int auto_eoi)
{ {
unsigned long flags; unsigned long flags;
...@@ -358,3 +364,47 @@ void init_8259A(int auto_eoi) ...@@ -358,3 +364,47 @@ void init_8259A(int auto_eoi)
raw_spin_unlock_irqrestore(&i8259A_lock, flags); raw_spin_unlock_irqrestore(&i8259A_lock, flags);
} }
/*
* make i8259 a driver so that we can select pic functions at run time. the goal
* is to make x86 binary compatible among pc compatible and non-pc compatible
* platforms, such as x86 MID.
*/
static void legacy_pic_noop(void) { };
static void legacy_pic_uint_noop(unsigned int unused) { };
static void legacy_pic_int_noop(int unused) { };
static struct irq_chip dummy_pic_chip = {
.name = "dummy pic",
.mask = legacy_pic_uint_noop,
.unmask = legacy_pic_uint_noop,
.disable = legacy_pic_uint_noop,
.mask_ack = legacy_pic_uint_noop,
};
static int legacy_pic_irq_pending_noop(unsigned int irq)
{
return 0;
}
struct legacy_pic null_legacy_pic = {
.nr_legacy_irqs = 0,
.chip = &dummy_pic_chip,
.mask_all = legacy_pic_noop,
.restore_mask = legacy_pic_noop,
.init = legacy_pic_int_noop,
.irq_pending = legacy_pic_irq_pending_noop,
.make_irq = legacy_pic_uint_noop,
};
struct legacy_pic default_legacy_pic = {
.nr_legacy_irqs = NR_IRQS_LEGACY,
.chip = &i8259A_chip,
.mask_all = mask_8259A,
.restore_mask = unmask_8259A,
.init = init_8259A,
.irq_pending = i8259A_irq_pending,
.make_irq = make_8259A_irq,
};
struct legacy_pic *legacy_pic = &default_legacy_pic;
...@@ -99,9 +99,6 @@ int vector_used_by_percpu_irq(unsigned int vector) ...@@ -99,9 +99,6 @@ int vector_used_by_percpu_irq(unsigned int vector)
return 0; return 0;
} }
/* Number of legacy interrupts */
int nr_legacy_irqs __read_mostly = NR_IRQS_LEGACY;
void __init init_ISA_irqs(void) void __init init_ISA_irqs(void)
{ {
int i; int i;
...@@ -109,12 +106,12 @@ void __init init_ISA_irqs(void) ...@@ -109,12 +106,12 @@ void __init init_ISA_irqs(void)
#if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC) #if defined(CONFIG_X86_64) || defined(CONFIG_X86_LOCAL_APIC)
init_bsp_APIC(); init_bsp_APIC();
#endif #endif
init_8259A(0); legacy_pic->init(0);
/* /*
* 16 old-style INTA-cycle interrupts: * 16 old-style INTA-cycle interrupts:
*/ */
for (i = 0; i < NR_IRQS_LEGACY; i++) { for (i = 0; i < legacy_pic->nr_legacy_irqs; i++) {
struct irq_desc *desc = irq_to_desc(i); struct irq_desc *desc = irq_to_desc(i);
desc->status = IRQ_DISABLED; desc->status = IRQ_DISABLED;
...@@ -138,7 +135,7 @@ void __init init_IRQ(void) ...@@ -138,7 +135,7 @@ void __init init_IRQ(void)
* then this vector space can be freed and re-used dynamically as the * then this vector space can be freed and re-used dynamically as the
* irq's migrate etc. * irq's migrate etc.
*/ */
for (i = 0; i < nr_legacy_irqs; i++) for (i = 0; i < legacy_pic->nr_legacy_irqs; i++)
per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i; per_cpu(vector_irq, 0)[IRQ0_VECTOR + i] = i;
x86_init.irqs.intr_init(); x86_init.irqs.intr_init();
......
...@@ -10,8 +10,211 @@ ...@@ -10,8 +10,211 @@
* of the License. * of the License.
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/kernel.h>
#include <linux/sfi.h>
#include <linux/irq.h>
#include <linux/module.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/mpspec_def.h>
#include <asm/hw_irq.h>
#include <asm/apic.h>
#include <asm/io_apic.h>
#include <asm/mrst.h>
#include <asm/io.h>
#include <asm/i8259.h>
#include <asm/apb_timer.h>
static u32 sfi_mtimer_usage[SFI_MTMR_MAX_NUM];
static struct sfi_timer_table_entry sfi_mtimer_array[SFI_MTMR_MAX_NUM];
int sfi_mtimer_num;
struct sfi_rtc_table_entry sfi_mrtc_array[SFI_MRTC_MAX];
EXPORT_SYMBOL_GPL(sfi_mrtc_array);
int sfi_mrtc_num;
static inline void assign_to_mp_irq(struct mpc_intsrc *m,
struct mpc_intsrc *mp_irq)
{
memcpy(mp_irq, m, sizeof(struct mpc_intsrc));
}
static inline int mp_irq_cmp(struct mpc_intsrc *mp_irq,
struct mpc_intsrc *m)
{
return memcmp(mp_irq, m, sizeof(struct mpc_intsrc));
}
static void save_mp_irq(struct mpc_intsrc *m)
{
int i;
for (i = 0; i < mp_irq_entries; i++) {
if (!mp_irq_cmp(&mp_irqs[i], m))
return;
}
assign_to_mp_irq(m, &mp_irqs[mp_irq_entries]);
if (++mp_irq_entries == MAX_IRQ_SOURCES)
panic("Max # of irq sources exceeded!!\n");
}
/* parse all the mtimer info to a static mtimer array */
static int __init sfi_parse_mtmr(struct sfi_table_header *table)
{
struct sfi_table_simple *sb;
struct sfi_timer_table_entry *pentry;
struct mpc_intsrc mp_irq;
int totallen;
sb = (struct sfi_table_simple *)table;
if (!sfi_mtimer_num) {
sfi_mtimer_num = SFI_GET_NUM_ENTRIES(sb,
struct sfi_timer_table_entry);
pentry = (struct sfi_timer_table_entry *) sb->pentry;
totallen = sfi_mtimer_num * sizeof(*pentry);
memcpy(sfi_mtimer_array, pentry, totallen);
}
printk(KERN_INFO "SFI: MTIMER info (num = %d):\n", sfi_mtimer_num);
pentry = sfi_mtimer_array;
for (totallen = 0; totallen < sfi_mtimer_num; totallen++, pentry++) {
printk(KERN_INFO "timer[%d]: paddr = 0x%08x, freq = %dHz,"
" irq = %d\n", totallen, (u32)pentry->phys_addr,
pentry->freq_hz, pentry->irq);
if (!pentry->irq)
continue;
mp_irq.type = MP_IOAPIC;
mp_irq.irqtype = mp_INT;
/* triggering mode edge bit 2-3, active high polarity bit 0-1 */
mp_irq.irqflag = 5;
mp_irq.srcbus = 0;
mp_irq.srcbusirq = pentry->irq; /* IRQ */
mp_irq.dstapic = MP_APIC_ALL;
mp_irq.dstirq = pentry->irq;
save_mp_irq(&mp_irq);
}
return 0;
}
struct sfi_timer_table_entry *sfi_get_mtmr(int hint)
{
int i;
if (hint < sfi_mtimer_num) {
if (!sfi_mtimer_usage[hint]) {
pr_debug("hint taken for timer %d irq %d\n",\
hint, sfi_mtimer_array[hint].irq);
sfi_mtimer_usage[hint] = 1;
return &sfi_mtimer_array[hint];
}
}
/* take the first timer available */
for (i = 0; i < sfi_mtimer_num;) {
if (!sfi_mtimer_usage[i]) {
sfi_mtimer_usage[i] = 1;
return &sfi_mtimer_array[i];
}
i++;
}
return NULL;
}
void sfi_free_mtmr(struct sfi_timer_table_entry *mtmr)
{
int i;
for (i = 0; i < sfi_mtimer_num;) {
if (mtmr->irq == sfi_mtimer_array[i].irq) {
sfi_mtimer_usage[i] = 0;
return;
}
i++;
}
}
/* parse all the mrtc info to a global mrtc array */
int __init sfi_parse_mrtc(struct sfi_table_header *table)
{
struct sfi_table_simple *sb;
struct sfi_rtc_table_entry *pentry;
struct mpc_intsrc mp_irq;
int totallen;
sb = (struct sfi_table_simple *)table;
if (!sfi_mrtc_num) {
sfi_mrtc_num = SFI_GET_NUM_ENTRIES(sb,
struct sfi_rtc_table_entry);
pentry = (struct sfi_rtc_table_entry *)sb->pentry;
totallen = sfi_mrtc_num * sizeof(*pentry);
memcpy(sfi_mrtc_array, pentry, totallen);
}
printk(KERN_INFO "SFI: RTC info (num = %d):\n", sfi_mrtc_num);
pentry = sfi_mrtc_array;
for (totallen = 0; totallen < sfi_mrtc_num; totallen++, pentry++) {
printk(KERN_INFO "RTC[%d]: paddr = 0x%08x, irq = %d\n",
totallen, (u32)pentry->phys_addr, pentry->irq);
mp_irq.type = MP_IOAPIC;
mp_irq.irqtype = mp_INT;
mp_irq.irqflag = 0;
mp_irq.srcbus = 0;
mp_irq.srcbusirq = pentry->irq; /* IRQ */
mp_irq.dstapic = MP_APIC_ALL;
mp_irq.dstirq = pentry->irq;
save_mp_irq(&mp_irq);
}
return 0;
}
/*
* the secondary clock in Moorestown can be APBT or LAPIC clock, default to
* APBT but cmdline option can also override it.
*/
static void __cpuinit mrst_setup_secondary_clock(void)
{
/* restore default lapic clock if disabled by cmdline */
if (disable_apbt_percpu)
return setup_secondary_APIC_clock();
apbt_setup_secondary_clock();
}
static unsigned long __init mrst_calibrate_tsc(void)
{
unsigned long flags, fast_calibrate;
local_irq_save(flags);
fast_calibrate = apbt_quick_calibrate();
local_irq_restore(flags);
if (fast_calibrate)
return fast_calibrate;
return 0;
}
void __init mrst_time_init(void)
{
sfi_table_parse(SFI_SIG_MTMR, NULL, NULL, sfi_parse_mtmr);
pre_init_apic_IRQ0();
apbt_time_init();
}
void __init mrst_rtc_init(void)
{
sfi_table_parse(SFI_SIG_MRTC, NULL, NULL, sfi_parse_mrtc);
}
/*
* if we use per cpu apb timer, the bootclock already setup. if we use lapic
* timer and one apbt timer for broadcast, we need to set up lapic boot clock.
*/
static void __init mrst_setup_boot_clock(void)
{
pr_info("%s: per cpu apbt flag %d \n", __func__, disable_apbt_percpu);
if (disable_apbt_percpu)
setup_boot_APIC_clock();
};
/* /*
* Moorestown specific x86_init function overrides and early setup * Moorestown specific x86_init function overrides and early setup
...@@ -21,4 +224,17 @@ void __init x86_mrst_early_setup(void) ...@@ -21,4 +224,17 @@ void __init x86_mrst_early_setup(void)
{ {
x86_init.resources.probe_roms = x86_init_noop; x86_init.resources.probe_roms = x86_init_noop;
x86_init.resources.reserve_resources = x86_init_noop; x86_init.resources.reserve_resources = x86_init_noop;
x86_init.timers.timer_init = mrst_time_init;
x86_init.timers.setup_percpu_clockev = mrst_setup_boot_clock;
x86_init.irqs.pre_vector_init = x86_init_noop;
x86_cpuinit.setup_percpu_clockev = mrst_setup_secondary_clock;
x86_platform.calibrate_tsc = mrst_calibrate_tsc;
x86_init.pci.init = pci_mrst_init;
x86_init.pci.fixup_irqs = x86_init_noop;
legacy_pic = &null_legacy_pic;
} }
...@@ -17,7 +17,9 @@ ...@@ -17,7 +17,9 @@
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/string.h> #include <linux/string.h>
#include <asm/geode.h> #include <asm/geode.h>
#include <asm/setup.h>
#include <asm/olpc.h> #include <asm/olpc.h>
#ifdef CONFIG_OPEN_FIRMWARE #ifdef CONFIG_OPEN_FIRMWARE
...@@ -243,9 +245,11 @@ static int __init olpc_init(void) ...@@ -243,9 +245,11 @@ static int __init olpc_init(void)
olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0, olpc_ec_cmd(EC_FIRMWARE_REV, NULL, 0,
(unsigned char *) &olpc_platform_info.ecver, 1); (unsigned char *) &olpc_platform_info.ecver, 1);
/* check to see if the VSA exists */ #ifdef CONFIG_PCI_OLPC
if (cs5535_has_vsa2()) /* If the VSA exists let it emulate PCI, if not emulate in kernel */
olpc_platform_info.flags |= OLPC_F_VSA; if (!cs5535_has_vsa2())
x86_init.pci.arch_init = pci_olpc_init;
#endif
printk(KERN_INFO "OLPC board revision %s%X (EC=%x)\n", printk(KERN_INFO "OLPC board revision %s%X (EC=%x)\n",
((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "", ((olpc_platform_info.boardrev & 0xf) < 8) ? "pre" : "",
......
...@@ -48,6 +48,7 @@ ...@@ -48,6 +48,7 @@
#include <linux/err.h> #include <linux/err.h>
#include <linux/nmi.h> #include <linux/nmi.h>
#include <linux/tboot.h> #include <linux/tboot.h>
#include <linux/stackprotector.h>
#include <asm/acpi.h> #include <asm/acpi.h>
#include <asm/desc.h> #include <asm/desc.h>
...@@ -67,6 +68,7 @@ ...@@ -67,6 +68,7 @@
#include <linux/mc146818rtc.h> #include <linux/mc146818rtc.h>
#include <asm/smpboot_hooks.h> #include <asm/smpboot_hooks.h>
#include <asm/i8259.h>
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
u8 apicid_2_node[MAX_APICID]; u8 apicid_2_node[MAX_APICID];
...@@ -291,9 +293,9 @@ notrace static void __cpuinit start_secondary(void *unused) ...@@ -291,9 +293,9 @@ notrace static void __cpuinit start_secondary(void *unused)
check_tsc_sync_target(); check_tsc_sync_target();
if (nmi_watchdog == NMI_IO_APIC) { if (nmi_watchdog == NMI_IO_APIC) {
disable_8259A_irq(0); legacy_pic->chip->mask(0);
enable_NMI_through_LVT0(); enable_NMI_through_LVT0();
enable_8259A_irq(0); legacy_pic->chip->unmask(0);
} }
#ifdef CONFIG_X86_32 #ifdef CONFIG_X86_32
...@@ -329,6 +331,9 @@ notrace static void __cpuinit start_secondary(void *unused) ...@@ -329,6 +331,9 @@ notrace static void __cpuinit start_secondary(void *unused)
/* enable local interrupts */ /* enable local interrupts */
local_irq_enable(); local_irq_enable();
/* to prevent fake stack check failure in clock setup */
boot_init_stack_canary();
x86_cpuinit.setup_percpu_clockev(); x86_cpuinit.setup_percpu_clockev();
wmb(); wmb();
......
...@@ -49,11 +49,6 @@ extern int no_broadcast; ...@@ -49,11 +49,6 @@ extern int no_broadcast;
char visws_board_type = -1; char visws_board_type = -1;
char visws_board_rev = -1; char visws_board_rev = -1;
int is_visws_box(void)
{
return visws_board_type >= 0;
}
static void __init visws_time_init(void) static void __init visws_time_init(void)
{ {
printk(KERN_INFO "Starting Cobalt Timer system clock\n"); printk(KERN_INFO "Starting Cobalt Timer system clock\n");
...@@ -242,6 +237,8 @@ void __init visws_early_detect(void) ...@@ -242,6 +237,8 @@ void __init visws_early_detect(void)
x86_init.irqs.pre_vector_init = visws_pre_intr_init; x86_init.irqs.pre_vector_init = visws_pre_intr_init;
x86_init.irqs.trap_init = visws_trap_init; x86_init.irqs.trap_init = visws_trap_init;
x86_init.timers.timer_init = visws_time_init; x86_init.timers.timer_init = visws_time_init;
x86_init.pci.init = pci_visws_init;
x86_init.pci.init_irq = x86_init_noop;
/* /*
* Install reboot quirks: * Install reboot quirks:
...@@ -508,7 +505,7 @@ static struct irq_chip cobalt_irq_type = { ...@@ -508,7 +505,7 @@ static struct irq_chip cobalt_irq_type = {
*/ */
static unsigned int startup_piix4_master_irq(unsigned int irq) static unsigned int startup_piix4_master_irq(unsigned int irq)
{ {
init_8259A(0); legacy_pic->init(0);
return startup_cobalt_irq(irq); return startup_cobalt_irq(irq);
} }
...@@ -532,9 +529,6 @@ static struct irq_chip piix4_master_irq_type = { ...@@ -532,9 +529,6 @@ static struct irq_chip piix4_master_irq_type = {
static struct irq_chip piix4_virtual_irq_type = { static struct irq_chip piix4_virtual_irq_type = {
.name = "PIIX4-virtual", .name = "PIIX4-virtual",
.shutdown = disable_8259A_irq,
.enable = enable_8259A_irq,
.disable = disable_8259A_irq,
}; };
...@@ -609,7 +603,7 @@ static irqreturn_t piix4_master_intr(int irq, void *dev_id) ...@@ -609,7 +603,7 @@ static irqreturn_t piix4_master_intr(int irq, void *dev_id)
handle_IRQ_event(realirq, desc->action); handle_IRQ_event(realirq, desc->action);
if (!(desc->status & IRQ_DISABLED)) if (!(desc->status & IRQ_DISABLED))
enable_8259A_irq(realirq); legacy_pic->chip->unmask(realirq);
return IRQ_HANDLED; return IRQ_HANDLED;
...@@ -628,6 +622,12 @@ static struct irqaction cascade_action = { ...@@ -628,6 +622,12 @@ static struct irqaction cascade_action = {
.name = "cascade", .name = "cascade",
}; };
static inline void set_piix4_virtual_irq_type(void)
{
piix4_virtual_irq_type.shutdown = i8259A_chip.mask;
piix4_virtual_irq_type.enable = i8259A_chip.unmask;
piix4_virtual_irq_type.disable = i8259A_chip.mask;
}
void init_VISWS_APIC_irqs(void) void init_VISWS_APIC_irqs(void)
{ {
...@@ -653,6 +653,7 @@ void init_VISWS_APIC_irqs(void) ...@@ -653,6 +653,7 @@ void init_VISWS_APIC_irqs(void)
desc->chip = &piix4_master_irq_type; desc->chip = &piix4_master_irq_type;
} }
else if (i < CO_IRQ_APIC0) { else if (i < CO_IRQ_APIC0) {
set_piix4_virtual_irq_type();
desc->chip = &piix4_virtual_irq_type; desc->chip = &piix4_virtual_irq_type;
} }
else if (IS_CO_APIC(i)) { else if (IS_CO_APIC(i)) {
......
...@@ -4,9 +4,11 @@ ...@@ -4,9 +4,11 @@
* For licencing details see kernel-base/COPYING * For licencing details see kernel-base/COPYING
*/ */
#include <linux/init.h> #include <linux/init.h>
#include <linux/ioport.h>
#include <asm/bios_ebda.h> #include <asm/bios_ebda.h>
#include <asm/paravirt.h> #include <asm/paravirt.h>
#include <asm/pci_x86.h>
#include <asm/mpspec.h> #include <asm/mpspec.h>
#include <asm/setup.h> #include <asm/setup.h>
#include <asm/apic.h> #include <asm/apic.h>
...@@ -70,6 +72,12 @@ struct x86_init_ops x86_init __initdata = { ...@@ -70,6 +72,12 @@ struct x86_init_ops x86_init __initdata = {
.iommu = { .iommu = {
.iommu_init = iommu_init_noop, .iommu_init = iommu_init_noop,
}, },
.pci = {
.init = x86_default_pci_init,
.init_irq = x86_default_pci_init_irq,
.fixup_irqs = x86_default_pci_fixup_irqs,
},
}; };
struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = { struct x86_cpuinit_ops x86_cpuinit __cpuinitdata = {
......
...@@ -13,6 +13,8 @@ obj-$(CONFIG_X86_VISWS) += visws.o ...@@ -13,6 +13,8 @@ obj-$(CONFIG_X86_VISWS) += visws.o
obj-$(CONFIG_X86_NUMAQ) += numaq_32.o obj-$(CONFIG_X86_NUMAQ) += numaq_32.o
obj-$(CONFIG_X86_MRST) += mrst.o
obj-y += common.o early.o obj-y += common.o early.o
obj-y += amd_bus.o bus_numa.o obj-y += amd_bus.o bus_numa.o
......
...@@ -298,17 +298,14 @@ int __init pci_acpi_init(void) ...@@ -298,17 +298,14 @@ int __init pci_acpi_init(void)
{ {
struct pci_dev *dev = NULL; struct pci_dev *dev = NULL;
if (pcibios_scanned)
return 0;
if (acpi_noirq) if (acpi_noirq)
return 0; return -ENODEV;
printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n"); printk(KERN_INFO "PCI: Using ACPI for IRQ routing\n");
acpi_irq_penalty_init(); acpi_irq_penalty_init();
pcibios_scanned++;
pcibios_enable_irq = acpi_pci_irq_enable; pcibios_enable_irq = acpi_pci_irq_enable;
pcibios_disable_irq = acpi_pci_irq_disable; pcibios_disable_irq = acpi_pci_irq_disable;
x86_init.pci.init_irq = x86_init_noop;
if (pci_routeirq) { if (pci_routeirq) {
/* /*
......
...@@ -71,12 +71,6 @@ struct pci_ops pci_root_ops = { ...@@ -71,12 +71,6 @@ struct pci_ops pci_root_ops = {
.write = pci_write, .write = pci_write,
}; };
/*
* legacy, numa, and acpi all want to call pcibios_scan_root
* from their initcalls. This flag prevents that.
*/
int pcibios_scanned;
/* /*
* This interrupt-safe spinlock protects all accesses to PCI * This interrupt-safe spinlock protects all accesses to PCI
* configuration space. * configuration space.
......
#include <linux/pci.h> #include <linux/pci.h>
#include <linux/init.h> #include <linux/init.h>
#include <asm/pci_x86.h> #include <asm/pci_x86.h>
#include <asm/x86_init.h>
/* arch_initcall has too random ordering, so call the initializers /* arch_initcall has too random ordering, so call the initializers
in the right sequence from here. */ in the right sequence from here. */
...@@ -15,10 +16,9 @@ static __init int pci_arch_init(void) ...@@ -15,10 +16,9 @@ static __init int pci_arch_init(void)
if (!(pci_probe & PCI_PROBE_NOEARLY)) if (!(pci_probe & PCI_PROBE_NOEARLY))
pci_mmcfg_early_init(); pci_mmcfg_early_init();
#ifdef CONFIG_PCI_OLPC if (x86_init.pci.arch_init && !x86_init.pci.arch_init())
if (!pci_olpc_init()) return 0;
return 0; /* skip additional checks if it's an XO */
#endif
#ifdef CONFIG_PCI_BIOS #ifdef CONFIG_PCI_BIOS
pci_pcbios_init(); pci_pcbios_init();
#endif #endif
......
...@@ -53,7 +53,7 @@ struct irq_router_handler { ...@@ -53,7 +53,7 @@ struct irq_router_handler {
int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device); int (*probe)(struct irq_router *r, struct pci_dev *router, u16 device);
}; };
int (*pcibios_enable_irq)(struct pci_dev *dev) = NULL; int (*pcibios_enable_irq)(struct pci_dev *dev) = pirq_enable_irq;
void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL; void (*pcibios_disable_irq)(struct pci_dev *dev) = NULL;
/* /*
...@@ -1018,7 +1018,7 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign) ...@@ -1018,7 +1018,7 @@ static int pcibios_lookup_irq(struct pci_dev *dev, int assign)
return 1; return 1;
} }
static void __init pcibios_fixup_irqs(void) void __init pcibios_fixup_irqs(void)
{ {
struct pci_dev *dev = NULL; struct pci_dev *dev = NULL;
u8 pin; u8 pin;
...@@ -1112,12 +1112,12 @@ static struct dmi_system_id __initdata pciirq_dmi_table[] = { ...@@ -1112,12 +1112,12 @@ static struct dmi_system_id __initdata pciirq_dmi_table[] = {
{ } { }
}; };
int __init pcibios_irq_init(void) void __init pcibios_irq_init(void)
{ {
DBG(KERN_DEBUG "PCI: IRQ init\n"); DBG(KERN_DEBUG "PCI: IRQ init\n");
if (pcibios_enable_irq || raw_pci_ops == NULL) if (raw_pci_ops == NULL)
return 0; return;
dmi_check_system(pciirq_dmi_table); dmi_check_system(pciirq_dmi_table);
...@@ -1144,9 +1144,7 @@ int __init pcibios_irq_init(void) ...@@ -1144,9 +1144,7 @@ int __init pcibios_irq_init(void)
pirq_table = NULL; pirq_table = NULL;
} }
pcibios_enable_irq = pirq_enable_irq; x86_init.pci.fixup_irqs();
pcibios_fixup_irqs();
if (io_apic_assign_pci_irqs && pci_routeirq) { if (io_apic_assign_pci_irqs && pci_routeirq) {
struct pci_dev *dev = NULL; struct pci_dev *dev = NULL;
...@@ -1159,8 +1157,6 @@ int __init pcibios_irq_init(void) ...@@ -1159,8 +1157,6 @@ int __init pcibios_irq_init(void)
for_each_pci_dev(dev) for_each_pci_dev(dev)
pirq_enable_irq(dev); pirq_enable_irq(dev);
} }
return 0;
} }
static void pirq_penalize_isa_irq(int irq, int active) static void pirq_penalize_isa_irq(int irq, int active)
......
...@@ -35,16 +35,13 @@ static void __devinit pcibios_fixup_peer_bridges(void) ...@@ -35,16 +35,13 @@ static void __devinit pcibios_fixup_peer_bridges(void)
} }
} }
static int __init pci_legacy_init(void) int __init pci_legacy_init(void)
{ {
if (!raw_pci_ops) { if (!raw_pci_ops) {
printk("PCI: System does not support PCI\n"); printk("PCI: System does not support PCI\n");
return 0; return 0;
} }
if (pcibios_scanned++)
return 0;
printk("PCI: Probing PCI hardware\n"); printk("PCI: Probing PCI hardware\n");
pci_root_bus = pcibios_scan_root(0); pci_root_bus = pcibios_scan_root(0);
if (pci_root_bus) if (pci_root_bus)
...@@ -55,18 +52,15 @@ static int __init pci_legacy_init(void) ...@@ -55,18 +52,15 @@ static int __init pci_legacy_init(void)
int __init pci_subsys_init(void) int __init pci_subsys_init(void)
{ {
#ifdef CONFIG_X86_NUMAQ /*
pci_numaq_init(); * The init function returns an non zero value when
#endif * pci_legacy_init should be invoked.
#ifdef CONFIG_ACPI */
pci_acpi_init(); if (x86_init.pci.init())
#endif pci_legacy_init();
#ifdef CONFIG_X86_VISWS
pci_visws_init();
#endif
pci_legacy_init();
pcibios_fixup_peer_bridges(); pcibios_fixup_peer_bridges();
pcibios_irq_init(); x86_init.pci.init_irq();
pcibios_init(); pcibios_init();
return 0; return 0;
......
/*
* Moorestown PCI support
* Copyright (c) 2008 Intel Corporation
* Jesse Barnes <jesse.barnes@intel.com>
*
* Moorestown has an interesting PCI implementation:
* - configuration space is memory mapped (as defined by MCFG)
* - Lincroft devices also have a real, type 1 configuration space
* - Early Lincroft silicon has a type 1 access bug that will cause
* a hang if non-existent devices are accessed
* - some devices have the "fixed BAR" capability, which means
* they can't be relocated or modified; check for that during
* BAR sizing
*
* So, we use the MCFG space for all reads and writes, but also send
* Lincroft writes to type 1 space. But only read/write if the device
* actually exists, otherwise return all 1s for reads and bit bucket
* the writes.
*/
#include <linux/sched.h>
#include <linux/pci.h>
#include <linux/ioport.h>
#include <linux/init.h>
#include <linux/dmi.h>
#include <asm/acpi.h>
#include <asm/segment.h>
#include <asm/io.h>
#include <asm/smp.h>
#include <asm/pci_x86.h>
#include <asm/hw_irq.h>
#include <asm/io_apic.h>
#define PCIE_CAP_OFFSET 0x100
/* Fixed BAR fields */
#define PCIE_VNDR_CAP_ID_FIXED_BAR 0x00 /* Fixed BAR (TBD) */
#define PCI_FIXED_BAR_0_SIZE 0x04
#define PCI_FIXED_BAR_1_SIZE 0x08
#define PCI_FIXED_BAR_2_SIZE 0x0c
#define PCI_FIXED_BAR_3_SIZE 0x10
#define PCI_FIXED_BAR_4_SIZE 0x14
#define PCI_FIXED_BAR_5_SIZE 0x1c
/**
* fixed_bar_cap - return the offset of the fixed BAR cap if found
* @bus: PCI bus
* @devfn: device in question
*
* Look for the fixed BAR cap on @bus and @devfn, returning its offset
* if found or 0 otherwise.
*/
static int fixed_bar_cap(struct pci_bus *bus, unsigned int devfn)
{
int pos;
u32 pcie_cap = 0, cap_data;
pos = PCIE_CAP_OFFSET;
if (!raw_pci_ext_ops)
return 0;
while (pos) {
if (raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
devfn, pos, 4, &pcie_cap))
return 0;
if (pcie_cap == 0xffffffff)
return 0;
if (PCI_EXT_CAP_ID(pcie_cap) == PCI_EXT_CAP_ID_VNDR) {
raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
devfn, pos + 4, 4, &cap_data);
if ((cap_data & 0xffff) == PCIE_VNDR_CAP_ID_FIXED_BAR)
return pos;
}
pos = pcie_cap >> 20;
}
return 0;
}
static int pci_device_update_fixed(struct pci_bus *bus, unsigned int devfn,
int reg, int len, u32 val, int offset)
{
u32 size;
unsigned int domain, busnum;
int bar = (reg - PCI_BASE_ADDRESS_0) >> 2;
domain = pci_domain_nr(bus);
busnum = bus->number;
if (val == ~0 && len == 4) {
unsigned long decode;
raw_pci_ext_ops->read(domain, busnum, devfn,
offset + 8 + (bar * 4), 4, &size);
/* Turn the size into a decode pattern for the sizing code */
if (size) {
decode = size - 1;
decode |= decode >> 1;
decode |= decode >> 2;
decode |= decode >> 4;
decode |= decode >> 8;
decode |= decode >> 16;
decode++;
decode = ~(decode - 1);
} else {
decode = ~0;
}
/*
* If val is all ones, the core code is trying to size the reg,
* so update the mmconfig space with the real size.
*
* Note: this assumes the fixed size we got is a power of two.
*/
return raw_pci_ext_ops->write(domain, busnum, devfn, reg, 4,
decode);
}
/* This is some other kind of BAR write, so just do it. */
return raw_pci_ext_ops->write(domain, busnum, devfn, reg, len, val);
}
/**
* type1_access_ok - check whether to use type 1
* @bus: bus number
* @devfn: device & function in question
*
* If the bus is on a Lincroft chip and it exists, or is not on a Lincroft at
* all, the we can go ahead with any reads & writes. If it's on a Lincroft,
* but doesn't exist, avoid the access altogether to keep the chip from
* hanging.
*/
static bool type1_access_ok(unsigned int bus, unsigned int devfn, int reg)
{
/* This is a workaround for A0 LNC bug where PCI status register does
* not have new CAP bit set. can not be written by SW either.
*
* PCI header type in real LNC indicates a single function device, this
* will prevent probing other devices under the same function in PCI
* shim. Therefore, use the header type in shim instead.
*/
if (reg >= 0x100 || reg == PCI_STATUS || reg == PCI_HEADER_TYPE)
return 0;
if (bus == 0 && (devfn == PCI_DEVFN(2, 0) || devfn == PCI_DEVFN(0, 0)))
return 1;
return 0; /* langwell on others */
}
static int pci_read(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 *value)
{
if (type1_access_ok(bus->number, devfn, where))
return pci_direct_conf1.read(pci_domain_nr(bus), bus->number,
devfn, where, size, value);
return raw_pci_ext_ops->read(pci_domain_nr(bus), bus->number,
devfn, where, size, value);
}
static int pci_write(struct pci_bus *bus, unsigned int devfn, int where,
int size, u32 value)
{
int offset;
/* On MRST, there is no PCI ROM BAR, this will cause a subsequent read
* to ROM BAR return 0 then being ignored.
*/
if (where == PCI_ROM_ADDRESS)
return 0;
/*
* Devices with fixed BARs need special handling:
* - BAR sizing code will save, write ~0, read size, restore
* - so writes to fixed BARs need special handling
* - other writes to fixed BAR devices should go through mmconfig
*/
offset = fixed_bar_cap(bus, devfn);
if (offset &&
(where >= PCI_BASE_ADDRESS_0 && where <= PCI_BASE_ADDRESS_5)) {
return pci_device_update_fixed(bus, devfn, where, size, value,
offset);
}
/*
* On Moorestown update both real & mmconfig space
* Note: early Lincroft silicon can't handle type 1 accesses to
* non-existent devices, so just eat the write in that case.
*/
if (type1_access_ok(bus->number, devfn, where))
return pci_direct_conf1.write(pci_domain_nr(bus), bus->number,
devfn, where, size, value);
return raw_pci_ext_ops->write(pci_domain_nr(bus), bus->number, devfn,
where, size, value);
}
static int mrst_pci_irq_enable(struct pci_dev *dev)
{
u8 pin;
struct io_apic_irq_attr irq_attr;
pci_read_config_byte(dev, PCI_INTERRUPT_PIN, &pin);
/* MRST only have IOAPIC, the PCI irq lines are 1:1 mapped to
* IOAPIC RTE entries, so we just enable RTE for the device.
*/
irq_attr.ioapic = mp_find_ioapic(dev->irq);
irq_attr.ioapic_pin = dev->irq;
irq_attr.trigger = 1; /* level */
irq_attr.polarity = 1; /* active low */
io_apic_set_pci_routing(&dev->dev, dev->irq, &irq_attr);
return 0;
}
struct pci_ops pci_mrst_ops = {
.read = pci_read,
.write = pci_write,
};
/**
* pci_mrst_init - installs pci_mrst_ops
*
* Moorestown has an interesting PCI implementation (see above).
* Called when the early platform detection installs it.
*/
int __init pci_mrst_init(void)
{
printk(KERN_INFO "Moorestown platform detected, using MRST PCI ops\n");
pci_mmcfg_late_init();
pcibios_enable_irq = mrst_pci_irq_enable;
pci_root_ops = pci_mrst_ops;
/* Continue with standard init */
return 1;
}
/*
* Langwell devices reside at fixed offsets, don't try to move them.
*/
static void __devinit pci_fixed_bar_fixup(struct pci_dev *dev)
{
unsigned long offset;
u32 size;
int i;
/* Fixup the BAR sizes for fixed BAR devices and make them unmoveable */
offset = fixed_bar_cap(dev->bus, dev->devfn);
if (!offset || PCI_DEVFN(2, 0) == dev->devfn ||
PCI_DEVFN(2, 2) == dev->devfn)
return;
for (i = 0; i < PCI_ROM_RESOURCE; i++) {
pci_read_config_dword(dev, offset + 8 + (i * 4), &size);
dev->resource[i].end = dev->resource[i].start + size - 1;
dev->resource[i].flags |= IORESOURCE_PCI_FIXED;
}
}
DECLARE_PCI_FIXUP_HEADER(PCI_VENDOR_ID_INTEL, PCI_ANY_ID, pci_fixed_bar_fixup);
...@@ -148,14 +148,8 @@ int __init pci_numaq_init(void) ...@@ -148,14 +148,8 @@ int __init pci_numaq_init(void)
{ {
int quad; int quad;
if (!found_numaq)
return 0;
raw_pci_ops = &pci_direct_conf1_mq; raw_pci_ops = &pci_direct_conf1_mq;
if (pcibios_scanned++)
return 0;
pci_root_bus = pcibios_scan_root(0); pci_root_bus = pcibios_scan_root(0);
if (pci_root_bus) if (pci_root_bus)
pci_bus_add_devices(pci_root_bus); pci_bus_add_devices(pci_root_bus);
......
...@@ -304,9 +304,6 @@ static struct pci_raw_ops pci_olpc_conf = { ...@@ -304,9 +304,6 @@ static struct pci_raw_ops pci_olpc_conf = {
int __init pci_olpc_init(void) int __init pci_olpc_init(void)
{ {
if (!machine_is_olpc() || olpc_has_vsa())
return -ENODEV;
printk(KERN_INFO "PCI: Using configuration type OLPC\n"); printk(KERN_INFO "PCI: Using configuration type OLPC\n");
raw_pci_ops = &pci_olpc_conf; raw_pci_ops = &pci_olpc_conf;
is_lx = is_geode_lx(); is_lx = is_geode_lx();
......
...@@ -69,9 +69,6 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq) ...@@ -69,9 +69,6 @@ void __init pcibios_update_irq(struct pci_dev *dev, int irq)
int __init pci_visws_init(void) int __init pci_visws_init(void)
{ {
if (!is_visws_box())
return -1;
pcibios_enable_irq = &pci_visws_enable_irq; pcibios_enable_irq = &pci_visws_enable_irq;
pcibios_disable_irq = &pci_visws_disable_irq; pcibios_disable_irq = &pci_visws_disable_irq;
...@@ -90,5 +87,6 @@ int __init pci_visws_init(void) ...@@ -90,5 +87,6 @@ int __init pci_visws_init(void)
pci_scan_bus_with_sysdata(pci_bus1); pci_scan_bus_with_sysdata(pci_bus1);
pci_fixup_irqs(pci_common_swizzle, visws_map_irq); pci_fixup_irqs(pci_common_swizzle, visws_map_irq);
pcibios_resource_survey(); pcibios_resource_survey();
return 0; /* Request bus scan */
return 1;
} }
...@@ -303,6 +303,49 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap) ...@@ -303,6 +303,49 @@ int pci_find_ext_capability(struct pci_dev *dev, int cap)
} }
EXPORT_SYMBOL_GPL(pci_find_ext_capability); EXPORT_SYMBOL_GPL(pci_find_ext_capability);
/**
* pci_bus_find_ext_capability - find an extended capability
* @bus: the PCI bus to query
* @devfn: PCI device to query
* @cap: capability code
*
* Like pci_find_ext_capability() but works for pci devices that do not have a
* pci_dev structure set up yet.
*
* Returns the address of the requested capability structure within the
* device's PCI configuration space or 0 in case the device does not
* support it.
*/
int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
int cap)
{
u32 header;
int ttl;
int pos = PCI_CFG_SPACE_SIZE;
/* minimum 8 bytes per capability */
ttl = (PCI_CFG_SPACE_EXP_SIZE - PCI_CFG_SPACE_SIZE) / 8;
if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
return 0;
if (header == 0xffffffff || header == 0)
return 0;
while (ttl-- > 0) {
if (PCI_EXT_CAP_ID(header) == cap)
return pos;
pos = PCI_EXT_CAP_NEXT(header);
if (pos < PCI_CFG_SPACE_SIZE)
break;
if (!pci_bus_read_config_dword(bus, devfn, pos, &header))
break;
}
return 0;
}
static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap) static int __pci_find_next_ht_cap(struct pci_dev *dev, int pos, int ht_cap)
{ {
int rc, ttl = PCI_FIND_CAP_TTL; int rc, ttl = PCI_FIND_CAP_TTL;
......
...@@ -678,6 +678,8 @@ enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev); ...@@ -678,6 +678,8 @@ enum pci_lost_interrupt_reason pci_lost_interrupt(struct pci_dev *dev);
int pci_find_capability(struct pci_dev *dev, int cap); int pci_find_capability(struct pci_dev *dev, int cap);
int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap); int pci_find_next_capability(struct pci_dev *dev, u8 pos, int cap);
int pci_find_ext_capability(struct pci_dev *dev, int cap); int pci_find_ext_capability(struct pci_dev *dev, int cap);
int pci_bus_find_ext_capability(struct pci_bus *bus, unsigned int devfn,
int cap);
int pci_find_ht_capability(struct pci_dev *dev, int ht_cap); int pci_find_ht_capability(struct pci_dev *dev, int ht_cap);
int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap); int pci_find_next_ht_capability(struct pci_dev *dev, int pos, int ht_cap);
struct pci_bus *pci_find_next_bus(const struct pci_bus *from); struct pci_bus *pci_find_next_bus(const struct pci_bus *from);
......
...@@ -507,6 +507,7 @@ ...@@ -507,6 +507,7 @@
#define PCI_EXT_CAP_ID_VC 2 #define PCI_EXT_CAP_ID_VC 2
#define PCI_EXT_CAP_ID_DSN 3 #define PCI_EXT_CAP_ID_DSN 3
#define PCI_EXT_CAP_ID_PWR 4 #define PCI_EXT_CAP_ID_PWR 4
#define PCI_EXT_CAP_ID_VNDR 11
#define PCI_EXT_CAP_ID_ACS 13 #define PCI_EXT_CAP_ID_ACS 13
#define PCI_EXT_CAP_ID_ARI 14 #define PCI_EXT_CAP_ID_ARI 14
#define PCI_EXT_CAP_ID_ATS 15 #define PCI_EXT_CAP_ID_ATS 15
......
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