Commit 32859f73 authored by Michel Dänzer's avatar Michel Dänzer Committed by Alex Deucher

drm/amdgpu/dce6: Set MASTER_UPDATE_MODE to 0 in resume_mc_access as well

Looks like this was missed when dce_v6_0.c was added.

Fixes: e2cdf640 ("drm/amdgpu: add display controller implementation for si v10")
Reviewed-by: default avatarChristian König <christian.koenig@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarMichel Dänzer <michel.daenzer@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
parent 7fe28576
...@@ -460,9 +460,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev, ...@@ -460,9 +460,8 @@ static void dce_v6_0_resume_mc_access(struct amdgpu_device *adev,
for (i = 0; i < adev->mode_info.num_crtc; i++) { for (i = 0; i < adev->mode_info.num_crtc; i++) {
if (save->crtc_enabled[i]) { if (save->crtc_enabled[i]) {
tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]); tmp = RREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i]);
if ((tmp & 0x7) != 3) { if ((tmp & 0x7) != 0) {
tmp &= ~0x7; tmp &= ~0x7;
tmp |= 0x3;
WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp); WREG32(mmMASTER_UPDATE_MODE + crtc_offsets[i], tmp);
} }
tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]); tmp = RREG32(mmGRPH_UPDATE + crtc_offsets[i]);
......
Markdown is supported
0%
or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment