Commit 32f2ed86 authored by William Wu's avatar William Wu Committed by Felipe Balbi

usb: dwc3: make usb2 phy utmi interface configurable

Support to configure the UTMI+ PHY with an 8- or 16-bit
interface via DT. The UTMI+ PHY interface is a hardware
capability, and it's platform dependent. Normally, the
PHYIF can be configured during coreconsultant.

But for some specific USB cores(e.g. rk3399 SoC DWC3),
the default PHYIF configuration value is false, so we
need to reconfigure it by software.
Signed-off-by: default avatarWilliam Wu <william.wu@rock-chips.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Signed-off-by: default avatarFelipe Balbi <felipe.balbi@linux.intel.com>
parent 16199f33
...@@ -11,6 +11,11 @@ Optional properties: ...@@ -11,6 +11,11 @@ Optional properties:
"peripheral" and "otg". In case this attribute isn't "peripheral" and "otg". In case this attribute isn't
passed via DT, USB DRD controllers should default to passed via DT, USB DRD controllers should default to
OTG. OTG.
- phy_type: tells USB controllers that we want to configure the core to support
a UTMI+ PHY with an 8- or 16-bit interface if UTMI+ is
selected. Valid arguments are "utmi" and "utmi_wide".
In case this isn't passed via DT, USB controllers should
default to HW capability.
- otg-rev: tells usb driver the release number of the OTG and EH supplement - otg-rev: tells usb driver the release number of the OTG and EH supplement
with which the device and its descriptors are compliant, with which the device and its descriptors are compliant,
in binary-coded decimal (i.e. 2.0 is 0200H). This in binary-coded decimal (i.e. 2.0 is 0200H). This
...@@ -34,6 +39,7 @@ dwc3@4a030000 { ...@@ -34,6 +39,7 @@ dwc3@4a030000 {
usb-phy = <&usb2_phy>, <&usb3,phy>; usb-phy = <&usb2_phy>, <&usb3,phy>;
maximum-speed = "super-speed"; maximum-speed = "super-speed";
dr_mode = "otg"; dr_mode = "otg";
phy_type = "utmi_wide";
otg-rev = <0x0200>; otg-rev = <0x0200>;
adp-disable; adp-disable;
}; };
...@@ -485,6 +485,23 @@ static int dwc3_phy_setup(struct dwc3 *dwc) ...@@ -485,6 +485,23 @@ static int dwc3_phy_setup(struct dwc3 *dwc)
break; break;
} }
switch (dwc->hsphy_mode) {
case USBPHY_INTERFACE_MODE_UTMI:
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
break;
case USBPHY_INTERFACE_MODE_UTMIW:
reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
break;
default:
break;
}
/* /*
* Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
* '0' during coreConsultant configuration. So default value will * '0' during coreConsultant configuration. So default value will
...@@ -891,6 +908,7 @@ static int dwc3_probe(struct platform_device *pdev) ...@@ -891,6 +908,7 @@ static int dwc3_probe(struct platform_device *pdev)
dwc->maximum_speed = usb_get_maximum_speed(dev); dwc->maximum_speed = usb_get_maximum_speed(dev);
dwc->dr_mode = usb_get_dr_mode(dev); dwc->dr_mode = usb_get_dr_mode(dev);
dwc->hsphy_mode = of_usb_get_phy_mode(dev->of_node);
dwc->has_lpm_erratum = device_property_read_bool(dev, dwc->has_lpm_erratum = device_property_read_bool(dev,
"snps,has-lpm-erratum"); "snps,has-lpm-erratum");
......
...@@ -203,6 +203,14 @@ ...@@ -203,6 +203,14 @@
#define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6) #define DWC3_GUSB2PHYCFG_SUSPHY (1 << 6)
#define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4) #define DWC3_GUSB2PHYCFG_ULPI_UTMI (1 << 4)
#define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8) #define DWC3_GUSB2PHYCFG_ENBLSLPM (1 << 8)
#define DWC3_GUSB2PHYCFG_PHYIF(n) (n << 3)
#define DWC3_GUSB2PHYCFG_PHYIF_MASK DWC3_GUSB2PHYCFG_PHYIF(1)
#define DWC3_GUSB2PHYCFG_USBTRDTIM(n) (n << 10)
#define DWC3_GUSB2PHYCFG_USBTRDTIM_MASK DWC3_GUSB2PHYCFG_USBTRDTIM(0xf)
#define USBTRDTIM_UTMI_8_BIT 9
#define USBTRDTIM_UTMI_16_BIT 5
#define UTMI_PHYIF_16_BIT 1
#define UTMI_PHYIF_8_BIT 0
/* Global USB2 PHY Vendor Control Register */ /* Global USB2 PHY Vendor Control Register */
#define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25) #define DWC3_GUSB2PHYACC_NEWREGREQ (1 << 25)
...@@ -748,6 +756,9 @@ struct dwc3_scratchpad_array { ...@@ -748,6 +756,9 @@ struct dwc3_scratchpad_array {
* @maximum_speed: maximum speed requested (mainly for testing purposes) * @maximum_speed: maximum speed requested (mainly for testing purposes)
* @revision: revision register contents * @revision: revision register contents
* @dr_mode: requested mode of operation * @dr_mode: requested mode of operation
* @hsphy_mode: UTMI phy mode, one of following:
* - USBPHY_INTERFACE_MODE_UTMI
* - USBPHY_INTERFACE_MODE_UTMIW
* @usb2_phy: pointer to USB2 PHY * @usb2_phy: pointer to USB2 PHY
* @usb3_phy: pointer to USB3 PHY * @usb3_phy: pointer to USB3 PHY
* @usb2_generic_phy: pointer to USB2 PHY * @usb2_generic_phy: pointer to USB2 PHY
...@@ -853,6 +864,7 @@ struct dwc3 { ...@@ -853,6 +864,7 @@ struct dwc3 {
size_t regs_size; size_t regs_size;
enum usb_dr_mode dr_mode; enum usb_dr_mode dr_mode;
enum usb_phy_interface hsphy_mode;
u32 fladj; u32 fladj;
u32 irq_gadget; u32 irq_gadget;
......
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