drm/amdgpu: rename ip_dump_cp_queues to compute queues

Rename the variable ip_dump_cp_queues to ip_dump_compute_queue
as it represent compute queues.
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Sunil Khatri <sunil.khatri@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>

drivers/gpu/drm/amd/amdgpu/amdgpu_gfx.h

@@ -436,7 +436,7 @@ struct amdgpu_gfx {
 
 	/* IP reg dump */
 	uint32_t			*ip_dump_core;
-	uint32_t			*ip_dump_cp_queues;
+	uint32_t			*ip_dump_compute_queues;
 	uint32_t			*ip_dump_gfx_queues;
 };
 

drivers/gpu/drm/amd/amdgpu/gfx_v10_0.c

@@ -4664,9 +4664,9 @@ static void gfx_v10_0_alloc_ip_dump(struct amdgpu_device *adev)
 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
 	if (ptr == NULL) {
 		DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
-		adev->gfx.ip_dump_cp_queues = NULL;
+		adev->gfx.ip_dump_compute_queues = NULL;
 	} else {
-		adev->gfx.ip_dump_cp_queues = ptr;
+		adev->gfx.ip_dump_compute_queues = ptr;
 	}
 
 	/* Allocate memory for gfx queue registers for all the instances */
@@ -4886,7 +4886,7 @@ static int gfx_v10_0_sw_fini(void *handle)
 	gfx_v10_0_free_microcode(adev);
 
 	kfree(adev->gfx.ip_dump_core);
-	kfree(adev->gfx.ip_dump_cp_queues);
+	kfree(adev->gfx.ip_dump_compute_queues);
 	kfree(adev->gfx.ip_dump_gfx_queues);
 
 	return 0;
@@ -9261,7 +9261,7 @@ static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
 			   adev->gfx.ip_dump_core[i]);
 
 	/* print compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
@@ -9277,7 +9277,7 @@ static void gfx_v10_ip_print(void *handle, struct drm_printer *p)
 				for (reg = 0; reg < reg_count; reg++) {
 					drm_printf(p, "%-50s \t 0x%08x\n",
 						   gc_cp_reg_list_10[reg].reg_name,
-						   adev->gfx.ip_dump_cp_queues[index + reg]);
+						   adev->gfx.ip_dump_compute_queues[index + reg]);
 				}
 				index += reg_count;
 			}
@@ -9324,7 +9324,7 @@ static void gfx_v10_ip_dump(void *handle)
 	amdgpu_gfx_off_ctrl(adev, true);
 
 	/* dump compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_10);
@@ -9337,7 +9337,7 @@ static void gfx_v10_ip_dump(void *handle)
 				nv_grbm_select(adev, 1 + i, j, k, 0);
 
 				for (reg = 0; reg < reg_count; reg++) {
-					adev->gfx.ip_dump_cp_queues[index + reg] =
+					adev->gfx.ip_dump_compute_queues[index + reg] =
 						RREG32(SOC15_REG_ENTRY_OFFSET(
 							gc_cp_reg_list_10[reg]));
 				}

drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c

@@ -1496,9 +1496,9 @@ static void gfx_v11_0_alloc_ip_dump(struct amdgpu_device *adev)
 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
 	if (ptr == NULL) {
 		DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
-		adev->gfx.ip_dump_cp_queues = NULL;
+		adev->gfx.ip_dump_compute_queues = NULL;
 	} else {
-		adev->gfx.ip_dump_cp_queues = ptr;
+		adev->gfx.ip_dump_compute_queues = ptr;
 	}
 
 	/* Allocate memory for gfx queue registers for all the instances */
@@ -1731,7 +1731,7 @@ static int gfx_v11_0_sw_fini(void *handle)
 	gfx_v11_0_free_microcode(adev);
 
 	kfree(adev->gfx.ip_dump_core);
-	kfree(adev->gfx.ip_dump_cp_queues);
+	kfree(adev->gfx.ip_dump_compute_queues);
 	kfree(adev->gfx.ip_dump_gfx_queues);
 
 	return 0;
@@ -6378,7 +6378,7 @@ static void gfx_v11_ip_print(void *handle, struct drm_printer *p)
 			   adev->gfx.ip_dump_core[i]);
 
 	/* print compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
@@ -6394,7 +6394,7 @@ static void gfx_v11_ip_print(void *handle, struct drm_printer *p)
 				for (reg = 0; reg < reg_count; reg++) {
 					drm_printf(p, "%-50s \t 0x%08x\n",
 						   gc_cp_reg_list_11[reg].reg_name,
-						   adev->gfx.ip_dump_cp_queues[index + reg]);
+						   adev->gfx.ip_dump_compute_queues[index + reg]);
 				}
 				index += reg_count;
 			}
@@ -6441,7 +6441,7 @@ static void gfx_v11_ip_dump(void *handle)
 	amdgpu_gfx_off_ctrl(adev, true);
 
 	/* dump compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_11);
@@ -6453,7 +6453,7 @@ static void gfx_v11_ip_dump(void *handle)
 				/* ME0 is for GFX so start from 1 for CP */
 				soc21_grbm_select(adev, 1+i, j, k, 0);
 				for (reg = 0; reg < reg_count; reg++) {
-					adev->gfx.ip_dump_cp_queues[index + reg] =
+					adev->gfx.ip_dump_compute_queues[index + reg] =
 						RREG32(SOC15_REG_ENTRY_OFFSET(
 							gc_cp_reg_list_11[reg]));
 				}

drivers/gpu/drm/amd/amdgpu/gfx_v9_0.c

@@ -2145,9 +2145,9 @@ static void gfx_v9_0_alloc_ip_dump(struct amdgpu_device *adev)
 	ptr = kcalloc(reg_count * inst, sizeof(uint32_t), GFP_KERNEL);
 	if (ptr == NULL) {
 		DRM_ERROR("Failed to allocate memory for GFX CP IP Dump\n");
-		adev->gfx.ip_dump_cp_queues = NULL;
+		adev->gfx.ip_dump_compute_queues = NULL;
 	} else {
-		adev->gfx.ip_dump_cp_queues = ptr;
+		adev->gfx.ip_dump_compute_queues = ptr;
 	}
 }
 
@@ -2366,7 +2366,7 @@ static int gfx_v9_0_sw_fini(void *handle)
 	gfx_v9_0_free_microcode(adev);
 
 	kfree(adev->gfx.ip_dump_core);
-	kfree(adev->gfx.ip_dump_cp_queues);
+	kfree(adev->gfx.ip_dump_compute_queues);
 
 	return 0;
 }
@@ -7017,7 +7017,7 @@ static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
 			   adev->gfx.ip_dump_core[i]);
 
 	/* print compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
@@ -7033,7 +7033,7 @@ static void gfx_v9_ip_print(void *handle, struct drm_printer *p)
 				for (reg = 0; reg < reg_count; reg++) {
 					drm_printf(p, "%-50s \t 0x%08x\n",
 						   gc_cp_reg_list_9[reg].reg_name,
-						   adev->gfx.ip_dump_cp_queues[index + reg]);
+						   adev->gfx.ip_dump_compute_queues[index + reg]);
 				}
 				index += reg_count;
 			}
@@ -7057,7 +7057,7 @@ static void gfx_v9_ip_dump(void *handle)
 	amdgpu_gfx_off_ctrl(adev, true);
 
 	/* dump compute queue registers for all instances */
-	if (!adev->gfx.ip_dump_cp_queues)
+	if (!adev->gfx.ip_dump_compute_queues)
 		return;
 
 	reg_count = ARRAY_SIZE(gc_cp_reg_list_9);
@@ -7070,7 +7070,7 @@ static void gfx_v9_ip_dump(void *handle)
 				soc15_grbm_select(adev, 1 + i, j, k, 0, 0);
 
 				for (reg = 0; reg < reg_count; reg++) {
-					adev->gfx.ip_dump_cp_queues[index + reg] =
+					adev->gfx.ip_dump_compute_queues[index + reg] =
 						RREG32(SOC15_REG_ENTRY_OFFSET(
 							gc_cp_reg_list_9[reg]));
 				}