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Commit 342ab21d authored by Manivannan Sadhasivam's avatar Manivannan Sadhasivam Committed by Vinod Koul
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phy: qcom-qmp-ufs: Remove _tbl suffix from qmp_phy_init_tbl definitions 

Following the other QMP PHY drivers like PCIe, let's remove the "_tbl"
suffix from the qmp_phy_init_tbl definitions. This helps in maintaining
the uniformity across all of the QMP PHY drivers.
Reviewed-by: default avatarDmitry Baryshkov <dmitry.baryshkov@linaro.org>
Tested-by: Andrew Halaney <ahalaney@redhat.com> # Qdrive3/sa8540p-ride
Signed-off-by: default avatarManivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Link: https://lore.kernel.org/r/20230114071009.88102-2-manivannan.sadhasivam@linaro.orgSigned-off-by: default avatarVinod Koul <vkoul@kernel.org>
parent 43108bb2
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Showing with 73 additions and 73 deletions
drivers/phy/qualcomm/phy-qcom-qmp-ufs.c
View file @ 342ab21d
...@@ -99,7 +99,7 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = { ...@@ -99,7 +99,7 @@ static const unsigned int ufsphy_v5_regs_layout[QPHY_LAYOUT_SIZE] = {
[QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL, [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_UFS_POWER_DOWN_CONTROL,
}; };
static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { static const struct qmp_phy_init_tbl msm8996_ufs_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0xd7),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
...@@ -148,12 +148,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = { ...@@ -148,12 +148,12 @@ static const struct qmp_phy_init_tbl msm8996_ufs_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00), QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE1, 0x00),
}; };
static const struct qmp_phy_init_tbl msm8996_ufs_tx_tbl[] = { static const struct qmp_phy_init_tbl msm8996_ufs_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x02),
}; };
static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { static const struct qmp_phy_init_tbl msm8996_ufs_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x02),
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x00),
...@@ -167,7 +167,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = { ...@@ -167,7 +167,7 @@ static const struct qmp_phy_init_tbl msm8996_ufs_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E), QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0E),
}; };
static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e), QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x0e),
QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
...@@ -223,12 +223,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = { ...@@ -223,12 +223,12 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44), QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x44),
}; };
static const struct qmp_phy_init_tbl sm6115_ufsphy_tx_tbl[] = { static const struct qmp_phy_init_tbl sm6115_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
}; };
static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { static const struct qmp_phy_init_tbl sm6115_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F), QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x0F),
QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40), QMP_PHY_INIT_CFG(QSERDES_RX_RX_INTERFACE_MODE, 0x40),
...@@ -246,7 +246,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = { ...@@ -246,7 +246,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B), QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x5B),
}; };
static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15), QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_PWM_GEAR_BAND, 0x15),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f), QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0f),
...@@ -258,7 +258,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = { ...@@ -258,7 +258,7 @@ static const struct qmp_phy_init_tbl sm6115_ufsphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */ QMP_PHY_INIT_CFG(QPHY_V2_PCS_UFS_RX_MIN_HIBERN8_TIME, 0x9a), /* 8 us */
}; };
static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
...@@ -300,13 +300,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = { ...@@ -300,13 +300,13 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44), QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x44),
}; };
static const struct qmp_phy_init_tbl sdm845_ufsphy_tx_tbl[] = { static const struct qmp_phy_init_tbl sdm845_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x04),
QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07), QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x07),
}; };
static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { static const struct qmp_phy_init_tbl sdm845_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
...@@ -325,7 +325,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = { ...@@ -325,7 +325,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59), QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x59),
}; };
static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_RX_SIGDET_CTRL2, 0x6e),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
...@@ -336,7 +336,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = { ...@@ -336,7 +336,7 @@ static const struct qmp_phy_init_tbl sdm845_ufsphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02), QMP_PHY_INIT_CFG(QPHY_V3_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
}; };
static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL, 0x00),
...@@ -366,7 +366,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = { ...@@ -366,7 +366,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x06),
}; };
static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { static const struct qmp_phy_init_tbl sm8150_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), QMP_PHY_INIT_CFG(QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
...@@ -375,7 +375,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = { ...@@ -375,7 +375,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V4_TX_TRAN_DRVR_EMP_EN, 0x0c),
}; };
static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { static const struct qmp_phy_init_tbl sm8150_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
...@@ -413,7 +413,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = { ...@@ -413,7 +413,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_rx_tbl[] = {
}; };
static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
...@@ -423,7 +423,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = { ...@@ -423,7 +423,7 @@ static const struct qmp_phy_init_tbl sm8150_ufsphy_pcs_tbl[] = {
QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02), QMP_PHY_INIT_CFG(QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1, 0x02),
}; };
static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9), QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0xd9),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x11),
QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00), QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL, 0x00),
...@@ -453,7 +453,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = { ...@@ -453,7 +453,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_serdes_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x06),
}; };
static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { static const struct qmp_phy_init_tbl sm8350_ufsphy_tx[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1, 0x06),
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1, 0x03),
QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01), QMP_PHY_INIT_CFG(QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1, 0x01),
...@@ -465,7 +465,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = { ...@@ -465,7 +465,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_tx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V5_TX_TRAN_DRVR_EMP_EN, 0x0c),
}; };
static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { static const struct qmp_phy_init_tbl sm8350_ufsphy_rx[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_LVL, 0x24),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x0f),
QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e), QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x1e),
...@@ -505,7 +505,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = { ...@@ -505,7 +505,7 @@ static const struct qmp_phy_init_tbl sm8350_ufsphy_rx_tbl[] = {
QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c),
}; };
static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs_tbl[] = { static const struct qmp_phy_init_tbl sm8350_ufsphy_pcs[] = {
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2, 0x6d),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL, 0x0a),
QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02), QMP_PHY_INIT_CFG(QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL, 0x02),
...@@ -637,12 +637,12 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = { ...@@ -637,12 +637,12 @@ static const struct qmp_ufs_offsets qmp_ufs_offsets_v5 = {
static const struct qmp_phy_cfg msm8996_ufs_cfg = { static const struct qmp_phy_cfg msm8996_ufs_cfg = {
.lanes = 1, .lanes = 1,
.serdes_tbl = msm8996_ufs_serdes_tbl, .serdes_tbl = msm8996_ufs_serdes,
.serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(msm8996_ufs_serdes),
.tx_tbl = msm8996_ufs_tx_tbl, .tx_tbl = msm8996_ufs_tx,
.tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx_tbl), .tx_tbl_num = ARRAY_SIZE(msm8996_ufs_tx),
.rx_tbl = msm8996_ufs_rx_tbl, .rx_tbl = msm8996_ufs_rx,
.rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx_tbl), .rx_tbl_num = ARRAY_SIZE(msm8996_ufs_rx),
.clk_list = msm8996_ufs_phy_clk_l, .clk_list = msm8996_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(msm8996_ufs_phy_clk_l),
...@@ -660,14 +660,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { ...@@ -660,14 +660,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
.offsets = &qmp_ufs_offsets_v5, .offsets = &qmp_ufs_offsets_v5,
.serdes_tbl = sm8350_ufsphy_serdes_tbl, .serdes_tbl = sm8350_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
.tx_tbl = sm8350_ufsphy_tx_tbl, .tx_tbl = sm8350_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
.rx_tbl = sm8350_ufsphy_rx_tbl, .rx_tbl = sm8350_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
.pcs_tbl = sm8350_ufsphy_pcs_tbl, .pcs_tbl = sm8350_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
.clk_list = sdm845_ufs_phy_clk_l, .clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
...@@ -678,14 +678,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = { ...@@ -678,14 +678,14 @@ static const struct qmp_phy_cfg sc8280xp_ufsphy_cfg = {
static const struct qmp_phy_cfg sdm845_ufsphy_cfg = { static const struct qmp_phy_cfg sdm845_ufsphy_cfg = {
.lanes = 2, .lanes = 2,
.serdes_tbl = sdm845_ufsphy_serdes_tbl, .serdes_tbl = sdm845_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sdm845_ufsphy_serdes),
.tx_tbl = sdm845_ufsphy_tx_tbl, .tx_tbl = sdm845_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_tx),
.rx_tbl = sdm845_ufsphy_rx_tbl, .rx_tbl = sdm845_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sdm845_ufsphy_rx),
.pcs_tbl = sdm845_ufsphy_pcs_tbl, .pcs_tbl = sdm845_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sdm845_ufsphy_pcs),
.clk_list = sdm845_ufs_phy_clk_l, .clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
...@@ -700,14 +700,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ...@@ -700,14 +700,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
.offsets = &qmp_ufs_offsets_v5, .offsets = &qmp_ufs_offsets_v5,
.serdes_tbl = sm6115_ufsphy_serdes_tbl, .serdes_tbl = sm6115_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sm6115_ufsphy_serdes),
.tx_tbl = sm6115_ufsphy_tx_tbl, .tx_tbl = sm6115_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_tx),
.rx_tbl = sm6115_ufsphy_rx_tbl, .rx_tbl = sm6115_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sm6115_ufsphy_rx),
.pcs_tbl = sm6115_ufsphy_pcs_tbl, .pcs_tbl = sm6115_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sm6115_ufsphy_pcs),
.clk_list = sdm845_ufs_phy_clk_l, .clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
...@@ -720,14 +720,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = { ...@@ -720,14 +720,14 @@ static const struct qmp_phy_cfg sm6115_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
.lanes = 2, .lanes = 2,
.serdes_tbl = sm8150_ufsphy_serdes_tbl, .serdes_tbl = sm8150_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sm8150_ufsphy_serdes),
.tx_tbl = sm8150_ufsphy_tx_tbl, .tx_tbl = sm8150_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_tx),
.rx_tbl = sm8150_ufsphy_rx_tbl, .rx_tbl = sm8150_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sm8150_ufsphy_rx),
.pcs_tbl = sm8150_ufsphy_pcs_tbl, .pcs_tbl = sm8150_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sm8150_ufsphy_pcs),
.clk_list = sdm845_ufs_phy_clk_l, .clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
...@@ -738,14 +738,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = { ...@@ -738,14 +738,14 @@ static const struct qmp_phy_cfg sm8150_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
.lanes = 2, .lanes = 2,
.serdes_tbl = sm8350_ufsphy_serdes_tbl, .serdes_tbl = sm8350_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
.tx_tbl = sm8350_ufsphy_tx_tbl, .tx_tbl = sm8350_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
.rx_tbl = sm8350_ufsphy_rx_tbl, .rx_tbl = sm8350_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
.pcs_tbl = sm8350_ufsphy_pcs_tbl, .pcs_tbl = sm8350_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
.clk_list = sdm845_ufs_phy_clk_l, .clk_list = sdm845_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sdm845_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
...@@ -756,14 +756,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = { ...@@ -756,14 +756,14 @@ static const struct qmp_phy_cfg sm8350_ufsphy_cfg = {
static const struct qmp_phy_cfg sm8450_ufsphy_cfg = { static const struct qmp_phy_cfg sm8450_ufsphy_cfg = {
.lanes = 2, .lanes = 2,
.serdes_tbl = sm8350_ufsphy_serdes_tbl, .serdes_tbl = sm8350_ufsphy_serdes,
.serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes_tbl), .serdes_tbl_num = ARRAY_SIZE(sm8350_ufsphy_serdes),
.tx_tbl = sm8350_ufsphy_tx_tbl, .tx_tbl = sm8350_ufsphy_tx,
.tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx_tbl), .tx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_tx),
.rx_tbl = sm8350_ufsphy_rx_tbl, .rx_tbl = sm8350_ufsphy_rx,
.rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx_tbl), .rx_tbl_num = ARRAY_SIZE(sm8350_ufsphy_rx),
.pcs_tbl = sm8350_ufsphy_pcs_tbl, .pcs_tbl = sm8350_ufsphy_pcs,
.pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs_tbl), .pcs_tbl_num = ARRAY_SIZE(sm8350_ufsphy_pcs),
.clk_list = sm8450_ufs_phy_clk_l, .clk_list = sm8450_ufs_phy_clk_l,
.num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l), .num_clks = ARRAY_SIZE(sm8450_ufs_phy_clk_l),
.vreg_list = qmp_phy_vreg_l, .vreg_list = qmp_phy_vreg_l,
......
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