Commit 349e1fba authored by Linus Torvalds's avatar Linus Torvalds

Merge branch 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux

* 'for-linus/samsung4' of git://git.fluff.org/bjdooks/linux: (98 commits)
  Input: s3c24xx_ts - depend on SAMSUNG_DEV_TS and update menu entry
  Input: s3c24xx_ts - Add FEAT for Samsung touchscreen support
  Input: s3c24xx_ts - Implement generic GPIO configuration callback
  ARM: SAMSUNG: Move s3c64xx dev-ts.c to plat-samsung and rename configuration
  ARM: SAMSUNG: Implements cfg_gpio function for Samsung touchscreen
  ARM: S3C64XX: Add touchscreen platform device definition
  ARM: SAMSUNG: Move mach/ts.h to plat/ts.h
  ARM: S5PC100: Move i2c helpers from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: Move frame buffer helpers from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: gpio.h cleanup
  ARM: S5PC100: Move gpio support from plat-s5pc1xx to mach-s5pc100
  ARM: S5PC100: Use common functions for gpiolib implementation
  drivers: serial: S5PC100 serial driver cleanup
  ARM: S5PC100: Pre-requisite clock patch for plat-s5pc1xx to plat-s5p move
  ARM: SAMSUNG: Copy common I2C0 device helpers to machine directories
  ARM: SAMSUNG: move driver strength gpio configuration helper to common dir
  ARM: S5PV210: Add GPIOlib support
  ARM: SAMSUNGy: fix broken timer irq base
  ARM: SMDK6440: Add audio devices on board
  ARM: S5P6440: Add audio platform devices
  ...
parents fa9dc265 504d36e9
...@@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__ ...@@ -110,6 +110,8 @@ CHECKFLAGS += -D__arm__
head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o head-y := arch/arm/kernel/head$(MMUEXT).o arch/arm/kernel/init_task.o
textofs-y := 0x00008000 textofs-y := 0x00008000
textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000 textofs-$(CONFIG_ARCH_CLPS711X) := 0x00028000
# We don't want the htc bootloader to corrupt kernel during resume
textofs-$(CONFIG_PM_H1940) := 0x00108000
# SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory # SA1111 DMA bug: we don't want the kernel to live in precious DMA-able memory
ifeq ($(CONFIG_ARCH_SA1100),y) ifeq ($(CONFIG_ARCH_SA1100),y)
textofs-$(CONFIG_SA1111) := 0x00208000 textofs-$(CONFIG_SA1111) := 0x00208000
......
...@@ -77,6 +77,7 @@ config ARCH_H1940 ...@@ -77,6 +77,7 @@ config ARCH_H1940
select PM_H1940 if PM select PM_H1940 if PM
select S3C_DEV_USB_HOST select S3C_DEV_USB_HOST
select S3C_DEV_NAND select S3C_DEV_NAND
select S3C2410_SETUP_TS
help help
Say Y here if you are using the HP IPAQ H1940 Say Y here if you are using the HP IPAQ H1940
...@@ -96,12 +97,19 @@ config PM_H1940 ...@@ -96,12 +97,19 @@ config PM_H1940
config MACH_N30 config MACH_N30
bool "Acer N30 family" bool "Acer N30 family"
select CPU_S3C2410 select CPU_S3C2410
select MACH_N35
select S3C_DEV_USB_HOST select S3C_DEV_USB_HOST
select S3C_DEV_NAND select S3C_DEV_NAND
help help
Say Y here if you want suppt for the Acer N30, Acer N35, Say Y here if you want suppt for the Acer N30, Acer N35,
Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs. Navman PiN570, Yakumo AlphaX or Airis NC05 PDAs.
config MACH_N35
bool
help
Internal node in order to enable support for Acer N35 if Acer N30 is
selected.
config ARCH_BAST config ARCH_BAST
bool "Simtec Electronics BAST (EB2410ITX)" bool "Simtec Electronics BAST (EB2410ITX)"
select CPU_S3C2410 select CPU_S3C2410
...@@ -111,6 +119,7 @@ config ARCH_BAST ...@@ -111,6 +119,7 @@ config ARCH_BAST
select MACH_BAST_IDE select MACH_BAST_IDE
select S3C24XX_DCLK select S3C24XX_DCLK
select ISA select ISA
select S3C_DEV_HWMON
select S3C_DEV_USB_HOST select S3C_DEV_USB_HOST
select S3C_DEV_NAND select S3C_DEV_NAND
help help
......
zreladdr-y := 0x30008000 ifeq ($(CONFIG_PM_H1940),y)
params_phys-y := 0x30000100 zreladdr-y := 0x30108000
params_phys-y := 0x30100100
else
zreladdr-y := 0x30008000
params_phys-y := 0x30000100
endif
...@@ -16,15 +16,28 @@ ...@@ -16,15 +16,28 @@
#define S3C2410_GPIONO(bank,offset) ((bank) + (offset)) #define S3C2410_GPIONO(bank,offset) ((bank) + (offset))
#define S3C2410_GPIO_BANKA (32*0)
#define S3C2410_GPIO_BANKB (32*1)
#define S3C2410_GPIO_BANKC (32*2)
#define S3C2410_GPIO_BANKD (32*3)
#define S3C2410_GPIO_BANKE (32*4)
#define S3C2410_GPIO_BANKF (32*5)
#define S3C2410_GPIO_BANKG (32*6) #define S3C2410_GPIO_BANKG (32*6)
#define S3C2410_GPIO_BANKH (32*7) #define S3C2410_GPIO_BANKH (32*7)
/* GPIO sizes for various SoCs:
*
* 2442
* 2410 2412 2440 2443 2416
* ---- ---- ---- ---- ----
* A 23 22 25 16 25
* B 11 11 11 11 9
* C 16 15 16 16 16
* D 16 16 16 16 16
* E 16 16 16 16 16
* F 8 8 8 8 8
* G 16 16 16 16 8
* H 11 11 9 15 15
* J -- -- 13 16 --
* K -- -- -- -- 16
* L -- -- -- 15 7
* M -- -- -- 2 2
*/
/* GPIO bank sizes */ /* GPIO bank sizes */
#define S3C2410_GPIO_A_NR (32) #define S3C2410_GPIO_A_NR (32)
#define S3C2410_GPIO_B_NR (32) #define S3C2410_GPIO_B_NR (32)
......
...@@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin) ...@@ -23,11 +23,11 @@ static inline struct s3c_gpio_chip *s3c_gpiolib_getchip(unsigned int pin)
{ {
struct s3c_gpio_chip *chip; struct s3c_gpio_chip *chip;
if (pin > S3C2410_GPG(10)) if (pin > S3C_GPIO_END)
return NULL; return NULL;
chip = &s3c24xx_gpios[pin/32]; chip = &s3c24xx_gpios[pin/32];
return (S3C2410_GPIO_OFFSET(pin) < chip->chip.ngpio) ? chip : NULL; return ((pin - chip->chip.base) < chip->chip.ngpio) ? chip : NULL;
} }
#endif /* __ASM_ARCH_GPIO_CORE_H */ #endif /* __ASM_ARCH_GPIO_CORE_H */
...@@ -20,10 +20,18 @@ ...@@ -20,10 +20,18 @@
* devices that need GPIO. * devices that need GPIO.
*/ */
#ifdef CONFIG_CPU_S3C244X
#define ARCH_NR_GPIOS (32 * 9 + CONFIG_S3C24XX_GPIO_EXTRA)
#else
#define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA) #define ARCH_NR_GPIOS (256 + CONFIG_S3C24XX_GPIO_EXTRA)
#endif
#include <asm-generic/gpio.h> #include <asm-generic/gpio.h>
#include <mach/gpio-nrs.h> #include <mach/gpio-nrs.h>
#include <mach/gpio-fns.h> #include <mach/gpio-fns.h>
#ifdef CONFIG_CPU_S3C24XX
#define S3C_GPIO_END (S3C2410_GPIO_BANKJ + 32)
#else
#define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32) #define S3C_GPIO_END (S3C2410_GPIO_BANKH + 32)
#endif
...@@ -187,6 +187,9 @@ ...@@ -187,6 +187,9 @@
#define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3 #define IRQ_S3CUART_TX3 IRQ_S3C2443_TX3
#define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3 #define IRQ_S3CUART_ERR3 IRQ_S3C2443_ERR3
#define IRQ_LCD_VSYNC IRQ_S3C2443_LCD3
#define IRQ_LCD_SYSTEM IRQ_S3C2443_LCD2
#ifdef CONFIG_CPU_S3C2440 #ifdef CONFIG_CPU_S3C2440
#define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97 #define IRQ_S3C244x_AC97 IRQ_S3C2440_AC97
#else #else
......
...@@ -67,6 +67,8 @@ ...@@ -67,6 +67,8 @@
#define S3C2443_PA_HSMMC (0x4A800000) #define S3C2443_PA_HSMMC (0x4A800000)
#define S3C2416_PA_HSMMC0 (0x4AC00000) #define S3C2416_PA_HSMMC0 (0x4AC00000)
#define S3C2443_PA_FB (0x4C800000)
/* S3C2412 memory and IO controls */ /* S3C2412 memory and IO controls */
#define S3C2412_PA_SSMC (0x4F000000) #define S3C2412_PA_SSMC (0x4F000000)
#define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000) #define S3C2412_VA_SSMC S3C_ADDR_CPU(0x00000000)
...@@ -106,6 +108,7 @@ ...@@ -106,6 +108,7 @@
#define S3C24XX_PA_SDI S3C2410_PA_SDI #define S3C24XX_PA_SDI S3C2410_PA_SDI
#define S3C24XX_PA_NAND S3C2410_PA_NAND #define S3C24XX_PA_NAND S3C2410_PA_NAND
#define S3C_PA_FB S3C2443_PA_FB
#define S3C_PA_IIC S3C2410_PA_IIC #define S3C_PA_IIC S3C2410_PA_IIC
#define S3C_PA_UART S3C24XX_PA_UART #define S3C_PA_UART S3C24XX_PA_UART
#define S3C_PA_USBHOST S3C2410_PA_USBHOST #define S3C_PA_USBHOST S3C2410_PA_USBHOST
......
...@@ -17,29 +17,11 @@ ...@@ -17,29 +17,11 @@
#include <mach/gpio-nrs.h> #include <mach/gpio-nrs.h>
#ifdef CONFIG_CPU_S3C2400 #ifdef CONFIG_CPU_S3C2400
#define S3C24XX_GPIO_BASE(x) S3C2400_GPIO_BASE(x) #define S3C24XX_MISCCR S3C2400_MISCCR
#define S3C24XX_MISCCR S3C2400_MISCCR
#else #else
#define S3C24XX_GPIO_BASE(x) S3C2410_GPIO_BASE(x) #define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#define S3C24XX_MISCCR S3C24XX_GPIOREG2(0x80)
#endif /* CONFIG_CPU_S3C2400 */ #endif /* CONFIG_CPU_S3C2400 */
/* S3C2400 doesn't have a 1:1 mapping to S3C2410 gpio base pins */
#define S3C2400_BANKNUM(pin) (((pin) & ~31) / 32)
#define S3C2400_BASEA2B(pin) ((((pin) & ~31) >> 2))
#define S3C2400_BASEC2H(pin) ((S3C2400_BANKNUM(pin) * 10) + \
(2 * (S3C2400_BANKNUM(pin)-2)))
#define S3C2400_GPIO_BASE(pin) (pin < S3C2410_GPIO_BANKC ? \
S3C2400_BASEA2B(pin)+S3C24XX_VA_GPIO : \
S3C2400_BASEC2H(pin)+S3C24XX_VA_GPIO)
#define S3C2410_GPIO_BASE(pin) ((((pin) & ~31) >> 1) + S3C24XX_VA_GPIO)
#define S3C2410_GPIO_OFFSET(pin) ((pin) & 31)
/* general configuration options */ /* general configuration options */
#define S3C2410_GPIO_LEAVE (0xFFFFFFFF) #define S3C2410_GPIO_LEAVE (0xFFFFFFFF)
......
...@@ -83,8 +83,7 @@ ...@@ -83,8 +83,7 @@
#define S3C2443_HCLKCON_DMA4 (1<<4) #define S3C2443_HCLKCON_DMA4 (1<<4)
#define S3C2443_HCLKCON_DMA5 (1<<5) #define S3C2443_HCLKCON_DMA5 (1<<5)
#define S3C2443_HCLKCON_CAMIF (1<<8) #define S3C2443_HCLKCON_CAMIF (1<<8)
#define S3C2443_HCLKCON_DISP (1<<9) #define S3C2443_HCLKCON_LCDC (1<<9)
#define S3C2443_HCLKCON_LCDC (1<<10)
#define S3C2443_HCLKCON_USBH (1<<11) #define S3C2443_HCLKCON_USBH (1<<11)
#define S3C2443_HCLKCON_USBD (1<<12) #define S3C2443_HCLKCON_USBD (1<<12)
#define S3C2443_HCLKCON_HSMMC (1<<16) #define S3C2443_HCLKCON_HSMMC (1<<16)
......
...@@ -633,7 +633,7 @@ static void __init bast_map_io(void) ...@@ -633,7 +633,7 @@ static void __init bast_map_io(void)
s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks)); s3c24xx_register_clocks(bast_clocks, ARRAY_SIZE(bast_clocks));
s3c_device_hwmon.dev.platform_data = &bast_hwmon_info; s3c_hwmon_set_platdata(&bast_hwmon_info);
s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc)); s3c24xx_init_io(bast_iodesc, ARRAY_SIZE(bast_iodesc));
s3c24xx_init_clocks(0); s3c24xx_init_clocks(0);
......
...@@ -46,7 +46,6 @@ ...@@ -46,7 +46,6 @@
#include <mach/h1940.h> #include <mach/h1940.h>
#include <mach/h1940-latch.h> #include <mach/h1940-latch.h>
#include <mach/fb.h> #include <mach/fb.h>
#include <mach/ts.h>
#include <plat/udc.h> #include <plat/udc.h>
#include <plat/iic.h> #include <plat/iic.h>
...@@ -57,6 +56,7 @@ ...@@ -57,6 +56,7 @@
#include <plat/pll.h> #include <plat/pll.h>
#include <plat/pm.h> #include <plat/pm.h>
#include <plat/mci.h> #include <plat/mci.h>
#include <plat/ts.h>
static struct map_desc h1940_iodesc[] __initdata = { static struct map_desc h1940_iodesc[] __initdata = {
[0] = { [0] = {
...@@ -146,6 +146,7 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = { ...@@ -146,6 +146,7 @@ static struct s3c2410_ts_mach_info h1940_ts_cfg __initdata = {
.delay = 10000, .delay = 10000,
.presc = 49, .presc = 49,
.oversampling_shift = 2, .oversampling_shift = 2,
.cfg_gpio = s3c24xx_ts_cfg_gpio,
}; };
/** /**
...@@ -163,8 +164,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = { ...@@ -163,8 +164,8 @@ static struct s3c2410fb_display h1940_lcd __initdata = {
.xres = 240, .xres = 240,
.yres = 320, .yres = 320,
.bpp = 16, .bpp = 16,
.left_margin = 20, .left_margin = 8,
.right_margin = 8, .right_margin = 20,
.hsync_len = 4, .hsync_len = 4,
.upper_margin = 8, .upper_margin = 8,
.lower_margin = 7, .lower_margin = 7,
...@@ -272,7 +273,6 @@ static struct platform_device h1940_lcd_powerdev = { ...@@ -272,7 +273,6 @@ static struct platform_device h1940_lcd_powerdev = {
}; };
static struct platform_device *h1940_devices[] __initdata = { static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_ts,
&s3c_device_ohci, &s3c_device_ohci,
&s3c_device_lcd, &s3c_device_lcd,
&s3c_device_wdt, &s3c_device_wdt,
...@@ -286,6 +286,8 @@ static struct platform_device *h1940_devices[] __initdata = { ...@@ -286,6 +286,8 @@ static struct platform_device *h1940_devices[] __initdata = {
&s3c_device_timer[0], &s3c_device_timer[0],
&h1940_backlight, &h1940_backlight,
&h1940_lcd_powerdev, &h1940_lcd_powerdev,
&s3c_device_adc,
&s3c_device_ts,
}; };
static void __init h1940_map_io(void) static void __init h1940_map_io(void)
...@@ -339,7 +341,7 @@ static void __init h1940_init(void) ...@@ -339,7 +341,7 @@ static void __init h1940_init(void)
} }
MACHINE_START(H1940, "IPAQ-H1940") MACHINE_START(H1940, "IPAQ-H1940")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -26,6 +26,7 @@ ...@@ -26,6 +26,7 @@
#include <linux/serial_core.h> #include <linux/serial_core.h>
#include <linux/timer.h> #include <linux/timer.h>
#include <linux/io.h> #include <linux/io.h>
#include <linux/mmc/host.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <asm/irq.h> #include <asm/irq.h>
...@@ -46,6 +47,7 @@ ...@@ -46,6 +47,7 @@
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/mci.h>
#include <plat/s3c2410.h> #include <plat/s3c2410.h>
#include <plat/udc.h> #include <plat/udc.h>
...@@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = { ...@@ -172,8 +174,10 @@ static struct gpio_keys_button n35_buttons[] = {
{ {
.gpio = S3C2410_GPF(0), .gpio = S3C2410_GPF(0),
.code = KEY_POWER, .code = KEY_POWER,
.type = EV_PWR,
.desc = "Power", .desc = "Power",
.active_low = 0, .active_low = 0,
.wakeup = 1,
}, },
{ {
.gpio = S3C2410_GPG(9), .gpio = S3C2410_GPG(9),
...@@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = { ...@@ -264,6 +268,14 @@ static struct s3c24xx_led_platdata n30_blue_led_pdata = {
.def_trigger = "", .def_trigger = "",
}; };
/* This is the blue LED on the device. Originaly used to indicate GPS activity
* by flashing. */
static struct s3c24xx_led_platdata n35_blue_led_pdata = {
.name = "blue_led",
.gpio = S3C2410_GPD(8),
.def_trigger = "",
};
/* This LED is driven by the battery microcontroller, and is blinking /* This LED is driven by the battery microcontroller, and is blinking
* red, blinking green or solid green when the battery is low, * red, blinking green or solid green when the battery is low,
* charging or full respectively. By driving GPD9 low, it's possible * charging or full respectively. By driving GPD9 low, it's possible
...@@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = { ...@@ -275,6 +287,13 @@ static struct s3c24xx_led_platdata n30_warning_led_pdata = {
.def_trigger = "", .def_trigger = "",
}; };
static struct s3c24xx_led_platdata n35_warning_led_pdata = {
.name = "warning_led",
.flags = S3C24XX_LEDF_ACTLOW | S3C24XX_LEDF_TRISTATE,
.gpio = S3C2410_GPD(9),
.def_trigger = "",
};
static struct platform_device n30_blue_led = { static struct platform_device n30_blue_led = {
.name = "s3c24xx_led", .name = "s3c24xx_led",
.id = 1, .id = 1,
...@@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = { ...@@ -283,6 +302,14 @@ static struct platform_device n30_blue_led = {
}, },
}; };
static struct platform_device n35_blue_led = {
.name = "s3c24xx_led",
.id = 1,
.dev = {
.platform_data = &n35_blue_led_pdata,
},
};
static struct platform_device n30_warning_led = { static struct platform_device n30_warning_led = {
.name = "s3c24xx_led", .name = "s3c24xx_led",
.id = 2, .id = 2,
...@@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = { ...@@ -291,6 +318,14 @@ static struct platform_device n30_warning_led = {
}, },
}; };
static struct platform_device n35_warning_led = {
.name = "s3c24xx_led",
.id = 2,
.dev = {
.platform_data = &n35_warning_led_pdata,
},
};
static struct s3c2410fb_display n30_display __initdata = { static struct s3c2410fb_display n30_display __initdata = {
.type = S3C2410_LCDCON1_TFT, .type = S3C2410_LCDCON1_TFT,
.width = 240, .width = 240,
...@@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = { ...@@ -317,13 +352,36 @@ static struct s3c2410fb_mach_info n30_fb_info __initdata = {
.lpcsel = 0x06, .lpcsel = 0x06,
}; };
static void n30_sdi_set_power(unsigned char power_mode, unsigned short vdd)
{
switch (power_mode) {
case MMC_POWER_ON:
case MMC_POWER_UP:
gpio_set_value(S3C2410_GPG(4), 1);
break;
case MMC_POWER_OFF:
default:
gpio_set_value(S3C2410_GPG(4), 0);
break;
}
}
static struct s3c24xx_mci_pdata n30_mci_cfg __initdata = {
.gpio_detect = S3C2410_GPF(1),
.gpio_wprotect = S3C2410_GPG(10),
.ocr_avail = MMC_VDD_32_33,
.set_power = n30_sdi_set_power,
};
static struct platform_device *n30_devices[] __initdata = { static struct platform_device *n30_devices[] __initdata = {
&s3c_device_lcd, &s3c_device_lcd,
&s3c_device_wdt, &s3c_device_wdt,
&s3c_device_i2c0, &s3c_device_i2c0,
&s3c_device_iis, &s3c_device_iis,
&s3c_device_ohci, &s3c_device_ohci,
&s3c_device_rtc,
&s3c_device_usbgadget, &s3c_device_usbgadget,
&s3c_device_sdi,
&n30_button_device, &n30_button_device,
&n30_blue_led, &n30_blue_led,
&n30_warning_led, &n30_warning_led,
...@@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = { ...@@ -334,8 +392,12 @@ static struct platform_device *n35_devices[] __initdata = {
&s3c_device_wdt, &s3c_device_wdt,
&s3c_device_i2c0, &s3c_device_i2c0,
&s3c_device_iis, &s3c_device_iis,
&s3c_device_rtc,
&s3c_device_usbgadget, &s3c_device_usbgadget,
&s3c_device_sdi,
&n35_button_device, &n35_button_device,
&n35_blue_led,
&n35_warning_led,
}; };
static struct s3c2410_platform_i2c __initdata n30_i2ccfg = { static struct s3c2410_platform_i2c __initdata n30_i2ccfg = {
...@@ -490,17 +552,15 @@ static void __init n30_map_io(void) ...@@ -490,17 +552,15 @@ static void __init n30_map_io(void)
s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs)); s3c24xx_init_uarts(n30_uartcfgs, ARRAY_SIZE(n30_uartcfgs));
} }
static void __init n30_init_irq(void)
{
s3c24xx_init_irq();
}
/* GPB3 is the line that controls the pull-up for the USB D+ line */ /* GPB3 is the line that controls the pull-up for the USB D+ line */
static void __init n30_init(void) static void __init n30_init(void)
{ {
WARN_ON(gpio_request(S3C2410_GPG(4), "mmc power"));
s3c24xx_fb_set_platdata(&n30_fb_info); s3c24xx_fb_set_platdata(&n30_fb_info);
s3c24xx_udc_set_platdata(&n30_udc_cfg); s3c24xx_udc_set_platdata(&n30_udc_cfg);
s3c24xx_mci_set_platdata(&n30_mci_cfg);
s3c_i2c0_set_platdata(&n30_i2ccfg); s3c_i2c0_set_platdata(&n30_i2ccfg);
/* Turn off suspend on both USB ports, and switch the /* Turn off suspend on both USB ports, and switch the
...@@ -532,7 +592,7 @@ static void __init n30_init(void) ...@@ -532,7 +592,7 @@ static void __init n30_init(void)
s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST | s3c2410_modify_misccr(S3C2410_MISCCR_USBHOST |
S3C2410_MISCCR_USBSUSPND0 | S3C2410_MISCCR_USBSUSPND0 |
S3C2410_MISCCR_USBSUSPND1, S3C2410_MISCCR_USBSUSPND1,
S3C2410_MISCCR_USBSUSPND1); S3C2410_MISCCR_USBSUSPND0);
platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices)); platform_add_devices(n35_devices, ARRAY_SIZE(n35_devices));
} }
...@@ -550,7 +610,7 @@ MACHINE_START(N30, "Acer-N30") ...@@ -550,7 +610,7 @@ MACHINE_START(N30, "Acer-N30")
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
.timer = &s3c24xx_timer, .timer = &s3c24xx_timer,
.init_machine = n30_init, .init_machine = n30_init,
.init_irq = n30_init_irq, .init_irq = s3c24xx_init_irq,
.map_io = n30_map_io, .map_io = n30_map_io,
MACHINE_END MACHINE_END
...@@ -562,6 +622,6 @@ MACHINE_START(N35, "Acer-N35") ...@@ -562,6 +622,6 @@ MACHINE_START(N35, "Acer-N35")
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
.timer = &s3c24xx_timer, .timer = &s3c24xx_timer,
.init_machine = n30_init, .init_machine = n30_init,
.init_irq = n30_init_irq, .init_irq = s3c24xx_init_irq,
.map_io = n30_map_io, .map_io = n30_map_io,
MACHINE_END MACHINE_END
...@@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void) ...@@ -60,10 +60,10 @@ static void s3c2410_pm_prepare(void)
__raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM)); __raw_writel(calc, phys_to_virt(H1940_SUSPEND_CHECKSUM));
} }
/* the RX3715 uses similar code and the same H1940 and the /* RX3715 and RX1950 use similar to H1940 code and the
* same offsets for resume and checksum pointers */ * same offsets for resume and checksum pointers */
if (machine_is_rx3715()) { if (machine_is_rx3715() || machine_is_rx1950()) {
void *base = phys_to_virt(H1940_SUSPEND_CHECK); void *base = phys_to_virt(H1940_SUSPEND_CHECK);
unsigned long ptr; unsigned long ptr;
unsigned long calc = 0; unsigned long calc = 0;
...@@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void) ...@@ -79,6 +79,17 @@ static void s3c2410_pm_prepare(void)
if ( machine_is_aml_m5900() ) if ( machine_is_aml_m5900() )
s3c2410_gpio_setpin(S3C2410_GPF(2), 1); s3c2410_gpio_setpin(S3C2410_GPF(2), 1);
if (machine_is_rx1950()) {
/* According to S3C2442 user's manual, page 7-17,
* when the system is operating in NAND boot mode,
* the hardware pin configuration - EINT[23:21] –
* must be set as input for starting up after
* wakeup from sleep mode
*/
s3c_gpio_cfgpin(S3C2410_GPG(13), S3C2410_GPIO_INPUT);
s3c_gpio_cfgpin(S3C2410_GPG(14), S3C2410_GPIO_INPUT);
s3c_gpio_cfgpin(S3C2410_GPG(15), S3C2410_GPIO_INPUT);
}
} }
static int s3c2410_pm_resume(struct sys_device *dev) static int s3c2410_pm_resume(struct sys_device *dev)
......
...@@ -16,41 +16,43 @@ ...@@ -16,41 +16,43 @@
#include <linux/types.h> #include <linux/types.h>
#include <linux/module.h> #include <linux/module.h>
#include <linux/interrupt.h> #include <linux/interrupt.h>
#include <linux/gpio.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
#include <mach/regs-gpio.h> #include <mach/regs-gpio.h>
#include <mach/hardware.h> #include <mach/hardware.h>
#include <plat/gpio-core.h>
int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state) int s3c2412_gpio_set_sleepcfg(unsigned int pin, unsigned int state)
{ {
void __iomem *base = S3C24XX_GPIO_BASE(pin); struct s3c_gpio_chip *chip = s3c_gpiolib_getchip(pin);
unsigned long offs = S3C2410_GPIO_OFFSET(pin); unsigned long offs = pin - chip->chip.base;
unsigned long flags; unsigned long flags;
unsigned long slpcon; unsigned long slpcon;
offs *= 2; offs *= 2;
if (pin < S3C2410_GPIO_BANKB) if (pin < S3C2410_GPB(0))
return -EINVAL; return -EINVAL;
if (pin >= S3C2410_GPIO_BANKF && if (pin >= S3C2410_GPF(0) &&
pin <= S3C2410_GPIO_BANKG) pin <= S3C2410_GPG(16))
return -EINVAL; return -EINVAL;
if (pin > (S3C2410_GPIO_BANKH + 32)) if (pin > S3C2410_GPH(16))
return -EINVAL; return -EINVAL;
local_irq_save(flags); local_irq_save(flags);
slpcon = __raw_readl(base + 0x0C); slpcon = __raw_readl(chip->base + 0x0C);
slpcon &= ~(3 << offs); slpcon &= ~(3 << offs);
slpcon |= state << offs; slpcon |= state << offs;
__raw_writel(slpcon, base + 0x0C); __raw_writel(slpcon, chip->base + 0x0C);
local_irq_restore(flags); local_irq_restore(flags);
......
...@@ -674,7 +674,7 @@ static void __init jive_machine_init(void) ...@@ -674,7 +674,7 @@ static void __init jive_machine_init(void)
} }
MACHINE_START(JIVE, "JIVE") MACHINE_START(JIVE, "JIVE")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void) ...@@ -150,7 +150,7 @@ static void __init smdk2413_machine_init(void)
} }
MACHINE_START(S3C2413, "S3C2413") MACHINE_START(S3C2413, "S3C2413")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
...@@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413") ...@@ -163,7 +163,7 @@ MACHINE_START(S3C2413, "S3C2413")
MACHINE_END MACHINE_END
MACHINE_START(SMDK2412, "SMDK2412") MACHINE_START(SMDK2412, "SMDK2412")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
...@@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412") ...@@ -176,7 +176,7 @@ MACHINE_START(SMDK2412, "SMDK2412")
MACHINE_END MACHINE_END
MACHINE_START(SMDK2413, "SMDK2413") MACHINE_START(SMDK2413, "SMDK2413")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -30,6 +30,7 @@ menu "S3C2416 Machines" ...@@ -30,6 +30,7 @@ menu "S3C2416 Machines"
config MACH_SMDK2416 config MACH_SMDK2416
bool "SMDK2416" bool "SMDK2416"
select CPU_S3C2416 select CPU_S3C2416
select S3C_DEV_FB
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC1
help help
......
...@@ -22,6 +22,7 @@ ...@@ -22,6 +22,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/mtd/partitions.h> #include <linux/mtd/partitions.h>
#include <linux/gpio.h> #include <linux/gpio.h>
#include <linux/fb.h>
#include <asm/mach/arch.h> #include <asm/mach/arch.h>
#include <asm/mach/map.h> #include <asm/mach/map.h>
...@@ -36,16 +37,19 @@ ...@@ -36,16 +37,19 @@
#include <mach/regs-lcd.h> #include <mach/regs-lcd.h>
#include <mach/idle.h> #include <mach/idle.h>
#include <mach/fb.h>
#include <mach/leds-gpio.h> #include <mach/leds-gpio.h>
#include <plat/iic.h> #include <plat/iic.h>
#include <plat/s3c2416.h> #include <plat/s3c2416.h>
#include <plat/gpio-cfg.h>
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/devs.h> #include <plat/devs.h>
#include <plat/cpu.h> #include <plat/cpu.h>
#include <plat/nand.h> #include <plat/nand.h>
#include <plat/regs-fb-v4.h>
#include <plat/fb.h>
#include <plat/common-smdk.h> #include <plat/common-smdk.h>
static struct map_desc smdk2416_iodesc[] __initdata = { static struct map_desc smdk2416_iodesc[] __initdata = {
...@@ -109,7 +113,54 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = { ...@@ -109,7 +113,54 @@ static struct s3c2410_uartcfg smdk2416_uartcfgs[] __initdata = {
} }
}; };
struct s3c_fb_pd_win smdk2416_fb_win[] = {
[0] = {
/* think this is the same as the smdk6410 */
.win_mode = {
.pixclock = 41094,
.left_margin = 8,
.right_margin = 13,
.upper_margin = 7,
.lower_margin = 5,
.hsync_len = 3,
.vsync_len = 1,
.xres = 800,
.yres = 480,
},
.default_bpp = 16,
.max_bpp = 32,
},
};
static void s3c2416_fb_gpio_setup_24bpp(void)
{
unsigned int gpio;
for (gpio = S3C2410_GPC(1); gpio <= S3C2410_GPC(4); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPC(8); gpio <= S3C2410_GPC(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
for (gpio = S3C2410_GPD(0); gpio <= S3C2410_GPD(15); gpio++) {
s3c_gpio_cfgpin(gpio, S3C_GPIO_SFN(2));
s3c_gpio_setpull(gpio, S3C_GPIO_PULL_NONE);
}
}
static struct s3c_fb_platdata smdk2416_fb_platdata = {
.win[0] = &smdk2416_fb_win[0],
.setup_gpio = s3c2416_fb_gpio_setup_24bpp,
.vidcon0 = VIDCON0_VIDOUT_RGB | VIDCON0_PNRMODE_RGB,
.vidcon1 = VIDCON1_INV_HSYNC | VIDCON1_INV_VSYNC,
};
static struct platform_device *smdk2416_devices[] __initdata = { static struct platform_device *smdk2416_devices[] __initdata = {
&s3c_device_fb,
&s3c_device_wdt, &s3c_device_wdt,
&s3c_device_ohci, &s3c_device_ohci,
&s3c_device_i2c0, &s3c_device_i2c0,
...@@ -119,20 +170,25 @@ static struct platform_device *smdk2416_devices[] __initdata = { ...@@ -119,20 +170,25 @@ static struct platform_device *smdk2416_devices[] __initdata = {
static void __init smdk2416_map_io(void) static void __init smdk2416_map_io(void)
{ {
s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc)); s3c24xx_init_io(smdk2416_iodesc, ARRAY_SIZE(smdk2416_iodesc));
s3c24xx_init_clocks(12000000); s3c24xx_init_clocks(12000000);
s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs)); s3c24xx_init_uarts(smdk2416_uartcfgs, ARRAY_SIZE(smdk2416_uartcfgs));
} }
static void __init smdk2416_machine_init(void) static void __init smdk2416_machine_init(void)
{ {
s3c_i2c0_set_platdata(NULL); s3c_i2c0_set_platdata(NULL);
s3c_fb_set_platdata(&smdk2416_fb_platdata);
gpio_request(S3C2410_GPB(4), "USBHost Power"); gpio_request(S3C2410_GPB(4), "USBHost Power");
gpio_direction_output(S3C2410_GPB(4), 1); gpio_direction_output(S3C2410_GPB(4), 1);
gpio_request(S3C2410_GPB(3), "Display Power");
gpio_direction_output(S3C2410_GPB(3), 1);
gpio_request(S3C2410_GPB(1), "Display Reset");
gpio_direction_output(S3C2410_GPB(1), 1);
platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices)); platform_add_devices(smdk2416_devices, ARRAY_SIZE(smdk2416_devices));
smdk_machine_init(); smdk_machine_init();
} }
......
...@@ -90,6 +90,8 @@ int __init s3c2416_init(void) ...@@ -90,6 +90,8 @@ int __init s3c2416_init(void)
s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c");
s3c_device_fb.name = "s3c2443-fb";
return sysdev_register(&s3c2416_sysdev); return sysdev_register(&s3c2416_sysdev);
} }
......
...@@ -188,4 +188,17 @@ config MACH_MINI2440 ...@@ -188,4 +188,17 @@ config MACH_MINI2440
Say Y here to select support for the MINI2440. Is a 10cm x 10cm board Say Y here to select support for the MINI2440. Is a 10cm x 10cm board
available via various sources. It can come with a 3.5" or 7" touch LCD. available via various sources. It can come with a 3.5" or 7" touch LCD.
config MACH_RX1950
bool "HP iPAQ rx1950"
select CPU_S3C2442
select S3C24XX_DCLK
select PM_H1940 if PM
select I2C
select S3C2410_PWM
select S3C_DEV_NAND
select S3C2410_IOTIMING if S3C2440_CPUFREQ
select S3C2440_XTAL_16934400
help
Say Y here if you're using HP iPAQ rx1950
endmenu endmenu
...@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o ...@@ -34,6 +34,7 @@ obj-$(CONFIG_MACH_NEXCODER_2440) += mach-nexcoder.o
obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o obj-$(CONFIG_MACH_AT2440EVB) += mach-at2440evb.o
obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o obj-$(CONFIG_MACH_MINI2440) += mach-mini2440.o
obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o obj-$(CONFIG_MACH_NEO1973_GTA02) += mach-gta02.o
obj-$(CONFIG_MACH_RX1950) += mach-rx1950.o
# extra machine support # extra machine support
......
This diff is collapsed.
...@@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void) ...@@ -209,7 +209,7 @@ static void __init rx3715_init_machine(void)
} }
MACHINE_START(RX3715, "IPAQ-RX3715") MACHINE_START(RX3715, "IPAQ-RX3715")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void) ...@@ -174,7 +174,7 @@ static void __init smdk2440_machine_init(void)
} }
MACHINE_START(S3C2440, "SMDK2440") MACHINE_START(S3C2440, "SMDK2440")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void) ...@@ -131,7 +131,7 @@ static void __init smdk2443_machine_init(void)
} }
MACHINE_START(SMDK2443, "SMDK2443") MACHINE_START(SMDK2443, "SMDK2443")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C2410_PA_UART, .phys_io = S3C2410_PA_UART,
.io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C24XX_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C2410_SDRAM_PA + 0x100, .boot_params = S3C2410_SDRAM_PA + 0x100,
......
...@@ -85,6 +85,7 @@ config MACH_ANW6410 ...@@ -85,6 +85,7 @@ config MACH_ANW6410
config MACH_SMDK6410 config MACH_SMDK6410
bool "SMDK6410" bool "SMDK6410"
select CPU_S3C6410 select CPU_S3C6410
select SAMSUNG_DEV_ADC
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC1
select S3C_DEV_I2C1 select S3C_DEV_I2C1
......
...@@ -56,7 +56,6 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o ...@@ -56,7 +56,6 @@ obj-$(CONFIG_MACH_HMT) += mach-hmt.o
# device support # device support
obj-y += dev-uart.o obj-y += dev-uart.o
obj-y += dev-rtc.o
obj-y += dev-audio.o obj-y += dev-audio.o
obj-$(CONFIG_S3C_ADC) += dev-adc.o
obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o obj-$(CONFIG_S3C64XX_DEV_SPI) += dev-spi.o
obj-$(CONFIG_S3C64XX_DEV_TS) += dev-ts.o
...@@ -88,6 +88,12 @@ struct clk clk_48m = { ...@@ -88,6 +88,12 @@ struct clk clk_48m = {
.enable = clk_48m_ctrl, .enable = clk_48m_ctrl,
}; };
struct clk clk_xusbxti = {
.name = "xusbxti",
.id = -1,
.rate = 48000000,
};
static int inline s3c64xx_gate(void __iomem *reg, static int inline s3c64xx_gate(void __iomem *reg,
struct clk *clk, struct clk *clk,
int enable) int enable)
...@@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = { ...@@ -518,6 +524,11 @@ static struct clk clk_iis_cd1 = {
.id = -1, .id = -1,
}; };
static struct clk clk_iisv4_cd = {
.name = "iis_cdclk_v4",
.id = -1,
};
static struct clk clk_pcm_cd = { static struct clk clk_pcm_cd = {
.name = "pcm_cdclk", .name = "pcm_cdclk",
.id = -1, .id = -1,
...@@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = { ...@@ -549,6 +560,19 @@ static struct clksrc_sources clkset_audio1 = {
.nr_sources = ARRAY_SIZE(clkset_audio1_list), .nr_sources = ARRAY_SIZE(clkset_audio1_list),
}; };
static struct clk *clkset_audio2_list[] = {
[0] = &clk_mout_epll.clk,
[1] = &clk_dout_mpll,
[2] = &clk_fin_epll,
[3] = &clk_iisv4_cd,
[4] = &clk_pcm_cd,
};
static struct clksrc_sources clkset_audio2 = {
.sources = clkset_audio2_list,
.nr_sources = ARRAY_SIZE(clkset_audio2_list),
};
static struct clk *clkset_camif_list[] = { static struct clk *clkset_camif_list[] = {
&clk_h2, &clk_h2,
}; };
...@@ -650,6 +674,16 @@ static struct clksrc_clk clksrcs[] = { ...@@ -650,6 +674,16 @@ static struct clksrc_clk clksrcs[] = {
.reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 }, .reg_src = { .reg = S3C_CLK_SRC, .shift = 10, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 }, .reg_div = { .reg = S3C_CLK_DIV2, .shift = 12, .size = 4 },
.sources = &clkset_audio1, .sources = &clkset_audio1,
}, {
.clk = {
.name = "audio-bus",
.id = -1, /* There's only one IISv4 port */
.ctrlbit = S3C6410_CLKCON_SCLK_AUDIO2,
.enable = s3c64xx_sclk_ctrl,
},
.reg_src = { .reg = S3C6410_CLK_SRC2, .shift = 0, .size = 3 },
.reg_div = { .reg = S3C_CLK_DIV2, .shift = 24, .size = 4 },
.sources = &clkset_audio2,
}, { }, {
.clk = { .clk = {
.name = "irda-bus", .name = "irda-bus",
...@@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = { ...@@ -749,6 +783,7 @@ static struct clk *clks1[] __initdata = {
&clk_ext_xtal_mux, &clk_ext_xtal_mux,
&clk_iis_cd0, &clk_iis_cd0,
&clk_iis_cd1, &clk_iis_cd1,
&clk_iisv4_cd,
&clk_pcm_cd, &clk_pcm_cd,
&clk_mout_epll.clk, &clk_mout_epll.clk,
&clk_mout_mpll.clk, &clk_mout_mpll.clk,
...@@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = { ...@@ -762,6 +797,7 @@ static struct clk *clks[] __initdata = {
&clk_27m, &clk_27m,
&clk_48m, &clk_48m,
&clk_h2, &clk_h2,
&clk_xusbxti,
}; };
/** /**
......
...@@ -414,7 +414,7 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id, ...@@ -414,7 +414,7 @@ int s3c2410_dma_enqueue(unsigned int channel, void *id,
EXPORT_SYMBOL(s3c2410_dma_enqueue); EXPORT_SYMBOL(s3c2410_dma_enqueue);
int s3c2410_dma_devconfig(int channel, int s3c2410_dma_devconfig(unsigned int channel,
enum s3c2410_dmasrc source, enum s3c2410_dmasrc source,
unsigned long devaddr) unsigned long devaddr)
{ {
......
...@@ -103,5 +103,8 @@ ...@@ -103,5 +103,8 @@
#define S3C_PA_USBHOST S3C64XX_PA_USBHOST #define S3C_PA_USBHOST S3C64XX_PA_USBHOST
#define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG #define S3C_PA_USB_HSOTG S3C64XX_PA_USB_HSOTG
#define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY #define S3C_VA_USB_HSPHY S3C64XX_VA_USB_HSPHY
#define S3C_PA_RTC S3C64XX_PA_RTC
#define SAMSUNG_PA_ADC S3C64XX_PA_ADC
#endif /* __ASM_ARCH_6400_MAP_H */ #endif /* __ASM_ARCH_6400_MAP_H */
...@@ -33,6 +33,7 @@ ...@@ -33,6 +33,7 @@
#define S3C_PCLK_GATE S3C_CLKREG(0x34) #define S3C_PCLK_GATE S3C_CLKREG(0x34)
#define S3C_SCLK_GATE S3C_CLKREG(0x38) #define S3C_SCLK_GATE S3C_CLKREG(0x38)
#define S3C_MEM0_GATE S3C_CLKREG(0x3C) #define S3C_MEM0_GATE S3C_CLKREG(0x3C)
#define S3C6410_CLK_SRC2 S3C_CLKREG(0x10C)
/* CLKDIV0 */ /* CLKDIV0 */
#define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12) #define S3C6400_CLKDIV0_PCLK_MASK (0xf << 12)
......
...@@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void) ...@@ -84,7 +84,7 @@ static void __init smdk6400_machine_init(void)
} }
MACHINE_START(SMDK6400, "SMDK6400") MACHINE_START(SMDK6400, "SMDK6400")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000, .phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100, .boot_params = S3C64XX_PA_SDRAM + 0x100,
......
...@@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void) ...@@ -656,7 +656,7 @@ static void __init smdk6410_machine_init(void)
} }
MACHINE_START(SMDK6410, "SMDK6410") MACHINE_START(SMDK6410, "SMDK6410")
/* Maintainer: Ben Dooks <ben@fluff.org> */ /* Maintainer: Ben Dooks <ben-linux@fluff.org> */
.phys_io = S3C_PA_UART & 0xfff00000, .phys_io = S3C_PA_UART & 0xfff00000,
.io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc, .io_pg_offst = (((u32)S3C_VA_UART) >> 18) & 0xfffc,
.boot_params = S3C64XX_PA_SDRAM + 0x100, .boot_params = S3C64XX_PA_SDRAM + 0x100,
......
...@@ -38,6 +38,7 @@ ...@@ -38,6 +38,7 @@
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/sdhci.h> #include <plat/sdhci.h>
#include <plat/iic-core.h> #include <plat/iic-core.h>
#include <plat/adc.h>
#include <mach/s3c6400.h> #include <mach/s3c6400.h>
#include <mach/s3c6410.h> #include <mach/s3c6410.h>
...@@ -52,6 +53,7 @@ void __init s3c6410_map_io(void) ...@@ -52,6 +53,7 @@ void __init s3c6410_map_io(void)
s3c_i2c0_setname("s3c2440-i2c"); s3c_i2c0_setname("s3c2440-i2c");
s3c_i2c1_setname("s3c2440-i2c"); s3c_i2c1_setname("s3c2440-i2c");
s3c_device_adc.name = "s3c64xx-adc";
s3c_device_nand.name = "s3c6400-nand"; s3c_device_nand.name = "s3c6400-nand";
} }
......
...@@ -9,6 +9,7 @@ if ARCH_S5P6440 ...@@ -9,6 +9,7 @@ if ARCH_S5P6440
config CPU_S5P6440 config CPU_S5P6440
bool bool
select S3C_PL330_DMA
help help
Enable S5P6440 CPU support Enable S5P6440 CPU support
......
...@@ -12,8 +12,12 @@ obj- := ...@@ -12,8 +12,12 @@ obj- :=
# Core support for S5P6440 system # Core support for S5P6440 system
obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o obj-$(CONFIG_CPU_S5P6440) += cpu.o init.o clock.o gpio.o dma.o
obj-$(CONFIG_CPU_S5P6440) += setup-i2c0.o
# machine support # machine support
obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o obj-$(CONFIG_MACH_SMDK6440) += mach-smdk6440.o
# device support
obj-y += dev-audio.o
This diff is collapsed.
...@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void) ...@@ -88,7 +88,7 @@ void __init s5p6440_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic)); s5p_init_irq(vic, ARRAY_SIZE(vic));
} }
static struct sysdev_class s5p6440_sysclass = { struct sysdev_class s5p6440_sysclass = {
.name = "s5p6440-core", .name = "s5p6440-core",
}; };
......
/* linux/arch/arm/mach-s5p6440/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/gpio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6440_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case -1:
s3c_gpio_cfgpin(S5P6440_GPR(4), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(5), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(5));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(5));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5p6440_cfg_i2s,
};
static struct resource s5p6440_iis0_resource[] = {
[0] = {
.start = S5P6440_PA_I2S,
.end = S5P6440_PA_I2S + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_iis = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6440_iis0_resource),
.resource = s5p6440_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6440_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6440_GPR(7), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(13), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(14), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(8), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6440_GPR(6), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6440_pcm_cfg_gpio,
};
static struct resource s5p6440_pcm0_resource[] = {
[0] = {
.start = S5P6440_PA_PCM,
.end = S5P6440_PA_PCM + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6440_device_pcm = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6440_pcm0_resource),
.resource = s5p6440_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6440_pdma_resource[] = {
[0] = {
.start = S5P6440_PA_PDMA,
.end = S5P6440_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_DMA0,
.end = IRQ_DMA0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6440_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_MAX,
[10] = DMACH_PCM0_TX,
[11] = DMACH_PCM0_RX,
[12] = DMACH_I2S0_TX,
[13] = DMACH_I2S0_RX,
[14] = DMACH_SPI0_TX,
[15] = DMACH_SPI0_RX,
[16] = DMACH_MAX,
[17] = DMACH_MAX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_SPI1_TX,
[21] = DMACH_SPI1_RX,
[22] = DMACH_MAX,
[23] = DMACH_MAX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MAX,
[28] = DMACH_MAX,
[29] = DMACH_PWM,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6440_device_pdma = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6440_pdma_resource),
.resource = s5p6440_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6440_pdma_pdata,
},
};
static struct platform_device *s5p6440_dmacs[] __initdata = {
&s5p6440_device_pdma,
};
static int __init s5p6440_dma_init(void)
{
platform_add_devices(s5p6440_dmacs, ARRAY_SIZE(s5p6440_dmacs));
return 0;
}
arch_initcall(s5p6440_dma_init);
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */
...@@ -29,6 +29,8 @@ ...@@ -29,6 +29,8 @@
#define S5P6440_PA_VIC0 (0xE4000000) #define S5P6440_PA_VIC0 (0xE4000000)
#define S5P_PA_VIC0 S5P6440_PA_VIC0 #define S5P_PA_VIC0 S5P6440_PA_VIC0
#define S5P6440_PA_PDMA 0xE9000000
#define S5P6440_PA_VIC1 (0xE4100000) #define S5P6440_PA_VIC1 (0xE4100000)
#define S5P_PA_VIC1 S5P6440_PA_VIC1 #define S5P_PA_VIC1 S5P6440_PA_VIC1
...@@ -61,6 +63,12 @@ ...@@ -61,6 +63,12 @@
#define S5P6440_PA_SDRAM (0x20000000) #define S5P6440_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6440_PA_SDRAM #define S5P_PA_SDRAM S5P6440_PA_SDRAM
/* I2S */
#define S5P6440_PA_I2S 0xF2000000
/* PCM */
#define S5P6440_PA_PCM 0xF2100000
/* compatibiltiy defines. */ /* compatibiltiy defines. */
#define S3C_PA_UART S5P6440_PA_UART #define S3C_PA_UART S5P6440_PA_UART
#define S3C_PA_IIC S5P6440_PA_IIC0 #define S3C_PA_IIC S5P6440_PA_IIC0
......
/* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h /* linux/arch/arm/mach-s5p6440/include/mach/pwm-clock.h
* *
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk> * Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/ * http://armlinux.simtec.co.uk/
* *
* Copyright 2009 Samsung Electronics Co., Ltd. * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
* http://www.samsung.com/
* *
* S5P6440 - pwm clock and timer support * S5P6440 - pwm clock and timer support
* *
...@@ -14,16 +17,19 @@ ...@@ -14,16 +17,19 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_PWMCLK_H
#define __ASM_ARCH_PWMCLK_H __FILE__
/** /**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0. * @tcfg: The timer TCFG1 register bits shifted down to 0.
* *
* Return true if the given configuration from TCFG1 is a TCLK instead * Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks. * any of the TDIV clocks.
*/ */
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{ {
return tcfg == S3C2410_TCFG1_MUX_TCLK; return 0;
} }
/** /**
...@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) ...@@ -35,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/ */
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{ {
return 1 << (1 + tcfg1); return 1 << tcfg1;
} }
/** /**
...@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) ...@@ -45,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/ */
static inline unsigned int pwm_tdiv_has_div1(void) static inline unsigned int pwm_tdiv_has_div1(void)
{ {
return 0; return 1;
} }
/** /**
...@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) ...@@ -56,7 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/ */
static inline unsigned long pwm_tdiv_div_bits(unsigned int div) static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{ {
return ilog2(div) - 1; return ilog2(div);
} }
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK #define S3C_TCFG1_MUX_TCLK 0
#endif /* __ASM_ARCH_PWMCLK_H */
...@@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = { ...@@ -84,6 +84,7 @@ static struct s3c2410_uartcfg smdk6440_uartcfgs[] __initdata = {
}; };
static struct platform_device *smdk6440_devices[] __initdata = { static struct platform_device *smdk6440_devices[] __initdata = {
&s5p6440_device_iis,
}; };
static void __init smdk6440_map_io(void) static void __init smdk6440_map_io(void)
......
/* linux/arch/arm/plat-s5p/setup-i2c0.c /* linux/arch/arm/mach-s5p6440/setup-i2c0.c
* *
* Copyright (c) 2009 Samsung Electronics Co., Ltd. * Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/ * http://www.samsung.com/
......
...@@ -12,6 +12,7 @@ if ARCH_S5P6442 ...@@ -12,6 +12,7 @@ if ARCH_S5P6442
config CPU_S5P6442 config CPU_S5P6442
bool bool
select PLAT_S5P select PLAT_S5P
select S3C_PL330_DMA
help help
Enable S5P6442 CPU support Enable S5P6442 CPU support
......
...@@ -12,8 +12,12 @@ obj- := ...@@ -12,8 +12,12 @@ obj- :=
# Core support for S5P6442 system # Core support for S5P6442 system
obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o obj-$(CONFIG_CPU_S5P6442) += cpu.o init.o clock.o dma.o
obj-$(CONFIG_CPU_S5P6442) += setup-i2c0.o
# machine support # machine support
obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o obj-$(CONFIG_MACH_SMDK6442) += mach-smdk6442.o
# device support
obj-y += dev-audio.o
...@@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void) ...@@ -95,7 +95,7 @@ void __init s5p6442_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic)); s5p_init_irq(vic, ARRAY_SIZE(vic));
} }
static struct sysdev_class s5p6442_sysclass = { struct sysdev_class s5p6442_sysclass = {
.name = "s5p6442-core", .name = "s5p6442-core",
}; };
......
/* linux/arch/arm/mach-s5p6442/dev-audio.c
*
* Copyright (c) 2010 Samsung Electronics Co. Ltd
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/gpio-cfg.h>
#include <plat/audio.h>
#include <mach/gpio.h>
#include <mach/map.h>
#include <mach/dma.h>
#include <mach/irqs.h>
static int s5p6442_cfg_i2s(struct platform_device *pdev)
{
/* configure GPIO for i2s port */
switch (pdev->id) {
case 1:
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(2));
break;
case -1:
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(2));
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(2));
break;
default:
printk(KERN_ERR "Invalid Device %d\n", pdev->id);
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_i2s_pdata = {
.cfg_gpio = s5p6442_cfg_i2s,
};
static struct resource s5p6442_iis0_resource[] = {
[0] = {
.start = S5P6442_PA_I2S0,
.end = S5P6442_PA_I2S0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S0_TX,
.end = DMACH_I2S0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S0_RX,
.end = DMACH_I2S0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis0 = {
.name = "s3c64xx-iis-v4",
.id = -1,
.num_resources = ARRAY_SIZE(s5p6442_iis0_resource),
.resource = s5p6442_iis0_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
static struct resource s5p6442_iis1_resource[] = {
[0] = {
.start = S5P6442_PA_I2S1,
.end = S5P6442_PA_I2S1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_I2S1_TX,
.end = DMACH_I2S1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_I2S1_RX,
.end = DMACH_I2S1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_iis1 = {
.name = "s3c64xx-iis",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_iis1_resource),
.resource = s5p6442_iis1_resource,
.dev = {
.platform_data = &s3c_i2s_pdata,
},
};
/* PCM Controller platform_devices */
static int s5p6442_pcm_cfg_gpio(struct platform_device *pdev)
{
switch (pdev->id) {
case 0:
s3c_gpio_cfgpin(S5P6442_GPC0(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC0(4), S3C_GPIO_SFN(3));
break;
case 1:
s3c_gpio_cfgpin(S5P6442_GPC1(0), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(1), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(2), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(3), S3C_GPIO_SFN(3));
s3c_gpio_cfgpin(S5P6442_GPC1(4), S3C_GPIO_SFN(3));
break;
default:
printk(KERN_DEBUG "Invalid PCM Controller number!");
return -EINVAL;
}
return 0;
}
static struct s3c_audio_pdata s3c_pcm_pdata = {
.cfg_gpio = s5p6442_pcm_cfg_gpio,
};
static struct resource s5p6442_pcm0_resource[] = {
[0] = {
.start = S5P6442_PA_PCM0,
.end = S5P6442_PA_PCM0 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM0_TX,
.end = DMACH_PCM0_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM0_RX,
.end = DMACH_PCM0_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm0 = {
.name = "samsung-pcm",
.id = 0,
.num_resources = ARRAY_SIZE(s5p6442_pcm0_resource),
.resource = s5p6442_pcm0_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
static struct resource s5p6442_pcm1_resource[] = {
[0] = {
.start = S5P6442_PA_PCM1,
.end = S5P6442_PA_PCM1 + 0x100 - 1,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = DMACH_PCM1_TX,
.end = DMACH_PCM1_TX,
.flags = IORESOURCE_DMA,
},
[2] = {
.start = DMACH_PCM1_RX,
.end = DMACH_PCM1_RX,
.flags = IORESOURCE_DMA,
},
};
struct platform_device s5p6442_device_pcm1 = {
.name = "samsung-pcm",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pcm1_resource),
.resource = s5p6442_pcm1_resource,
.dev = {
.platform_data = &s3c_pcm_pdata,
},
};
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5p6442_pdma_resource[] = {
[0] = {
.start = S5P6442_PA_PDMA,
.end = S5P6442_PA_PDMA + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA,
.end = IRQ_PDMA,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5p6442_pdma_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_MAX,
[7] = DMACH_MAX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_MAX,
[19] = DMACH_MAX,
[20] = DMACH_PCM0_RX,
[21] = DMACH_PCM0_TX,
[22] = DMACH_PCM1_RX,
[23] = DMACH_PCM1_TX,
[24] = DMACH_MAX,
[25] = DMACH_MAX,
[26] = DMACH_MAX,
[27] = DMACH_MSM_REQ0,
[28] = DMACH_MSM_REQ1,
[29] = DMACH_MSM_REQ2,
[30] = DMACH_MSM_REQ3,
[31] = DMACH_MAX,
},
};
static struct platform_device s5p6442_device_pdma = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5p6442_pdma_resource),
.resource = s5p6442_pdma_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5p6442_pdma_pdata,
},
};
static struct platform_device *s5p6442_dmacs[] __initdata = {
&s5p6442_device_pdma,
};
static int __init s5p6442_dma_init(void)
{
platform_add_devices(s5p6442_dmacs, ARRAY_SIZE(s5p6442_dmacs));
return 0;
}
arch_initcall(s5p6442_dma_init);
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */
...@@ -34,6 +34,9 @@ ...@@ -34,6 +34,9 @@
#define S5P6442_PA_VIC2 (0xE4200000) #define S5P6442_PA_VIC2 (0xE4200000)
#define S5P_PA_VIC2 S5P6442_PA_VIC2 #define S5P_PA_VIC2 S5P6442_PA_VIC2
#define S5P6442_PA_MDMA 0xE8000000
#define S5P6442_PA_PDMA 0xE9000000
#define S5P6442_PA_TIMER (0xEA000000) #define S5P6442_PA_TIMER (0xEA000000)
#define S5P_PA_TIMER S5P6442_PA_TIMER #define S5P_PA_TIMER S5P6442_PA_TIMER
...@@ -51,6 +54,14 @@ ...@@ -51,6 +54,14 @@
#define S5P6442_PA_SDRAM (0x20000000) #define S5P6442_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5P6442_PA_SDRAM #define S5P_PA_SDRAM S5P6442_PA_SDRAM
/* I2S */
#define S5P6442_PA_I2S0 0xC0B00000
#define S5P6442_PA_I2S1 0xF2200000
/* PCM */
#define S5P6442_PA_PCM0 0xF2400000
#define S5P6442_PA_PCM1 0xF2500000
/* compatibiltiy defines. */ /* compatibiltiy defines. */
#define S3C_PA_UART S5P6442_PA_UART #define S3C_PA_UART S5P6442_PA_UART
#define S3C_PA_IIC S5P6442_PA_IIC0 #define S3C_PA_IIC S5P6442_PA_IIC0
......
/* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h /* linux/arch/arm/mach-s5p6442/include/mach/pwm-clock.h
* *
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* Copyright 2008 Openmoko, Inc.
* Copyright 2008 Simtec Electronics * Copyright 2008 Simtec Electronics
* Ben Dooks <ben@simtec.co.uk> * Ben Dooks <ben@simtec.co.uk>
* http://armlinux.simtec.co.uk/ * http://armlinux.simtec.co.uk/
* *
* Copyright 2010 Samsung Electronics Co., Ltd. * Based on arch/arm/mach-s3c64xx/include/mach/pwm-clock.h
* http://www.samsung.com/
*
* Based on arch/arm/plat-s3c24xx/include/mach/pwm-clock.h
* *
* S5P6442 - pwm clock and timer support * S5P6442 - pwm clock and timer support
* *
...@@ -21,14 +22,14 @@ ...@@ -21,14 +22,14 @@
/** /**
* pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk * pwm_cfg_src_is_tclk() - return whether the given mux config is a tclk
* @cfg: The timer TCFG1 register bits shifted down to 0. * @tcfg: The timer TCFG1 register bits shifted down to 0.
* *
* Return true if the given configuration from TCFG1 is a TCLK instead * Return true if the given configuration from TCFG1 is a TCLK instead
* any of the TDIV clocks. * any of the TDIV clocks.
*/ */
static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
{ {
return tcfg == S3C2410_TCFG1_MUX_TCLK; return tcfg == S3C64XX_TCFG1_MUX_TCLK;
} }
/** /**
...@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg) ...@@ -40,7 +41,7 @@ static inline int pwm_cfg_src_is_tclk(unsigned long tcfg)
*/ */
static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
{ {
return 1 << (1 + tcfg1); return 1 << tcfg1;
} }
/** /**
...@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1) ...@@ -50,7 +51,7 @@ static inline unsigned long tcfg_to_divisor(unsigned long tcfg1)
*/ */
static inline unsigned int pwm_tdiv_has_div1(void) static inline unsigned int pwm_tdiv_has_div1(void)
{ {
return 0; return 1;
} }
/** /**
...@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void) ...@@ -61,9 +62,9 @@ static inline unsigned int pwm_tdiv_has_div1(void)
*/ */
static inline unsigned long pwm_tdiv_div_bits(unsigned int div) static inline unsigned long pwm_tdiv_div_bits(unsigned int div)
{ {
return ilog2(div) - 1; return ilog2(div);
} }
#define S3C_TCFG1_MUX_TCLK S3C2410_TCFG1_MUX_TCLK #define S3C_TCFG1_MUX_TCLK S3C64XX_TCFG1_MUX_TCLK
#endif /* __ASM_ARCH_PWMCLK_H */ #endif /* __ASM_ARCH_PWMCLK_H */
...@@ -65,6 +65,7 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = { ...@@ -65,6 +65,7 @@ static struct s3c2410_uartcfg smdk6442_uartcfgs[] __initdata = {
}; };
static struct platform_device *smdk6442_devices[] __initdata = { static struct platform_device *smdk6442_devices[] __initdata = {
&s5p6442_device_iis0,
}; };
static void __init smdk6442_map_io(void) static void __init smdk6442_map_io(void)
......
/* linux/arch/arm/mach-s5p6442/setup-i2c0.c
*
* Copyright (c) 2009 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* I2C0 GPIO configuration.
*
* Based on plat-s3c64xx/setup-i2c0.c
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#include <linux/kernel.h>
#include <linux/types.h>
struct platform_device; /* don't need the contents */
#include <plat/iic.h>
void s3c_i2c0_cfg_gpio(struct platform_device *dev)
{
/* Will be populated later */
}
...@@ -12,12 +12,22 @@ config CPU_S5PC100 ...@@ -12,12 +12,22 @@ config CPU_S5PC100
help help
Enable S5PC100 CPU support Enable S5PC100 CPU support
config S5PC100_SETUP_FB_24BPP
bool
help
Common setup code for S5PC1XX with an 24bpp RGB display helper.
config S5PC100_SETUP_SDHCI config S5PC100_SETUP_SDHCI
bool bool
select S5PC1XX_SETUP_SDHCI_GPIO select S5PC1XX_SETUP_SDHCI_GPIO
help help
Internal helper functions for S5PC100 based SDHCI systems Internal helper functions for S5PC100 based SDHCI systems
config S5PC100_SETUP_I2C1
bool
help
Common setup code for i2c bus 1.
config MACH_SMDKC100 config MACH_SMDKC100
bool "SMDKC100" bool "SMDKC100"
select CPU_S5PC100 select CPU_S5PC100
...@@ -26,9 +36,8 @@ config MACH_SMDKC100 ...@@ -26,9 +36,8 @@ config MACH_SMDKC100
select S3C_DEV_HSMMC select S3C_DEV_HSMMC
select S3C_DEV_HSMMC1 select S3C_DEV_HSMMC1
select S3C_DEV_HSMMC2 select S3C_DEV_HSMMC2
select S5PC1XX_SETUP_I2C0 select S5PC100_SETUP_FB_24BPP
select S5PC1XX_SETUP_I2C1 select S5PC100_SETUP_I2C1
select S5PC1XX_SETUP_FB_24BPP
select S5PC100_SETUP_SDHCI select S5PC100_SETUP_SDHCI
help help
Machine support for the Samsung SMDKC100 Machine support for the Samsung SMDKC100
...@@ -11,10 +11,13 @@ obj- := ...@@ -11,10 +11,13 @@ obj- :=
# Core support for S5PC100 system # Core support for S5PC100 system
obj-$(CONFIG_CPU_S5PC100) += cpu.o obj-$(CONFIG_CPU_S5PC100) += cpu.o gpiolib.o
obj-$(CONFIG_CPU_S5PC100) += setup-i2c0.o
# Helper and device support # Helper and device support
obj-$(CONFIG_S5PC100_SETUP_FB_24BPP) += setup-fb-24bpp.o
obj-$(CONFIG_S5PC100_SETUP_I2C1) += setup-i2c1.o
obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o obj-$(CONFIG_S5PC100_SETUP_SDHCI) += setup-sdhci.o
# machine support # machine support
......
This diff is collapsed.
...@@ -17,11 +17,11 @@ ...@@ -17,11 +17,11 @@
#include <linux/gpio.h> #include <linux/gpio.h>
#include <mach/map.h> #include <mach/map.h>
#include <mach/regs-gpio.h>
#include <plat/gpio-core.h> #include <plat/gpio-core.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-helpers.h> #include <plat/gpio-cfg-helpers.h>
#include <plat/regs-gpio.h>
/* S5PC100 GPIO bank summary: /* S5PC100 GPIO bank summary:
* *
...@@ -61,74 +61,7 @@ ...@@ -61,74 +61,7 @@
* L3 8 4Bit None * L3 8 4Bit None
*/ */
#define OFF_GPCON (0x00) #if 0
#define OFF_GPDAT (0x04)
#define con_4bit_shift(__off) ((__off) * 4)
#if 1
#define gpio_dbg(x...) do { } while (0)
#else
#define gpio_dbg(x...) printk(KERN_DEBUG x)
#endif
/* The s5pc1xx_gpiolib routines are to control the gpio banks where
* the gpio configuration register (GPxCON) has 4 bits per GPIO, as the
* following example:
*
* base + 0x00: Control register, 4 bits per gpio
* gpio n: 4 bits starting at (4*n)
* 0000 = input, 0001 = output, others mean special-function
* base + 0x04: Data register, 1 bit per gpio
* bit n: data bit n
*
* Note, since the data register is one bit per gpio and is at base + 0x4
* we can use s3c_gpiolib_get and s3c_gpiolib_set to change the state of
* the output.
*/
static int s5pc1xx_gpiolib_input(struct gpio_chip *chip, unsigned offset)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
__raw_writel(con, base + OFF_GPCON);
gpio_dbg("%s: %p: CON now %08lx\n", __func__, base, con);
return 0;
}
static int s5pc1xx_gpiolib_output(struct gpio_chip *chip,
unsigned offset, int value)
{
struct s3c_gpio_chip *ourchip = to_s3c_gpio(chip);
void __iomem *base = ourchip->base;
unsigned long con;
unsigned long dat;
con = __raw_readl(base + OFF_GPCON);
con &= ~(0xf << con_4bit_shift(offset));
con |= 0x1 << con_4bit_shift(offset);
dat = __raw_readl(base + OFF_GPDAT);
if (value)
dat |= 1 << offset;
else
dat &= ~(1 << offset);
__raw_writel(dat, base + OFF_GPDAT);
__raw_writel(con, base + OFF_GPCON);
__raw_writel(dat, base + OFF_GPDAT);
gpio_dbg("%s: %p: CON %08lx, DAT %08lx\n", __func__, base, con, dat);
return 0;
}
static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset) static int s5pc1xx_gpiolib_to_irq(struct gpio_chip *chip, unsigned int offset)
{ {
return S3C_IRQ_GPIO(chip->base + offset); return S3C_IRQ_GPIO(chip->base + offset);
...@@ -152,7 +85,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset) ...@@ -152,7 +85,7 @@ static int s5pc1xx_gpiolib_to_eint(struct gpio_chip *chip, unsigned int offset)
return IRQ_EINT(24 + offset); return IRQ_EINT(24 + offset);
return -EINVAL; return -EINVAL;
} }
#endif
static struct s3c_gpio_cfg gpio_cfg = { static struct s3c_gpio_cfg gpio_cfg = {
.set_config = s3c_gpio_setcfg_s3c64xx_4bit, .set_config = s3c_gpio_setcfg_s3c64xx_4bit,
.set_pull = s3c_gpio_setpull_updown, .set_pull = s3c_gpio_setpull_updown,
...@@ -452,12 +385,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = { ...@@ -452,12 +385,9 @@ static struct s3c_gpio_chip s5pc100_gpio_chips[] = {
extern struct irq_chip s5pc1xx_gpioint; extern struct irq_chip s5pc1xx_gpioint;
extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc); extern void s5pc1xx_irq_gpioint_handler(unsigned int irq, struct irq_desc *desc);
static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) static __init void s5pc100_gpiolib_link(struct s3c_gpio_chip *chip)
{ {
chip->chip.direction_input = s5pc1xx_gpiolib_input; #if 0
chip->chip.direction_output = s5pc1xx_gpiolib_output;
chip->pm = __gpio_pm(&s3c_gpio_pm_4bit);
/* Interrupt */ /* Interrupt */
if (chip->config == &gpio_cfg) { if (chip->config == &gpio_cfg) {
int i, irq; int i, irq;
...@@ -473,31 +403,26 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip) ...@@ -473,31 +403,26 @@ static __init void s5pc1xx_gpiolib_link(struct s3c_gpio_chip *chip)
} }
} else if (chip->config == &gpio_cfg_eint) } else if (chip->config == &gpio_cfg_eint)
chip->chip.to_irq = s5pc1xx_gpiolib_to_eint; chip->chip.to_irq = s5pc1xx_gpiolib_to_eint;
} #endif
static __init void s5pc1xx_gpiolib_add(struct s3c_gpio_chip *chips,
int nr_chips,
void (*fn)(struct s3c_gpio_chip *))
{
for (; nr_chips > 0; nr_chips--, chips++) {
if (fn)
(fn)(chips);
s3c_gpiolib_add(chips);
}
} }
static __init int s5pc1xx_gpiolib_init(void) static __init int s5pc1xx_gpiolib_init(void)
{ {
struct s3c_gpio_chip *chips; struct s3c_gpio_chip *chip;
int nr_chips; int nr_chips;
chips = s5pc100_gpio_chips; chip = s5pc100_gpio_chips;
nr_chips = ARRAY_SIZE(s5pc100_gpio_chips); nr_chips = ARRAY_SIZE(s5pc100_gpio_chips);
for (; nr_chips > 0; nr_chips--, chip++)
s5pc100_gpiolib_link(chip);
s5pc1xx_gpiolib_add(chips, nr_chips, s5pc1xx_gpiolib_link); samsung_gpiolib_add_4bit_chips(s5pc100_gpio_chips,
ARRAY_SIZE(s5pc100_gpio_chips));
#if 0
/* Interrupt */ /* Interrupt */
set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler); set_irq_chained_handler(IRQ_GPIOINT, s5pc1xx_irq_gpioint_handler);
#endif
return 0; return 0;
} }
core_initcall(s5pc1xx_gpiolib_init); core_initcall(s5pc1xx_gpiolib_init);
...@@ -12,6 +12,9 @@ ...@@ -12,6 +12,9 @@
* published by the Free Software Foundation. * published by the Free Software Foundation.
*/ */
#ifndef __ASM_ARCH_GPIO_H
#define __ASM_ARCH_GPIO_H __FILE__
#define gpio_get_value __gpio_get_value #define gpio_get_value __gpio_get_value
#define gpio_set_value __gpio_set_value #define gpio_set_value __gpio_set_value
#define gpio_cansleep __gpio_cansleep #define gpio_cansleep __gpio_cansleep
...@@ -52,11 +55,6 @@ ...@@ -52,11 +55,6 @@
#define S5PC100_GPIO_L2_NR (8) #define S5PC100_GPIO_L2_NR (8)
#define S5PC100_GPIO_L3_NR (8) #define S5PC100_GPIO_L3_NR (8)
#define S5PC100_GPIO_L4_NR (8) #define S5PC100_GPIO_L4_NR (8)
#define S5PC100_GPIO_MP00_NR (8)
#define S5PC100_GPIO_MP01_NR (8)
#define S5PC100_GPIO_MP02_NR (8)
#define S5PC100_GPIO_MP03_NR (8)
#define S5PC100_GPIO_MP04_NR (5)
/* GPIO bank numbes */ /* GPIO bank numbes */
...@@ -65,50 +63,45 @@ ...@@ -65,50 +63,45 @@
* change from one gpio bank to another can be caught. * change from one gpio bank to another can be caught.
*/ */
#define S5PC1XX_GPIO_NEXT(__gpio) \ #define S5PC100_GPIO_NEXT(__gpio) \
((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1) ((__gpio##_START) + (__gpio##_NR) + CONFIG_S3C_GPIO_SPACE + 1)
enum s3c_gpio_number { enum s5p_gpio_number {
S5PC100_GPIO_A0_START = 0, S5PC100_GPIO_A0_START = 0,
S5PC100_GPIO_A1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A0), S5PC100_GPIO_A1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A0),
S5PC100_GPIO_B_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_A1), S5PC100_GPIO_B_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_A1),
S5PC100_GPIO_C_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_B), S5PC100_GPIO_C_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_B),
S5PC100_GPIO_D_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_C), S5PC100_GPIO_D_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_C),
S5PC100_GPIO_E0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_D), S5PC100_GPIO_E0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_D),
S5PC100_GPIO_E1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E0), S5PC100_GPIO_E1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E0),
S5PC100_GPIO_F0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_E1), S5PC100_GPIO_F0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_E1),
S5PC100_GPIO_F1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F0), S5PC100_GPIO_F1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F0),
S5PC100_GPIO_F2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F1), S5PC100_GPIO_F2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F1),
S5PC100_GPIO_F3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F2), S5PC100_GPIO_F3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F2),
S5PC100_GPIO_G0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_F3), S5PC100_GPIO_G0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_F3),
S5PC100_GPIO_G1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G0), S5PC100_GPIO_G1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G0),
S5PC100_GPIO_G2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G1), S5PC100_GPIO_G2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G1),
S5PC100_GPIO_G3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G2), S5PC100_GPIO_G3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G2),
S5PC100_GPIO_H0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_G3), S5PC100_GPIO_H0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_G3),
S5PC100_GPIO_H1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H0), S5PC100_GPIO_H1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H0),
S5PC100_GPIO_H2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H1), S5PC100_GPIO_H2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H1),
S5PC100_GPIO_H3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H2), S5PC100_GPIO_H3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H2),
S5PC100_GPIO_I_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_H3), S5PC100_GPIO_I_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_H3),
S5PC100_GPIO_J0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_I), S5PC100_GPIO_J0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_I),
S5PC100_GPIO_J1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J0), S5PC100_GPIO_J1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J0),
S5PC100_GPIO_J2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J1), S5PC100_GPIO_J2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J1),
S5PC100_GPIO_J3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J2), S5PC100_GPIO_J3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J2),
S5PC100_GPIO_J4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J3), S5PC100_GPIO_J4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J3),
S5PC100_GPIO_K0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_J4), S5PC100_GPIO_K0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_J4),
S5PC100_GPIO_K1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K0), S5PC100_GPIO_K1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K0),
S5PC100_GPIO_K2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K1), S5PC100_GPIO_K2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K1),
S5PC100_GPIO_K3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K2), S5PC100_GPIO_K3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K2),
S5PC100_GPIO_L0_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_K3), S5PC100_GPIO_L0_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_K3),
S5PC100_GPIO_L1_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L0), S5PC100_GPIO_L1_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L0),
S5PC100_GPIO_L2_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L1), S5PC100_GPIO_L2_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L1),
S5PC100_GPIO_L3_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L2), S5PC100_GPIO_L3_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L2),
S5PC100_GPIO_L4_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L3), S5PC100_GPIO_L4_START = S5PC100_GPIO_NEXT(S5PC100_GPIO_L3),
S5PC100_GPIO_MP00_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_L4), S5PC100_GPIO_END = S5PC100_GPIO_NEXT(S5PC100_GPIO_L4),
S5PC100_GPIO_MP01_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP00),
S5PC100_GPIO_MP02_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP01),
S5PC100_GPIO_MP03_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP02),
S5PC100_GPIO_MP04_START = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP03),
S5PC100_GPIO_END = S5PC1XX_GPIO_NEXT(S5PC100_GPIO_MP04),
}; };
/* S5PC100 GPIO number definitions. */ /* S5PC100 GPIO number definitions. */
...@@ -146,17 +139,13 @@ enum s3c_gpio_number { ...@@ -146,17 +139,13 @@ enum s3c_gpio_number {
#define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr)) #define S5PC100_GPL2(_nr) (S5PC100_GPIO_L2_START + (_nr))
#define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr)) #define S5PC100_GPL3(_nr) (S5PC100_GPIO_L3_START + (_nr))
#define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr)) #define S5PC100_GPL4(_nr) (S5PC100_GPIO_L4_START + (_nr))
#define S5PC100_MP00(_nr) (S5PC100_GPIO_MP00_START + (_nr))
#define S5PC100_MP01(_nr) (S5PC100_GPIO_MP01_START + (_nr))
#define S5PC100_MP02(_nr) (S5PC100_GPIO_MP02_START + (_nr))
#define S5PC100_MP03(_nr) (S5PC100_GPIO_MP03_START + (_nr))
#define S5PC100_MP04(_nr) (S5PC100_GPIO_MP04_START + (_nr))
#define S5PC100_MP05(_nr) (S5PC100_GPIO_MP05_START + (_nr))
/* It used the end of the S5PC1XX gpios */ /* It used the end of the S5PC100 gpios */
#define S3C_GPIO_END S5PC100_GPIO_END #define S3C_GPIO_END S5PC100_GPIO_END
/* define the number of gpios we need to the one after the MP04() range */ /* define the number of gpios we need to the one after the MP04() range */
#define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1) #define ARCH_NR_GPIOS (S5PC100_GPIO_END + 1)
#include <asm-generic/gpio.h> #include <asm-generic/gpio.h>
#endif /* __ASM_ARCH_GPIO_H */
/* linux/arch/arm/mach-s5pc100/include/mach/regs-clock.h
*
* Copyright (c) 2010 Samsung Electronics Co., Ltd.
* http://www.samsung.com/
*
* S5PC100 - Clock register definitions
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*/
#ifndef __ASM_ARCH_REGS_CLOCK_H
#define __ASM_ARCH_REGS_CLOCK_H __FILE__
#include <mach/map.h>
#define S5P_CLKREG(x) (S3C_VA_SYS + (x))
#define S5P_APLL_LOCK S5P_CLKREG(0x00)
#define S5P_MPLL_LOCK S5P_CLKREG(0x04)
#define S5P_EPLL_LOCK S5P_CLKREG(0x08)
#define S5P_HPLL_LOCK S5P_CLKREG(0x0C)
#define S5P_APLL_CON S5P_CLKREG(0x100)
#define S5P_MPLL_CON S5P_CLKREG(0x104)
#define S5P_EPLL_CON S5P_CLKREG(0x108)
#define S5P_HPLL_CON S5P_CLKREG(0x10C)
#define S5P_CLK_SRC0 S5P_CLKREG(0x200)
#define S5P_CLK_SRC1 S5P_CLKREG(0x204)
#define S5P_CLK_SRC2 S5P_CLKREG(0x208)
#define S5P_CLK_SRC3 S5P_CLKREG(0x20C)
#define S5P_CLK_DIV0 S5P_CLKREG(0x300)
#define S5P_CLK_DIV1 S5P_CLKREG(0x304)
#define S5P_CLK_DIV2 S5P_CLKREG(0x308)
#define S5P_CLK_DIV3 S5P_CLKREG(0x30C)
#define S5P_CLK_DIV4 S5P_CLKREG(0x310)
#define S5P_CLK_OUT S5P_CLKREG(0x400)
#define S5P_CLKGATE_D00 S5P_CLKREG(0x500)
#define S5P_CLKGATE_D01 S5P_CLKREG(0x504)
#define S5P_CLKGATE_D02 S5P_CLKREG(0x508)
#define S5P_CLKGATE_D10 S5P_CLKREG(0x520)
#define S5P_CLKGATE_D11 S5P_CLKREG(0x524)
#define S5P_CLKGATE_D12 S5P_CLKREG(0x528)
#define S5P_CLKGATE_D13 S5P_CLKREG(0x52C)
#define S5P_CLKGATE_D14 S5P_CLKREG(0x530)
#define S5P_CLKGATE_D15 S5P_CLKREG(0x534)
#define S5P_CLKGATE_D20 S5P_CLKREG(0x540)
#define S5P_CLKGATE_SCLK0 S5P_CLKREG(0x560)
#define S5P_CLKGATE_SCLK1 S5P_CLKREG(0x564)
/* CLKDIV0 */
#define S5P_CLKDIV0_D0_MASK (0x7<<8)
#define S5P_CLKDIV0_D0_SHIFT (8)
#define S5P_CLKDIV0_PCLKD0_MASK (0x7<<12)
#define S5P_CLKDIV0_PCLKD0_SHIFT (12)
/* CLKDIV1 */
#define S5P_CLKDIV1_D1_MASK (0x7<<12)
#define S5P_CLKDIV1_D1_SHIFT (12)
#define S5P_CLKDIV1_PCLKD1_MASK (0x7<<16)
#define S5P_CLKDIV1_PCLKD1_SHIFT (16)
#endif /* __ASM_ARCH_REGS_CLOCK_H */
...@@ -3,11 +3,11 @@ ...@@ -3,11 +3,11 @@
* Copyright 2009 Samsung Electronics Co. * Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com> * Byungho Min <bhmin@samsung.com>
* *
* S5PC1XX - GPIO register definitions * S5PC100 - GPIO register definitions
*/ */
#ifndef __ASM_PLAT_S5PC1XX_REGS_GPIO_H #ifndef __ASM_MACH_S5PC100_REGS_GPIO_H
#define __ASM_PLAT_S5PC1XX_REGS_GPIO_H __FILE__ #define __ASM_MACH_S5PC100_REGS_GPIO_H __FILE__
#include <mach/map.h> #include <mach/map.h>
...@@ -66,5 +66,5 @@ ...@@ -66,5 +66,5 @@
#define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4)) #define S5PC100_GPx_OUTPUT(__gpio) (0x1 << ((__gpio) * 4))
#define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4)) #define S5PC100_GPx_CONMASK(__gpio) (0xf << ((__gpio) * 4))
#endif /* __ASM_PLAT_S5PC1XX_REGS_GPIO_H */ #endif /* __ASM_MACH_S5PC100_REGS_GPIO_H */
...@@ -35,7 +35,6 @@ ...@@ -35,7 +35,6 @@
#include <plat/regs-serial.h> #include <plat/regs-serial.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/regs-gpio.h>
#include <plat/clock.h> #include <plat/clock.h>
#include <plat/devs.h> #include <plat/devs.h>
......
/* /*
* linux/arch/arm/plat-s5pc100/setup-fb-24bpp.c * linux/arch/arm/mach-s5pc100/setup-fb-24bpp.c
* *
* Copyright 2009 Samsung Electronics * Copyright 2009 Samsung Electronics
* *
* Base S5PC1XX setup information for 24bpp LCD framebuffer * Base S5PC100 setup information for 24bpp LCD framebuffer
* *
* This program is free software; you can redistribute it and/or modify * This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as * it under the terms of the GNU General Public License version 2 as
...@@ -19,7 +19,6 @@ ...@@ -19,7 +19,6 @@
#include <mach/map.h> #include <mach/map.h>
#include <plat/fb.h> #include <plat/fb.h>
#include <plat/gpio-cfg.h> #include <plat/gpio-cfg.h>
#include <plat/gpio-cfg-s5pc1xx.h>
#define DISR_OFFSET 0x7008 #define DISR_OFFSET 0x7008
......
/* linux/arch/arm/plat-s5pc1xx/setup-i2c0.c /* linux/arch/arm/mach-s5pc100/setup-i2c0.c
* *
* Copyright 2009 Samsung Electronics Co. * Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com> * Byungho Min <bhmin@samsung.com>
* *
* Base S5PC1XX I2C bus 0 gpio configuration * Base S5PC100 I2C bus 0 gpio configuration
* *
* Based on plat-s3c64xx/setup-i2c0.c * Based on plat-s3c64xx/setup-i2c0.c
* *
......
/* linux/arch/arm/plat-s3c64xx/setup-i2c1.c /* linux/arch/arm/mach-s5pc100/setup-i2c1.c
* *
* Copyright 2009 Samsung Electronics Co. * Copyright 2009 Samsung Electronics Co.
* Byungho Min <bhmin@samsung.com> * Byungho Min <bhmin@samsung.com>
* *
* Base S5PC1XX I2C bus 1 gpio configuration * Base S5PC100 I2C bus 1 gpio configuration
* *
* Based on plat-s3c64xx/setup-i2c1.c * Based on plat-s3c64xx/setup-i2c1.c
* *
......
...@@ -12,6 +12,7 @@ if ARCH_S5PV210 ...@@ -12,6 +12,7 @@ if ARCH_S5PV210
config CPU_S5PV210 config CPU_S5PV210
bool bool
select PLAT_S5P select PLAT_S5P
select S3C_PL330_DMA
help help
Enable S5PV210 CPU support Enable S5PV210 CPU support
......
...@@ -12,9 +12,14 @@ obj- := ...@@ -12,9 +12,14 @@ obj- :=
# Core support for S5PV210 system # Core support for S5PV210 system
obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o obj-$(CONFIG_CPU_S5PV210) += cpu.o init.o clock.o dma.o gpiolib.o
obj-$(CONFIG_CPU_S5PV210) += setup-i2c0.o
# machine support # machine support
obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o obj-$(CONFIG_MACH_SMDKV210) += mach-smdkv210.o
obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o obj-$(CONFIG_MACH_SMDKC110) += mach-smdkc110.o
# device support
obj-y += dev-audio.o
This diff is collapsed.
...@@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void) ...@@ -100,7 +100,7 @@ void __init s5pv210_init_irq(void)
s5p_init_irq(vic, ARRAY_SIZE(vic)); s5p_init_irq(vic, ARRAY_SIZE(vic));
} }
static struct sysdev_class s5pv210_sysclass = { struct sysdev_class s5pv210_sysclass = {
.name = "s5pv210-core", .name = "s5pv210-core",
}; };
......
This diff is collapsed.
/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#include <linux/platform_device.h>
#include <linux/dma-mapping.h>
#include <plat/devs.h>
#include <plat/irqs.h>
#include <mach/map.h>
#include <mach/irqs.h>
#include <plat/s3c-pl330-pdata.h>
static u64 dma_dmamask = DMA_BIT_MASK(32);
static struct resource s5pv210_pdma0_resource[] = {
[0] = {
.start = S5PV210_PA_PDMA0,
.end = S5PV210_PA_PDMA0 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA0,
.end = IRQ_PDMA0,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5pv210_pdma0_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_MAX,
[15] = DMACH_MAX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_SPI1_RX,
[19] = DMACH_SPI1_TX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_AC97_MICIN,
[23] = DMACH_AC97_PCMIN,
[24] = DMACH_AC97_PCMOUT,
[25] = DMACH_MAX,
[26] = DMACH_PWM,
[27] = DMACH_SPDIF,
[28] = DMACH_MAX,
[29] = DMACH_MAX,
[30] = DMACH_MAX,
[31] = DMACH_MAX,
},
};
static struct platform_device s5pv210_device_pdma0 = {
.name = "s3c-pl330",
.id = 1,
.num_resources = ARRAY_SIZE(s5pv210_pdma0_resource),
.resource = s5pv210_pdma0_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma0_pdata,
},
};
static struct resource s5pv210_pdma1_resource[] = {
[0] = {
.start = S5PV210_PA_PDMA1,
.end = S5PV210_PA_PDMA1 + SZ_4K,
.flags = IORESOURCE_MEM,
},
[1] = {
.start = IRQ_PDMA1,
.end = IRQ_PDMA1,
.flags = IORESOURCE_IRQ,
},
};
static struct s3c_pl330_platdata s5pv210_pdma1_pdata = {
.peri = {
[0] = DMACH_UART0_RX,
[1] = DMACH_UART0_TX,
[2] = DMACH_UART1_RX,
[3] = DMACH_UART1_TX,
[4] = DMACH_UART2_RX,
[5] = DMACH_UART2_TX,
[6] = DMACH_UART3_RX,
[7] = DMACH_UART3_TX,
[8] = DMACH_MAX,
[9] = DMACH_I2S0_RX,
[10] = DMACH_I2S0_TX,
[11] = DMACH_I2S0S_TX,
[12] = DMACH_I2S1_RX,
[13] = DMACH_I2S1_TX,
[14] = DMACH_I2S2_RX,
[15] = DMACH_I2S2_TX,
[16] = DMACH_SPI0_RX,
[17] = DMACH_SPI0_TX,
[18] = DMACH_SPI1_RX,
[19] = DMACH_SPI1_TX,
[20] = DMACH_MAX,
[21] = DMACH_MAX,
[22] = DMACH_PCM0_RX,
[23] = DMACH_PCM0_TX,
[24] = DMACH_PCM1_RX,
[25] = DMACH_PCM1_TX,
[26] = DMACH_MSM_REQ0,
[27] = DMACH_MSM_REQ1,
[28] = DMACH_MSM_REQ2,
[29] = DMACH_MSM_REQ3,
[30] = DMACH_PCM2_RX,
[31] = DMACH_PCM2_TX,
},
};
static struct platform_device s5pv210_device_pdma1 = {
.name = "s3c-pl330",
.id = 2,
.num_resources = ARRAY_SIZE(s5pv210_pdma1_resource),
.resource = s5pv210_pdma1_resource,
.dev = {
.dma_mask = &dma_dmamask,
.coherent_dma_mask = DMA_BIT_MASK(32),
.platform_data = &s5pv210_pdma1_pdata,
},
};
static struct platform_device *s5pv210_dmacs[] __initdata = {
&s5pv210_device_pdma0,
&s5pv210_device_pdma1,
};
static int __init s5pv210_dma_init(void)
{
platform_add_devices(s5pv210_dmacs, ARRAY_SIZE(s5pv210_dmacs));
return 0;
}
arch_initcall(s5pv210_dma_init);
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/*
* Copyright (C) 2010 Samsung Electronics Co. Ltd.
* Jaswinder Singh <jassi.brar@samsung.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA.
*/
#ifndef __MACH_DMA_H
#define __MACH_DMA_H
/* This platform uses the common S3C DMA API driver for PL330 */
#include <plat/s3c-dma-pl330.h>
#endif /* __MACH_DMA_H */
...@@ -18,6 +18,8 @@ ...@@ -18,6 +18,8 @@
#define gpio_cansleep __gpio_cansleep #define gpio_cansleep __gpio_cansleep
#define gpio_to_irq __gpio_to_irq #define gpio_to_irq __gpio_to_irq
/* Practically, GPIO banks upto MP03 are the configurable gpio banks */
/* GPIO bank sizes */ /* GPIO bank sizes */
#define S5PV210_GPIO_A0_NR (8) #define S5PV210_GPIO_A0_NR (8)
#define S5PV210_GPIO_A1_NR (4) #define S5PV210_GPIO_A1_NR (4)
...@@ -47,6 +49,10 @@ ...@@ -47,6 +49,10 @@
#define S5PV210_GPIO_J3_NR (8) #define S5PV210_GPIO_J3_NR (8)
#define S5PV210_GPIO_J4_NR (5) #define S5PV210_GPIO_J4_NR (5)
#define S5PV210_GPIO_MP01_NR (8)
#define S5PV210_GPIO_MP02_NR (4)
#define S5PV210_GPIO_MP03_NR (8)
/* GPIO bank numbers */ /* GPIO bank numbers */
/* CONFIG_S3C_GPIO_SPACE allows the user to select extra /* CONFIG_S3C_GPIO_SPACE allows the user to select extra
...@@ -85,6 +91,9 @@ enum s5p_gpio_number { ...@@ -85,6 +91,9 @@ enum s5p_gpio_number {
S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1), S5PV210_GPIO_J2_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J1),
S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2), S5PV210_GPIO_J3_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J2),
S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3), S5PV210_GPIO_J4_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J3),
S5PV210_GPIO_MP01_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_J4),
S5PV210_GPIO_MP02_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP01),
S5PV210_GPIO_MP03_START = S5PV210_GPIO_NEXT(S5PV210_GPIO_MP02),
}; };
/* S5PV210 GPIO number definitions */ /* S5PV210 GPIO number definitions */
...@@ -115,13 +124,16 @@ enum s5p_gpio_number { ...@@ -115,13 +124,16 @@ enum s5p_gpio_number {
#define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr)) #define S5PV210_GPJ2(_nr) (S5PV210_GPIO_J2_START + (_nr))
#define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr)) #define S5PV210_GPJ3(_nr) (S5PV210_GPIO_J3_START + (_nr))
#define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr)) #define S5PV210_GPJ4(_nr) (S5PV210_GPIO_J4_START + (_nr))
#define S5PV210_MP01(_nr) (S5PV210_GPIO_MP01_START + (_nr))
#define S5PV210_MP02(_nr) (S5PV210_GPIO_MP02_START + (_nr))
#define S5PV210_MP03(_nr) (S5PV210_GPIO_MP03_START + (_nr))
/* the end of the S5PV210 specific gpios */ /* the end of the S5PV210 specific gpios */
#define S5PV210_GPIO_END (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + 1) #define S5PV210_GPIO_END (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + 1)
#define S3C_GPIO_END S5PV210_GPIO_END #define S3C_GPIO_END S5PV210_GPIO_END
/* define the number of gpios we need to the one after the GPJ4() range */ /* define the number of gpios we need to the one after the MP03() range */
#define ARCH_NR_GPIOS (S5PV210_GPJ4(S5PV210_GPIO_J4_NR) + \ #define ARCH_NR_GPIOS (S5PV210_MP03(S5PV210_GPIO_MP03_NR) + \
CONFIG_SAMSUNG_GPIO_EXTRA + 1) CONFIG_SAMSUNG_GPIO_EXTRA + 1)
#include <asm-generic/gpio.h> #include <asm-generic/gpio.h>
......
...@@ -43,6 +43,10 @@ ...@@ -43,6 +43,10 @@
#define S5PV210_PA_SROMC (0xE8000000) #define S5PV210_PA_SROMC (0xE8000000)
#define S5PV210_PA_MDMA 0xFA200000
#define S5PV210_PA_PDMA0 0xE0900000
#define S5PV210_PA_PDMA1 0xE0A00000
#define S5PV210_PA_VIC0 (0xF2000000) #define S5PV210_PA_VIC0 (0xF2000000)
#define S5P_PA_VIC0 S5PV210_PA_VIC0 #define S5P_PA_VIC0 S5PV210_PA_VIC0
...@@ -58,6 +62,19 @@ ...@@ -58,6 +62,19 @@
#define S5PV210_PA_SDRAM (0x20000000) #define S5PV210_PA_SDRAM (0x20000000)
#define S5P_PA_SDRAM S5PV210_PA_SDRAM #define S5P_PA_SDRAM S5PV210_PA_SDRAM
/* I2S */
#define S5PV210_PA_IIS0 0xEEE30000
#define S5PV210_PA_IIS1 0xE2100000
#define S5PV210_PA_IIS2 0xE2A00000
/* PCM */
#define S5PV210_PA_PCM0 0xE2300000
#define S5PV210_PA_PCM1 0xE1200000
#define S5PV210_PA_PCM2 0xE2B00000
/* AC97 */
#define S5PV210_PA_AC97 0xE2200000
/* compatibiltiy defines. */ /* compatibiltiy defines. */
#define S3C_PA_UART S5PV210_PA_UART #define S3C_PA_UART S5PV210_PA_UART
#define S3C_PA_IIC S5PV210_PA_IIC0 #define S3C_PA_IIC S5PV210_PA_IIC0
......
...@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { ...@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
}; };
static struct platform_device *smdkc110_devices[] __initdata = { static struct platform_device *smdkc110_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
}; };
static void __init smdkc110_map_io(void) static void __init smdkc110_map_io(void)
......
...@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = { ...@@ -72,6 +72,8 @@ static struct s3c2410_uartcfg smdkv210_uartcfgs[] __initdata = {
}; };
static struct platform_device *smdkv210_devices[] __initdata = { static struct platform_device *smdkv210_devices[] __initdata = {
&s5pv210_device_iis0,
&s5pv210_device_ac97,
}; };
static void __init smdkv210_map_io(void) static void __init smdkv210_map_io(void)
......
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...@@ -164,4 +164,9 @@ config S3C24XX_SIMTEC_AUDIO ...@@ -164,4 +164,9 @@ config S3C24XX_SIMTEC_AUDIO
help help
Add audio devices for common Simtec S3C24XX boards Add audio devices for common Simtec S3C24XX boards
config S3C2410_SETUP_TS
bool
help
Compile in platform device definition for Samsung TouchScreen.
endif endif
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