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Commit 34cb72ef authored by Ian Rogers's avatar Ian Rogers Committed by Arnaldo Carvalho de Melo
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perf vendor events: Update metrics for Broadwell DE 

Based on TMA_metrics-full.csv version 4.3 at 01.org:
    https://download.01.org/perfmon/
Events are still at version 7:
    https://download.01.org/perfmon/BDW-DE
Json files generated by:
    https://github.com/intel/event-converter-for-linux-perf

This adds TopdownL1_SMT metrics to bdwde-metrics.json. A discussed in:
https://lore.kernel.org/all/20220129080929.837293-4-irogers@google.com/
The TMA_Metrics-full.csv was modified so that BDW-DE is in the server
column with BDX, the Page_Walks_Utilization and
Page_Walks_Utilization_SMT metrics are then copied from BDW.

Tested:

  ...
    6: Parse event definition strings                                  : Ok
    7: Simple expression parser                                        : Ok
  ...
    9: Parse perf pmu format                                           : Ok
   10: PMU events                                                      :
   10.1: PMU event table sanity                                        : Ok
   10.2: PMU event map aliases                                         : Ok
   10.3: Parsing of PMU event table metrics                            : Ok
   10.4: Parsing of PMU event table metrics with fake PMUs             : Ok
  ...
   68: Parse and process metrics                                       : Ok
  ...
   88: perf stat metrics (shadow stat) test                            : Ok
   89: perf all metricgroups test                                      : Ok
   90: perf all metrics test                                           : Skip
   91: perf all PMU test                                               : Ok
  ...

90 skips due to a lack of floating point samples, which is
understandable.
Suggested-by: default avatarKan Liang <kan.liang@linux.intel.com>
Reviewed-by: default avatarKan Liang <kan.liang@linux.intel.com>
Signed-off-by: default avatarIan Rogers <irogers@google.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexandre Torgue <alexandre.torgue@foss.st.com>
Cc: Andi Kleen <ak@linux.intel.com>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: James Clark <james.clark@arm.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: John Garry <john.garry@huawei.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Maxime Coquelin <mcoquelin.stm32@gmail.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Zhengjun Xing <zhengjun.xing@linux.intel.com>
Link: https://lore.kernel.org/r/20220201015858.1226914-4-irogers@google.comSigned-off-by: default avatarArnaldo Carvalho de Melo <acme@redhat.com>
parent 3bad20d7
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tools/perf/pmu-events/arch/x86/broadwellde/bdwde-metrics.json
View file @ 34cb72ef
[ [
{ {
"BriefDescription": "Instructions Per Cycle (per logical thread)", "BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Frontend_Bound",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound."
},
{
"BriefDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Frontend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where the processor's Frontend undersupplies its Backend. Frontend denotes the first part of the processor core responsible to fetch operations that are executed later on by the Backend part. Within the Frontend; a branch predictor predicts the next address to fetch; cache-lines are fetched from the memory subsystem; parsed into instructions; and lastly decoded into micro-operations (uops). Ideally the Frontend can issue Machine_Width uops every cycle to the Backend. Frontend Bound denotes unutilized issue-slots when there is no Backend stall; i.e. bubbles where Frontend delivered no uops while Backend could have accepted them. For example; stalls due to instruction-cache misses would be categorized under Frontend Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Bad_Speculation",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example."
},
{
"BriefDescription": "This category represents fraction of slots wasted due to incorrect speculations. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Bad_Speculation_SMT",
"PublicDescription": "This category represents fraction of slots wasted due to incorrect speculations. This include slots used to issue uops that do not eventually get retired and slots for which the issue-pipeline was blocked due to recovery from earlier incorrect speculation. For example; wasted work due to miss-predicted branches are categorized under Bad Speculation category. Incorrect data speculation followed by Memory Ordering Nukes is another example. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend",
"MetricConstraint": "NO_NMI_WATCHDOG",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD)) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)) )",
"MetricGroup": "TopdownL1",
"MetricName": "Backend_Bound",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound."
},
{
"BriefDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "1 - ( (IDQ_UOPS_NOT_DELIVERED.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) + (UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) )",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Backend_Bound_SMT",
"PublicDescription": "This category represents fraction of slots where no uops are being delivered due to a lack of required resources for accepting new uops in the Backend. Backend is the portion of the processor core where the out-of-order scheduler dispatches ready uops into their respective execution units; and once completed these uops get retired according to program order. For example; stalls due to data-cache misses or stalls due to the divider unit being overloaded are both categorized under Backend Bound. Backend Bound is further divided into two main categories: Memory Bound and Core Bound. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "TopdownL1",
"MetricName": "Retiring",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided."
},
{
"BriefDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))",
"MetricGroup": "TopdownL1_SMT",
"MetricName": "Retiring_SMT",
"PublicDescription": "This category represents fraction of slots utilized by useful work i.e. issued uops that eventually get retired. Ideally; all pipeline slots would be attributed to the Retiring category. Retiring of 100% would indicate the maximum Pipeline_Width throughput was achieved. Maximizing Retiring typically increases the Instructions-per-cycle (see IPC metric). Note that a high Retiring value does not necessary mean there is no room for more performance. For example; Heavy-operations or Microcode Assists are categorized under Retiring. They often indicate suboptimal performance and can often be optimized or avoided. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{
"BriefDescription": "Instructions Per Cycle (per Logical Processor)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD", "MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1", "MetricGroup": "Ret;Summary",
"MetricName": "IPC" "MetricName": "IPC"
}, },
{ {
"BriefDescription": "Uops Per Instruction", "BriefDescription": "Uops Per Instruction",
"MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY",
"MetricGroup": "Pipeline", "MetricGroup": "Pipeline;Ret;Retire",
"MetricName": "UPI" "MetricName": "UPI"
}, },
{ {
"BriefDescription": "Rough Estimation of fraction of fetched lines bytes that were likely consumed by program instructions", "BriefDescription": "Instruction per taken branch",
"MetricExpr": "min( 1 , IDQ.MITE_UOPS / ( UOPS_RETIRED.RETIRE_SLOTS / INST_RETIRED.ANY * 16 * ( ICACHE.HIT + ICACHE.MISSES ) / 4.0 ) )", "MetricExpr": "UOPS_RETIRED.RETIRE_SLOTS / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Frontend", "MetricGroup": "Branches;Fed;FetchBW",
"MetricName": "IFetch_Line_Utilization" "MetricName": "UpTB"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded Icache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
"MetricGroup": "DSB; Frontend_Bandwidth",
"MetricName": "DSB_Coverage"
}, },
{ {
"BriefDescription": "Cycles Per Instruction (threaded)", "BriefDescription": "Cycles Per Instruction (per Logical Processor)",
"MetricExpr": "1 / INST_RETIRED.ANY / cycles", "MetricExpr": "1 / (INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD)",
"MetricGroup": "Pipeline;Summary", "MetricGroup": "Pipeline;Mem",
"MetricName": "CPI" "MetricName": "CPI"
}, },
{ {
"BriefDescription": "Per-thread actual clocks when the logical processor is active. This is called 'Clockticks' in VTune.", "BriefDescription": "Per-Logical Processor actual clocks when the Logical Processor is active.",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD", "MetricExpr": "CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary", "MetricGroup": "Pipeline",
"MetricName": "CLKS" "MetricName": "CLKS"
}, },
{ {
"BriefDescription": "Total issue-pipeline slots", "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "4*( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", "MetricExpr": "4 * CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "TopDownL1", "MetricGroup": "TmaL1",
"MetricName": "SLOTS" "MetricName": "SLOTS"
}, },
{ {
"BriefDescription": "Total number of retired Instructions", "BriefDescription": "Total issue-pipeline slots (per-Physical Core till ICL; per-Logical Processor ICL onward)",
"MetricExpr": "INST_RETIRED.ANY", "MetricExpr": "4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Summary", "MetricGroup": "TmaL1_SMT",
"MetricName": "Instructions" "MetricName": "SLOTS_SMT"
}, },
{ {
"BriefDescription": "Instructions Per Cycle (per physical core)", "BriefDescription": "The ratio of Executed- by Issued-Uops",
"MetricExpr": "INST_RETIRED.ANY / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", "MetricExpr": "UOPS_EXECUTED.THREAD / UOPS_ISSUED.ANY",
"MetricGroup": "SMT", "MetricGroup": "Cor;Pipeline",
"MetricName": "Execute_per_Issue",
"PublicDescription": "The ratio of Executed- by Issued-Uops. Ratio > 1 suggests high rate of uop micro-fusions. Ratio < 1 suggest high rate of \"execute\" at rename stage."
},
{
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;SMT;TmaL1",
"MetricName": "CoreIPC" "MetricName": "CoreIPC"
}, },
{
"BriefDescription": "Instructions Per Cycle across hyper-threads (per physical core)",
"MetricExpr": "INST_RETIRED.ANY / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;SMT;TmaL1_SMT",
"MetricName": "CoreIPC_SMT"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Ret;Flops",
"MetricName": "FLOPc"
},
{
"BriefDescription": "Floating Point Operations Per Cycle",
"MetricExpr": "( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Ret;Flops_SMT",
"MetricName": "FLOPc_SMT"
},
{
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width)",
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * CPU_CLK_UNHALTED.THREAD )",
"MetricGroup": "Cor;Flops;HPC",
"MetricName": "FP_Arith_Utilization",
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting."
},
{
"BriefDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). SMT version; use when SMT is enabled and measuring per logical CPU.",
"MetricExpr": "( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) ) / ( 2 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ) )",
"MetricGroup": "Cor;Flops;HPC_SMT",
"MetricName": "FP_Arith_Utilization_SMT",
"PublicDescription": "Actual per-core usage of the Floating Point execution units (regardless of the vector width). Values > 1 are possible due to Fused-Multiply Add (FMA) counting. SMT version; use when SMT is enabled and measuring per logical CPU."
},
{ {
"BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)", "BriefDescription": "Instruction-Level-Parallelism (average number of uops executed when there is at least 1 uop executed)",
"MetricExpr": "UOPS_EXECUTED.THREAD / ( cpu@uops_executed.core\\,cmask\\=1@ / 2) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC", "MetricExpr": "UOPS_EXECUTED.THREAD / (( cpu@UOPS_EXECUTED.CORE\\,cmask\\=1@ / 2 ) if #SMT_on else UOPS_EXECUTED.CYCLES_GE_1_UOP_EXEC)",
"MetricGroup": "Pipeline;Ports_Utilization", "MetricGroup": "Backend;Cor;Pipeline;PortsUtil",
"MetricName": "ILP" "MetricName": "ILP"
}, },
{ {
"BriefDescription": "Average Branch Address Clear Cost (fraction of cycles)", "BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "2* ( RS_EVENTS.EMPTY_CYCLES - ICACHE.IFDATA_STALL - ( 14 * ITLB_MISSES.STLB_HIT + cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + 7* ITLB_MISSES.WALK_COMPLETED ) ) / RS_EVENTS.EMPTY_END", "MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * INT_MISC.RECOVERY_CYCLES ) / (4 * CPU_CLK_UNHALTED.THREAD))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * CPU_CLK_UNHALTED.THREAD)) ) * (4 * CPU_CLK_UNHALTED.THREAD) / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Unknown_Branches", "MetricGroup": "Bad;BrMispredicts",
"MetricName": "BAClear_Cost" "MetricName": "Branch_Misprediction_Cost"
},
{
"BriefDescription": "Branch Misprediction Cost: Fraction of TMA slots wasted per non-speculative branch misprediction (retired JEClear)",
"MetricExpr": "( ((BR_MISP_RETIRED.ALL_BRANCHES / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT )) * (( UOPS_ISSUED.ANY - UOPS_RETIRED.RETIRE_SLOTS + 4 * ( INT_MISC.RECOVERY_CYCLES_ANY / 2 ) ) / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )))) + (4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) * (BR_MISP_RETIRED.ALL_BRANCHES * (12 * ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY ) / CPU_CLK_UNHALTED.THREAD) / ( BR_MISP_RETIRED.ALL_BRANCHES + MACHINE_CLEARS.COUNT + BACLEARS.ANY )) / #(4 * IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE / (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) ))) ) * (4 * ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )) / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BrMispredicts_SMT",
"MetricName": "Branch_Misprediction_Cost_SMT"
},
{
"BriefDescription": "Number of Instructions per non-speculative Branch Misprediction (JEClear)",
"MetricExpr": "INST_RETIRED.ANY / BR_MISP_RETIRED.ALL_BRANCHES",
"MetricGroup": "Bad;BadSpec;BrMispredicts",
"MetricName": "IpMispredict"
}, },
{ {
"BriefDescription": "Core actual clocks when any thread is active on the physical core", "BriefDescription": "Core actual clocks when any Logical Processor is active on the Physical Core",
"MetricExpr": "( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else CPU_CLK_UNHALTED.THREAD", "MetricExpr": "( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "SMT", "MetricGroup": "SMT",
"MetricName": "CORE_CLKS" "MetricName": "CORE_CLKS"
}, },
{ {
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand loads", "BriefDescription": "Instructions per Load (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_LOADS",
"MetricGroup": "InsType",
"MetricName": "IpLoad"
},
{
"BriefDescription": "Instructions per Store (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / MEM_UOPS_RETIRED.ALL_STORES",
"MetricGroup": "InsType",
"MetricName": "IpStore"
},
{
"BriefDescription": "Instructions per Branch (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.ALL_BRANCHES",
"MetricGroup": "Branches;Fed;InsType",
"MetricName": "IpBranch"
},
{
"BriefDescription": "Instructions per (near) call (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_CALL",
"MetricGroup": "Branches;Fed;PGO",
"MetricName": "IpCall"
},
{
"BriefDescription": "Instruction per taken branch",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;FetchBW;Frontend;PGO",
"MetricName": "IpTB"
},
{
"BriefDescription": "Branch instructions per taken branch.",
"MetricExpr": "BR_INST_RETIRED.ALL_BRANCHES / BR_INST_RETIRED.NEAR_TAKEN",
"MetricGroup": "Branches;Fed;PGO",
"MetricName": "BpTkBranch"
},
{
"BriefDescription": "Instructions per Floating Point (FP) Operation (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
"MetricGroup": "Flops;InsType",
"MetricName": "IpFLOP"
},
{
"BriefDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ( (FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE) + (FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE) )",
"MetricGroup": "Flops;InsType",
"MetricName": "IpArith",
"PublicDescription": "Instructions per FP Arithmetic instruction (lower number means higher occurrence rate). May undercount due to FMA double counting. Approximated prior to BDW."
},
{
"BriefDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"MetricGroup": "Flops;FpScalar;InsType",
"MetricName": "IpArith_Scalar_SP",
"PublicDescription": "Instructions per FP Arithmetic Scalar Single-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
"BriefDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"MetricGroup": "Flops;FpScalar;InsType",
"MetricName": "IpArith_Scalar_DP",
"PublicDescription": "Instructions per FP Arithmetic Scalar Double-Precision instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
"BriefDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE )",
"MetricGroup": "Flops;FpVector;InsType",
"MetricName": "IpArith_AVX128",
"PublicDescription": "Instructions per FP Arithmetic AVX/SSE 128-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
"BriefDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate)",
"MetricExpr": "INST_RETIRED.ANY / ( FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE + FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE )",
"MetricGroup": "Flops;FpVector;InsType",
"MetricName": "IpArith_AVX256",
"PublicDescription": "Instructions per FP Arithmetic AVX* 256-bit instruction (lower number means higher occurrence rate). May undercount due to FMA double counting."
},
{
"BriefDescription": "Total number of retired Instructions, Sample with: INST_RETIRED.PREC_DIST",
"MetricExpr": "INST_RETIRED.ANY",
"MetricGroup": "Summary;TmaL1",
"MetricName": "Instructions"
},
{
"BriefDescription": "Fraction of Uops delivered by the DSB (aka Decoded ICache; or Uop Cache)",
"MetricExpr": "IDQ.DSB_UOPS / ( IDQ.DSB_UOPS + LSD.UOPS + IDQ.MITE_UOPS + IDQ.MS_UOPS )",
"MetricGroup": "DSB;Fed;FetchBW",
"MetricName": "DSB_Coverage"
},
{
"BriefDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles)",
"MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )", "MetricExpr": "L1D_PEND_MISS.PENDING / ( MEM_LOAD_UOPS_RETIRED.L1_MISS + mem_load_uops_retired.hit_lfb )",
"MetricGroup": "Memory_Bound;Memory_Lat", "MetricGroup": "Mem;MemoryBound;MemoryLat",
"MetricName": "Load_Miss_Real_Latency" "MetricName": "Load_Miss_Real_Latency",
"PublicDescription": "Actual Average Latency for L1 data-cache miss demand load instructions (in core cycles). Latency may be overestimated for multi-load instructions - e.g. repeat strings."
}, },
{ {
"BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least 1 such miss)", "BriefDescription": "Memory-Level-Parallelism (average number of L1 miss demand load when there is at least one such miss. Per-Logical Processor)",
"MetricExpr": "L1D_PEND_MISS.PENDING / ( cpu@l1d_pend_miss.pending_cycles\\,any\\=1@ / 2) if #SMT_on else L1D_PEND_MISS.PENDING_CYCLES", "MetricExpr": "L1D_PEND_MISS.PENDING / L1D_PEND_MISS.PENDING_CYCLES",
"MetricGroup": "Memory_Bound;Memory_BW", "MetricGroup": "Mem;MemoryBound;MemoryBW",
"MetricName": "MLP" "MetricName": "MLP"
}, },
{
"BriefDescription": "Average data fill bandwidth to the L1 data cache [GB / sec]",
"MetricExpr": "64 * L1D.REPLACEMENT / 1000000000 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L1D_Cache_Fill_BW"
},
{
"BriefDescription": "Average data fill bandwidth to the L2 cache [GB / sec]",
"MetricExpr": "64 * L2_LINES_IN.ALL / 1000000000 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L2_Cache_Fill_BW"
},
{
"BriefDescription": "Average per-core data fill bandwidth to the L3 cache [GB / sec]",
"MetricExpr": "64 * LONGEST_LAT_CACHE.MISS / 1000000000 / duration_time",
"MetricGroup": "Mem;MemoryBW",
"MetricName": "L3_Cache_Fill_BW"
},
{
"BriefDescription": "L1 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L1_MISS / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L1MPKI"
},
{
"BriefDescription": "L2 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L2_MISS / INST_RETIRED.ANY",
"MetricGroup": "Mem;Backend;CacheMisses",
"MetricName": "L2MPKI"
},
{
"BriefDescription": "L2 cache misses per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.MISS / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses;Offcore",
"MetricName": "L2MPKI_All"
},
{
"BriefDescription": "L2 cache misses per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_MISS / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L2MPKI_Load"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all request types (including speculative)",
"MetricExpr": "1000 * ( L2_RQSTS.REFERENCES - L2_RQSTS.MISS ) / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L2HPKI_All"
},
{
"BriefDescription": "L2 cache hits per kilo instruction for all demand loads (including speculative)",
"MetricExpr": "1000 * L2_RQSTS.DEMAND_DATA_RD_HIT / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L2HPKI_Load"
},
{
"BriefDescription": "L3 cache true misses per kilo instruction for retired demand loads",
"MetricExpr": "1000 * MEM_LOAD_UOPS_RETIRED.L3_MISS / INST_RETIRED.ANY",
"MetricGroup": "Mem;CacheMisses",
"MetricName": "L3MPKI"
},
{ {
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses", "BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7*(DTLB_STORE_MISSES.WALK_COMPLETED+DTLB_LOAD_MISSES.WALK_COMPLETED+ITLB_MISSES.WALK_COMPLETED)) / ( CPU_CLK_UNHALTED.THREAD_ANY / 2 ) if #SMT_on else cycles", "MetricConstraint": "NO_NMI_WATCHDOG",
"MetricGroup": "TLB", "MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Mem;MemoryTLB",
"MetricName": "Page_Walks_Utilization" "MetricName": "Page_Walks_Utilization"
}, },
{
"BriefDescription": "Utilization of the core's Page Walker(s) serving STLB misses triggered by instruction/Load/Store accesses",
"MetricExpr": "( cpu@ITLB_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_LOAD_MISSES.WALK_DURATION\\,cmask\\=1@ + cpu@DTLB_STORE_MISSES.WALK_DURATION\\,cmask\\=1@ + 7 * ( DTLB_STORE_MISSES.WALK_COMPLETED + DTLB_LOAD_MISSES.WALK_COMPLETED + ITLB_MISSES.WALK_COMPLETED ) ) / ( ( CPU_CLK_UNHALTED.THREAD / 2 ) * ( 1 + CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / CPU_CLK_UNHALTED.REF_XCLK ) )",
"MetricGroup": "Mem;MemoryTLB_SMT",
"MetricName": "Page_Walks_Utilization_SMT"
},
{ {
"BriefDescription": "Average CPU Utilization", "BriefDescription": "Average CPU Utilization",
"MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@", "MetricExpr": "CPU_CLK_UNHALTED.REF_TSC / msr@tsc@",
"MetricGroup": "Summary", "MetricGroup": "HPC;Summary",
"MetricName": "CPU_Utilization" "MetricName": "CPU_Utilization"
}, },
{
"BriefDescription": "Measured Average Frequency for unhalted processors [GHz]",
"MetricExpr": "(CPU_CLK_UNHALTED.THREAD / CPU_CLK_UNHALTED.REF_TSC) * msr@tsc@ / 1000000000 / duration_time",
"MetricGroup": "Summary;Power",
"MetricName": "Average_Frequency"
},
{ {
"BriefDescription": "Giga Floating Point Operations Per Second", "BriefDescription": "Giga Floating Point Operations Per Second",
"MetricExpr": "( 1*( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2* FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4*( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8* FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 / duration_time", "MetricExpr": "( ( 1 * ( FP_ARITH_INST_RETIRED.SCALAR_SINGLE + FP_ARITH_INST_RETIRED.SCALAR_DOUBLE ) + 2 * FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE + 4 * ( FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE + FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE ) + 8 * FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE ) / 1000000000 ) / duration_time",
"MetricGroup": "FLOPS;Summary", "MetricGroup": "Cor;Flops;HPC",
"MetricName": "GFLOPs" "MetricName": "GFLOPs"
}, },
{ {
...@@ -108,17 +373,53 @@ ...@@ -108,17 +373,53 @@
"MetricName": "Turbo_Utilization" "MetricName": "Turbo_Utilization"
}, },
{ {
"BriefDescription": "Fraction of cycles where both hardware threads were active", "BriefDescription": "Fraction of cycles where both hardware Logical Processors were active",
"MetricExpr": "1 - CPU_CLK_THREAD_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_THREAD_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0", "MetricExpr": "1 - CPU_CLK_UNHALTED.ONE_THREAD_ACTIVE / ( CPU_CLK_UNHALTED.REF_XCLK_ANY / 2 ) if #SMT_on else 0",
"MetricGroup": "SMT;Summary", "MetricGroup": "SMT",
"MetricName": "SMT_2T_Utilization" "MetricName": "SMT_2T_Utilization"
}, },
{ {
"BriefDescription": "Fraction of cycles spent in Kernel mode", "BriefDescription": "Fraction of cycles spent in the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD:k / CPU_CLK_UNHALTED.THREAD", "MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / CPU_CLK_UNHALTED.THREAD",
"MetricGroup": "Summary", "MetricGroup": "OS",
"MetricName": "Kernel_Utilization" "MetricName": "Kernel_Utilization"
}, },
{
"BriefDescription": "Cycles Per Instruction for the Operating System (OS) Kernel mode",
"MetricExpr": "CPU_CLK_UNHALTED.THREAD_P:k / INST_RETIRED.ANY_P:k",
"MetricGroup": "OS",
"MetricName": "Kernel_CPI"
},
{
"BriefDescription": "Average external Memory Bandwidth Use for reads and writes [GB / sec]",
"MetricExpr": "( 64 * ( uncore_imc@cas_count_read@ + uncore_imc@cas_count_write@ ) / 1000000000 ) / duration_time",
"MetricGroup": "HPC;Mem;MemoryBW;SoC",
"MetricName": "DRAM_BW_Use"
},
{
"BriefDescription": "Average latency of data read request to external memory (in nanoseconds). Accounts for demand loads and L1/L2 prefetches",
"MetricExpr": "1000000000 * ( cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x35\\,umask\\=0x3\\,filter_opc\\=0x182@ ) / ( cbox_0@event\\=0x0@ / duration_time )",
"MetricGroup": "Mem;MemoryLat;SoC",
"MetricName": "MEM_Read_Latency"
},
{
"BriefDescription": "Average number of parallel data read requests to external memory. Accounts for demand loads and L1/L2 prefetches",
"MetricExpr": "cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182@ / cbox@event\\=0x36\\,umask\\=0x3\\,filter_opc\\=0x182\\,thresh\\=1@",
"MetricGroup": "Mem;MemoryBW;SoC",
"MetricName": "MEM_Parallel_Reads"
},
{
"BriefDescription": "Socket actual clocks when any core is active on that socket",
"MetricExpr": "cbox_0@event\\=0x0@",
"MetricGroup": "SoC",
"MetricName": "Socket_CLKS"
},
{
"BriefDescription": "Instructions per Far Branch ( Far Branches apply upon transition from application to operating system, handling interrupts, exceptions) [lower number means higher occurrence rate]",
"MetricExpr": "INST_RETIRED.ANY / BR_INST_RETIRED.FAR_BRANCH:u",
"MetricGroup": "Branches;OS",
"MetricName": "IpFarBranch"
},
{ {
"BriefDescription": "C3 residency percent per core", "BriefDescription": "C3 residency percent per core",
"MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100", "MetricExpr": "(cstate_core@c3\\-residency@ / msr@tsc@) * 100",
......
tools/perf/pmu-events/arch/x86/broadwellde/cache.json
View file @ 34cb72ef
[ [
{ {
"BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x51",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.FB_FULL",
"SampleAfterValue": "2000003",
"UMask": "0x2"
},
{
"BriefDescription": "L1D miss oustandings duration in cycles",
"Counter": "2",
"CounterHTOff": "2",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"AnyThread": "1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"CounterHTOff": "2",
"CounterMask": "1",
"EventCode": "0x48",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Not rejected writebacks that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x27",
"EventName": "L2_DEMAND_RQSTS.WB_HIT",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.",
"SampleAfterValue": "200003",
"UMask": "0x50"
},
{
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.ALL",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
"UMask": "0x7"
},
{
"BriefDescription": "L2 cache lines in E state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.E",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
"UMask": "0x4"
},
{
"BriefDescription": "L2 cache lines in I state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.I",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
"UMask": "0x1"
},
{
"BriefDescription": "L2 cache lines in S state filling L2",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF1",
"EventName": "L2_LINES_IN.S",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.",
"SampleAfterValue": "100003",
"UMask": "0x2"
},
{
"BriefDescription": "Clean L2 cache lines evicted by demand.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF2",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN",
"SampleAfterValue": "100003",
"UMask": "0x5"
},
{
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24", "EventCode": "0x24",
"UMask": "0x21", "EventName": "L2_RQSTS.ALL_CODE_RD",
"BriefDescription": "Demand Data Read miss L2, no rejects", "PublicDescription": "This event counts the total number of L2 code requests.",
"SampleAfterValue": "200003",
"UMask": "0xe4"
},
{
"BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.", "EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xe1"
}, },
{ {
"BriefDescription": "Demand requests that miss L2 cache.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24", "EventCode": "0x24",
"UMask": "0x22", "EventName": "L2_RQSTS.ALL_DEMAND_MISS",
"BriefDescription": "RFO requests that miss L2 cache.", "SampleAfterValue": "200003",
"UMask": "0x27"
},
{
"BriefDescription": "Demand requests to L2 cache.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.RFO_MISS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES",
"SampleAfterValue": "200003",
"UMask": "0xe7"
},
{
"BriefDescription": "Requests from L2 hardware prefetchers",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_PF",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.",
"SampleAfterValue": "200003",
"UMask": "0xf8"
},
{
"BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.ALL_RFO",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xe2"
}, },
{ {
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24", "EventCode": "0x24",
"UMask": "0x24", "EventName": "L2_RQSTS.CODE_RD_HIT",
"SampleAfterValue": "200003",
"UMask": "0x44"
},
{
"BriefDescription": "L2 cache misses when fetching instructions.", "BriefDescription": "L2 cache misses when fetching instructions.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.CODE_RD_MISS", "EventName": "L2_RQSTS.CODE_RD_MISS",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x24"
}, },
{ {
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24", "EventCode": "0x24",
"UMask": "0x27", "EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT",
"BriefDescription": "Demand requests that miss L2 cache.", "PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003",
"UMask": "0x41"
},
{
"BriefDescription": "Demand Data Read miss L2, no rejects",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_MISS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_MISS",
"PublicDescription": "This event counts the number of demand Data Read requests that miss L2 cache. Only not rejected loads are counted.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x21"
}, },
{ {
"BriefDescription": "L2 prefetch requests that hit L2 cache",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24", "EventCode": "0x24",
"UMask": "0x30", "EventName": "L2_RQSTS.L2_PF_HIT",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.",
"SampleAfterValue": "200003",
"UMask": "0x50"
},
{
"BriefDescription": "L2 prefetch requests that miss L2 cache", "BriefDescription": "L2 prefetch requests that miss L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.L2_PF_MISS", "EventName": "L2_RQSTS.L2_PF_MISS",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.", "PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that miss L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x30"
}, },
{ {
"EventCode": "0x24",
"UMask": "0x3f",
"BriefDescription": "All requests that miss L2 cache.", "BriefDescription": "All requests that miss L2 cache.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.MISS", "EventName": "L2_RQSTS.MISS",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x3f"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "All L2 requests.",
"UMask": "0x41",
"BriefDescription": "Demand Data Read requests that hit L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.DEMAND_DATA_RD_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of demand Data Read requests that hit L2 cache. Only not rejected loads are counted.", "EventCode": "0x24",
"EventName": "L2_RQSTS.REFERENCES",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xff"
}, },
{ {
"EventCode": "0x24",
"UMask": "0x42",
"BriefDescription": "RFO requests that hit L2 cache.", "BriefDescription": "RFO requests that hit L2 cache.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_HIT", "EventName": "L2_RQSTS.RFO_HIT",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x42"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "RFO requests that miss L2 cache.",
"UMask": "0x44",
"BriefDescription": "L2 cache hits when fetching instructions, code reads.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.CODE_RD_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x24",
"EventName": "L2_RQSTS.RFO_MISS",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x22"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
"UMask": "0x50",
"BriefDescription": "L2 prefetch requests that hit L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.L2_PF_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of requests from the L2 hardware prefetchers that hit L2 cache. L3 prefetch new types.", "EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_PF",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "Transactions accessing L2 pipe",
"UMask": "0xe1",
"BriefDescription": "Demand Data Read requests",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_DATA_RD", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of demand Data Read requests (including requests from L1D hardware prefetchers). These loads may hit or miss L2 cache. Only non rejected loads are counted.", "EventCode": "0xF0",
"EventName": "L2_TRANS.ALL_REQUESTS",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x80"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "L2 cache accesses when fetching instructions",
"UMask": "0xe2",
"BriefDescription": "RFO requests to L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_RFO", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the total number of RFO (read for ownership) requests to L2 cache. L2 RFO requests include both L1D demand RFO misses as well as L1D RFO prefetches.", "EventCode": "0xF0",
"EventName": "L2_TRANS.CODE_RD",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "Demand Data Read requests that access L2 cache",
"UMask": "0xe4",
"BriefDescription": "L2 code requests",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_CODE_RD", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the total number of L2 code requests.", "EventCode": "0xF0",
"EventName": "L2_TRANS.DEMAND_DATA_RD",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "L1D writebacks that access L2 cache",
"UMask": "0xe7",
"BriefDescription": "Demand requests to L2 cache.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_DEMAND_REFERENCES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L1D_WB",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "L2 fill requests that access L2 cache",
"UMask": "0xf8",
"BriefDescription": "Requests from L2 hardware prefetchers",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.ALL_PF", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the total number of requests from the L2 hardware prefetchers.", "EventCode": "0xF0",
"EventName": "L2_TRANS.L2_FILL",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x24", "BriefDescription": "L2 writebacks that access L2 cache",
"UMask": "0xff",
"BriefDescription": "All L2 requests.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_RQSTS.REFERENCES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xF0",
"EventName": "L2_TRANS.L2_WB",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0x27", "BriefDescription": "RFO requests that access L2 cache",
"UMask": "0x50",
"BriefDescription": "Not rejected writebacks that hit L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_DEMAND_RQSTS.WB_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of WB requests that hit L2 cache.", "EventCode": "0xF0",
"EventName": "L2_TRANS.RFO",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.",
"SampleAfterValue": "200003", "SampleAfterValue": "200003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
},
{
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}, },
{ {
"EventCode": "0x2E",
"UMask": "0x41",
"BriefDescription": "Core-originated cacheable demand requests missed L3", "BriefDescription": "Core-originated cacheable demand requests missed L3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.MISS", "EventName": "LONGEST_LAT_CACHE.MISS",
"PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "PublicDescription": "This event counts core-originated cacheable demand requests that miss the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x41"
}, },
{ {
"EventCode": "0x2E",
"UMask": "0x4f",
"BriefDescription": "Core-originated cacheable demand requests that refer to L3", "BriefDescription": "Core-originated cacheable demand requests that refer to L3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x2E",
"EventName": "LONGEST_LAT_CACHE.REFERENCE", "EventName": "LONGEST_LAT_CACHE.REFERENCE",
"PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.", "PublicDescription": "This event counts core-originated cacheable demand requests that refer to the last level cache (LLC). Demand requests include loads, RFOs, and hardware prefetches from L1D, and instruction fetches from IFU.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4f"
}, },
{ {
"EventCode": "0x48", "BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)",
"UMask": "0x1",
"BriefDescription": "L1D miss oustandings duration in cycles",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING",
"PublicDescription": "This event counts duration of L1D miss outstanding, that is each cycle number of Fill Buffers (FB) outstanding required by Demand Reads. FB either is held by demand loads, or it is held by non-demand loads and gets hit at least once by demand. The valid outstanding interval is defined until the FB deallocation by one of the following ways: from FB allocation, if FB is allocated by demand; from the demand Hit FB, if it is allocated by hardware or software prefetch.\nNote: In the L1D, a Demand Read contains cacheable or noncacheable demand loads, including ones causing cache-line splits and reads due to page walks resulted from any request type.",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES",
"CounterMask": "1",
"PublicDescription": "This event counts duration of L1D miss outstanding in cycles.",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x1",
"BriefDescription": "Cycles with L1D load Misses outstanding from any thread on physical core.",
"Counter": "2",
"EventName": "L1D_PEND_MISS.PENDING_CYCLES_ANY",
"AnyThread": "1",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "2"
},
{
"EventCode": "0x48",
"UMask": "0x2",
"BriefDescription": "Cycles a demand request was blocked due to Fill Buffers inavailability.",
"Counter": "0,1,2,3",
"EventName": "L1D_PEND_MISS.FB_FULL",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x51",
"UMask": "0x1",
"BriefDescription": "L1D data line replacements",
"Counter": "0,1,2,3",
"EventName": "L1D.REPLACEMENT",
"PublicDescription": "This event counts L1D data line replacements including opportunistic replacements, and replacements that require stall-for-replace or block-for-replace.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"Errata": "BDM76",
"PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"CounterMask": "1",
"Errata": "BDM76",
"PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x1",
"BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
"CounterMask": "6",
"Errata": "BDM76",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x2",
"BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"Errata": "BDM76",
"PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x4",
"BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"Errata": "BDM76",
"PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x4",
"BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"CounterMask": "1",
"Errata": "BDM76",
"PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x8",
"BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"Errata": "BDM76",
"PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x60",
"UMask": "0x8",
"BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"CounterMask": "1",
"Errata": "BDM76",
"PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x63",
"UMask": "0x2",
"BriefDescription": "Cycles when L1D is locked",
"Counter": "0,1,2,3",
"EventName": "LOCK_CYCLES.CACHE_LOCK_DURATION",
"PublicDescription": "This event counts the number of cycles when the L1D is locked. It is a superset of the 0x1 mask (BUS_LOCK_CLOCKS.BUS_LOCK_DURATION).",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xB0",
"UMask": "0x1",
"BriefDescription": "Demand Data Read requests sent to uncore",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.", "Data_LA": "1",
"SampleAfterValue": "100003", "Errata": "BDM100",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x2"
}, },
{ {
"EventCode": "0xB0", "BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)",
"UMask": "0x2",
"BriefDescription": "Cacheable and noncachaeble code read requests",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This event counts both cacheable and noncachaeble code read requests.", "Data_LA": "1",
"SampleAfterValue": "100003", "Errata": "BDM100",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).",
"SampleAfterValue": "20011",
"UMask": "0x4"
}, },
{ {
"EventCode": "0xB0", "BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)",
"UMask": "0x4",
"BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.DEMAND_RFO", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.", "Data_LA": "1",
"SampleAfterValue": "100003", "Errata": "BDM100",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",
"SampleAfterValue": "20011",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xB0", "BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)",
"UMask": "0x8",
"BriefDescription": "Demand and prefetch data reads",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS.ALL_DATA_RD", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.", "Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD2",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0xb2",
"UMask": "0x1",
"BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xB7, 0xBB",
"UMask": "0x1",
"BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"Counter": "0,1,2,3",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x11",
"BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDE70, BDM100",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS", "SampleAfterValue": "100007",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.", "UMask": "0x1"
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD0", "BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)",
"UMask": "0x12", "Counter": "0,1,2,3",
"BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "SampleAfterValue": "100007",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES", "UMask": "0x4"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"SampleAfterValue": "100003",
"L1_Hit_Indication": "1",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD0", "BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
"UMask": "0x21", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"Errata": "BDM35",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3" "UMask": "0x20"
}, },
{ {
"EventCode": "0xD0", "BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)",
"UMask": "0x41", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDE70",
"EventCode": "0xD3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "SampleAfterValue": "100007",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS", "UMask": "0x10"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD0", "BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
"UMask": "0x42", "Counter": "0,1,2,3",
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"L1_Hit_Indication": "1", "UMask": "0x40"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD0", "BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)",
"UMask": "0x81",
"BriefDescription": "All retired load uops. (Precise Event - PEBS)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD0",
"UMask": "0x82",
"BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"L1_Hit_Indication": "1", "UMask": "0x1"
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD1", "BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops with L1 cache hits as data sources. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_HIT", "SampleAfterValue": "100003",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data source were hits in the nearest-level (L1) cache.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load. This event also counts SW prefetches independent of the actual data source.", "UMask": "0x8"
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD1",
"UMask": "0x2",
"BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)", "BriefDescription": "Retired load uops with L2 cache hits as data sources. (Precise Event - PEBS)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT", "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM35", "Errata": "BDM35",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_HIT",
"PEBS": "1",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the mid-level (L2) cache.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3" "UMask": "0x2"
}, },
{ {
"EventCode": "0xD1", "BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
"UMask": "0x4", "Counter": "0,1,2,3",
"BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"Errata": "BDM100",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",
"SampleAfterValue": "50021", "SampleAfterValue": "50021",
"CounterHTOff": "0,1,2,3" "UMask": "0x10"
}, },
{ {
"EventCode": "0xD1", "BriefDescription": "Hit in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS)",
"UMask": "0x8",
"BriefDescription": "Retired load uops misses in L1 cache as data sources. Uses PEBS.",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L1_MISS", "CounterHTOff": "0,1,2,3",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the nearest-level (L1) cache. Counting excludes unknown and UC data source.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD1",
"UMask": "0x10",
"BriefDescription": "Retired load uops with L2 cache misses as data sources. Uses PEBS.",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDM100",
"EventCode": "0xD1",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_HIT",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were data hits in the last-level (L3) cache without snoops required.",
"EventName": "MEM_LOAD_UOPS_RETIRED.L2_MISS",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were misses in the mid-level (L2) cache. Counting excludes unknown and UC data source.",
"SampleAfterValue": "50021", "SampleAfterValue": "50021",
"CounterHTOff": "0,1,2,3" "UMask": "0x4"
}, },
{ {
"EventCode": "0xD1",
"UMask": "0x20",
"BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).", "BriefDescription": "Miss in last-level (L3) cache. Excludes Unknown data-source. (Precise Event - PEBS).",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS", "CounterHTOff": "0,1,2,3",
"Data_LA": "1",
"Errata": "BDM100, BDE70", "Errata": "BDM100, BDE70",
"SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xD1", "EventCode": "0xD1",
"UMask": "0x40", "EventName": "MEM_LOAD_UOPS_RETIRED.L3_MISS",
"BriefDescription": "Retired load uops which data sources were load uops missed L1 but hit FB due to preceding miss to the same cache line with data not ready. (Precise Event - PEBS)",
"Data_LA": "1",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "SampleAfterValue": "100007",
"EventName": "MEM_LOAD_UOPS_RETIRED.HIT_LFB", "UMask": "0x20"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were load uops missed L1 but hit a fill buffer due to a preceding miss to the same cache line with the data not ready.\nNote: Only two data-sources of L1/FB are applicable for AVX-256bit even though the corresponding AVX load could be serviced by a deeper level in the memory hierarchy. Data source is reported for the Low-half load.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD2", "BriefDescription": "All retired load uops. (Precise Event - PEBS)",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops which data sources were L3 hit and cross-core snoop missed in on-pkg core cache. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_LOADS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement. This event also counts SW prefetches.",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_MISS", "SampleAfterValue": "2000003",
"Errata": "BDM100", "UMask": "0x81"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 Hit and a cross-core snoop missed in the on-pkg core cache.",
"SampleAfterValue": "20011",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD2", "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
"UMask": "0x2", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops which data sources were L3 and cross-core snoop hits in on-pkg core cache. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.ALL_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops retired to the architected path with a filter on bits 0 and 1 applied.\nNote: This event ?ounts AVX-256bit load/store double-pump memory uops as a single uop at retirement.",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HIT", "SampleAfterValue": "2000003",
"Errata": "BDM100", "UMask": "0x82"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were L3 hit and a cross-core snoop hit in the on-pkg core cache.",
"SampleAfterValue": "20011",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD2", "BriefDescription": "Retired load uops with locked access. (Precise Event - PEBS)",
"UMask": "0x4", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops which data sources were HitM responses from shared L3. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"Errata": "BDM35",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.LOCK_LOADS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with locked access retired to the architected path.",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_HITM", "SampleAfterValue": "100007",
"Errata": "BDM100", "UMask": "0x21"
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were HitM responses from a core on same socket (shared L3).",
"SampleAfterValue": "20011",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD2", "BriefDescription": "Retired load uops that split across a cacheline boundary.(Precise Event - PEBS)",
"UMask": "0x8", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uops which data sources were hits in L3 without snoops required. (Precise Event - PEBS)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_LOADS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted load uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"EventName": "MEM_LOAD_UOPS_L3_HIT_RETIRED.XSNP_NONE",
"Errata": "BDM100",
"PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts retired load uops which data sources were hits in the last-level (L3) cache without snoops required.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3" "UMask": "0x41"
}, },
{ {
"EventCode": "0xD3", "BriefDescription": "Retired store uops that split across a cacheline boundary. (Precise Event - PEBS)",
"UMask": "0x1", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.SPLIT_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts line-splitted store uops retired to the architected path. A line split is across 64B cache-line which includes a page split (4K).",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.LOCAL_DRAM", "SampleAfterValue": "100003",
"Errata": "BDE70, BDM100", "UMask": "0x42"
"PublicDescription": "This event counts retired load uops where the data came from local DRAM. This does not include hardware prefetches. This is a precise event.",
"SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD3", "BriefDescription": "Retired load uops that miss the STLB. (Precise Event - PEBS)",
"UMask": "0x4", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uop whose Data Source was: remote DRAM either Snoop not needed or Snoop Miss (RspI) (Precise Event)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_LOADS",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts load uops with true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_DRAM", "SampleAfterValue": "100003",
"Errata": "BDE70", "UMask": "0x11"
"SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD3", "BriefDescription": "Retired store uops that miss the STLB. (Precise Event - PEBS)",
"UMask": "0x10", "Counter": "0,1,2,3",
"BriefDescription": "Retired load uop whose Data Source was: Remote cache HITM (Precise Event)", "CounterHTOff": "0,1,2,3",
"Data_LA": "1", "Data_LA": "1",
"EventCode": "0xD0",
"EventName": "MEM_UOPS_RETIRED.STLB_MISS_STORES",
"L1_Hit_Indication": "1",
"PEBS": "1", "PEBS": "1",
"Counter": "0,1,2,3", "PublicDescription": "This is a precise version (that is, uses PEBS) of the event that counts store uops true STLB miss retired to the architected path. True STLB miss is an uop triggering page walk that gets completed without blocks, and later gets retired. This page walk can end up with or without a fault.",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_HITM", "SampleAfterValue": "100003",
"Errata": "BDE70", "UMask": "0x12"
"SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3"
}, },
{ {
"EventCode": "0xD3", "BriefDescription": "Demand and prefetch data reads",
"UMask": "0x20",
"BriefDescription": "Retired load uop whose Data Source was: forwarded from remote cache (Precise Event)",
"Data_LA": "1",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MEM_LOAD_UOPS_L3_MISS_RETIRED.REMOTE_FWD", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDE70", "EventCode": "0xB0",
"SampleAfterValue": "100007", "EventName": "OFFCORE_REQUESTS.ALL_DATA_RD",
"CounterHTOff": "0,1,2,3" "PublicDescription": "This event counts the demand and prefetch data reads. All Core Data Reads include cacheable Demands and L2 prefetchers (not L3 prefetchers). Counting also covers reads due to page walks resulted from any request type.",
"SampleAfterValue": "100003",
"UMask": "0x8"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Cacheable and noncachaeble code read requests",
"UMask": "0x1",
"BriefDescription": "Demand Data Read requests that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.DEMAND_DATA_RD", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts Demand Data Read requests that access L2 cache, including rejects.", "EventCode": "0xB0",
"SampleAfterValue": "200003", "EventName": "OFFCORE_REQUESTS.DEMAND_CODE_RD",
"CounterHTOff": "0,1,2,3,4,5,6,7" "PublicDescription": "This event counts both cacheable and noncachaeble code read requests.",
"SampleAfterValue": "100003",
"UMask": "0x2"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Demand Data Read requests sent to uncore",
"UMask": "0x2",
"BriefDescription": "RFO requests that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.RFO", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts Read for Ownership (RFO) requests that access L2 cache.", "EventCode": "0xB0",
"SampleAfterValue": "200003", "EventName": "OFFCORE_REQUESTS.DEMAND_DATA_RD",
"CounterHTOff": "0,1,2,3,4,5,6,7" "PublicDescription": "This event counts the Demand Data Read requests sent to uncore. Use it in conjunction with OFFCORE_REQUESTS_OUTSTANDING to determine average latency in the uncore.",
"SampleAfterValue": "100003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Demand RFO requests including regular RFOs, locks, ItoM",
"UMask": "0x4",
"BriefDescription": "L2 cache accesses when fetching instructions",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.CODE_RD", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of L2 cache accesses when fetching instructions.", "EventCode": "0xB0",
"SampleAfterValue": "200003", "EventName": "OFFCORE_REQUESTS.DEMAND_RFO",
"CounterHTOff": "0,1,2,3,4,5,6,7" "PublicDescription": "This event counts the demand RFO (read for ownership) requests including regular RFOs, locks, ItoM.",
"SampleAfterValue": "100003",
"UMask": "0x4"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Offcore requests buffer cannot take more entries for this thread core.",
"UMask": "0x8",
"BriefDescription": "L2 or L3 HW prefetches that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.ALL_PF", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts L2 or L3 HW prefetches that access L2 cache including rejects.", "EventCode": "0xb2",
"SampleAfterValue": "200003", "EventName": "OFFCORE_REQUESTS_BUFFER.SQ_FULL",
"CounterHTOff": "0,1,2,3,4,5,6,7" "PublicDescription": "This event counts the number of cases when the offcore requests buffer cannot take more entries for the core. This can happen when the superqueue does not contain eligible entries, or when L1D writeback pending FIFO requests is full.\nNote: Writeback pending FIFO has six entries.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Offcore outstanding cacheable Core Data Read transactions in SuperQueue (SQ), queue to uncore",
"UMask": "0x10",
"BriefDescription": "L1D writebacks that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.L1D_WB", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts L1D writebacks that access L2 cache.", "Errata": "BDM76",
"SampleAfterValue": "200003", "EventCode": "0x60",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventName": "OFFCORE_REQUESTS_OUTSTANDING.ALL_DATA_RD",
"PublicDescription": "This event counts the number of offcore outstanding cacheable Core Data Read transactions in the super queue every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Cycles when offcore outstanding cacheable Core Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"UMask": "0x20",
"BriefDescription": "L2 fill requests that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.L2_FILL", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts L2 fill requests that access L2 cache.", "CounterMask": "1",
"SampleAfterValue": "200003", "Errata": "BDM76",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD",
"PublicDescription": "This event counts cycles when offcore outstanding cacheable Core Data Read transactions are present in the super queue. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"UMask": "0x8"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Cycles when offcore outstanding Demand Data Read transactions are present in SuperQueue (SQ), queue to uncore",
"UMask": "0x40",
"BriefDescription": "L2 writebacks that access L2 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.L2_WB", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts L2 writebacks that access L2 cache.", "CounterMask": "1",
"SampleAfterValue": "200003", "Errata": "BDM76",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_DATA_RD",
"PublicDescription": "This event counts cycles when offcore outstanding Demand Data Read transactions are present in the super queue (SQ). A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation).",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xF0", "BriefDescription": "Offcore outstanding demand rfo reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"UMask": "0x80",
"BriefDescription": "Transactions accessing L2 pipe",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_TRANS.ALL_REQUESTS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts transactions that access the L2 pipe including snoops, pagewalks, and so on.", "CounterMask": "1",
"SampleAfterValue": "200003", "Errata": "BDM76",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO",
"PublicDescription": "This event counts the number of offcore outstanding demand rfo Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
}, },
{ {
"EventCode": "0xF1", "BriefDescription": "Offcore outstanding code reads transactions in SuperQueue (SQ), queue to uncore, every cycle",
"UMask": "0x1",
"BriefDescription": "L2 cache lines in I state filling L2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_LINES_IN.I", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of L2 cache lines in the Invalidate state filling the L2. Counting does not cover rejects.", "Errata": "BDM76",
"SampleAfterValue": "100003", "EventCode": "0x60",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_CODE_RD",
"PublicDescription": "This event counts the number of offcore outstanding Code Reads transactions in the super queue every cycle. The Offcore outstanding state of the transaction lasts from the L2 miss until the sending transaction completion to requestor (SQ deallocation). See the corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"UMask": "0x2"
}, },
{ {
"EventCode": "0xF1", "BriefDescription": "Offcore outstanding Demand Data Read transactions in uncore queue.",
"UMask": "0x2",
"BriefDescription": "L2 cache lines in S state filling L2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_LINES_IN.S", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of L2 cache lines in the Shared state filling the L2. Counting does not cover rejects.", "Errata": "BDM76",
"SampleAfterValue": "100003", "EventCode": "0x60",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD",
"PublicDescription": "This event counts the number of offcore outstanding Demand Data Read transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor. See the corresponding Umask under OFFCORE_REQUESTS.\nNote: A prefetch promoted to Demand is counted from the promotion point.",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xF1", "BriefDescription": "Cycles with at least 6 offcore outstanding Demand Data Read transactions in uncore queue.",
"UMask": "0x4",
"BriefDescription": "L2 cache lines in E state filling L2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_LINES_IN.E", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of L2 cache lines in the Exclusive state filling the L2. Counting does not cover rejects.", "CounterMask": "6",
"SampleAfterValue": "100003", "Errata": "BDM76",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0x60",
"EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_DATA_RD_GE_6",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xF1", "BriefDescription": "Offcore outstanding RFO store transactions in SuperQueue (SQ), queue to uncore",
"UMask": "0x7",
"BriefDescription": "L2 cache lines filling L2",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_LINES_IN.ALL", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of L2 cache lines filling the L2. Counting does not cover rejects.", "Errata": "BDM76",
"SampleAfterValue": "100003", "EventCode": "0x60",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventName": "OFFCORE_REQUESTS_OUTSTANDING.DEMAND_RFO",
"PublicDescription": "This event counts the number of offcore outstanding RFO (store) transactions in the super queue (SQ) every cycle. A transaction is considered to be in the Offcore outstanding state between L2 miss and transaction completion sent to requestor (SQ de-allocation). See corresponding Umask under OFFCORE_REQUESTS.",
"SampleAfterValue": "2000003",
"UMask": "0x4"
}, },
{ {
"EventCode": "0xF2", "BriefDescription": "Offcore response can be programmed only with a specific pair of event select and counter MSR, and with specific event codes and predefine mask bit value in a dedicated MSR to specify attributes of the offcore transaction.",
"UMask": "0x5",
"BriefDescription": "Clean L2 cache lines evicted by demand.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "L2_LINES_OUT.DEMAND_CLEAN", "CounterHTOff": "0,1,2,3",
"EventCode": "0xB7, 0xBB",
"EventName": "OFFCORE_RESPONSE",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0xf4",
"UMask": "0x10",
"BriefDescription": "Split locks in SQ", "BriefDescription": "Split locks in SQ",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xf4",
"EventName": "SQ_MISC.SPLIT_LOCK", "EventName": "SQ_MISC.SPLIT_LOCK",
"PublicDescription": "This event counts the number of split locks in the super queue.", "PublicDescription": "This event counts the number of split locks in the super queue.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwellde/floating-point.json
View file @ 34cb72ef
[ [
{ {
"EventCode": "0xC1", "BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x8",
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE", "CounterHTOff": "0,1,2,3",
"Errata": "BDM30", "EventCode": "0xC7",
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE",
"SampleAfterValue": "100003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0xC1", "BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x10",
"BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX", "CounterHTOff": "0,1,2,3",
"Errata": "BDM30",
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0xC7", "EventCode": "0xC7",
"UMask": "0x1", "EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE",
"BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x8"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x2",
"BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE", "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x10"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x3",
"BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR", "CounterHTOff": "0,1,2,3",
"EventCode": "0xc7",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x20"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"UMask": "0x4",
"BriefDescription": "Number of SSE/AVX computational 128-bit packed double precision floating-point instructions retired. Each count represents 2 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_DOUBLE", "CounterHTOff": "0,1,2,3",
"SampleAfterValue": "2000003", "EventCode": "0xC7",
"CounterHTOff": "0,1,2,3" "EventName": "FP_ARITH_INST_RETIRED.DOUBLE",
"SampleAfterValue": "2000006",
"UMask": "0x15"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x8",
"BriefDescription": "Number of SSE/AVX computational 128-bit packed single precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.128B_PACKED_SINGLE", "CounterHTOff": "0,1,2,3",
"SampleAfterValue": "2000003", "EventCode": "0xC7",
"CounterHTOff": "0,1,2,3" "EventName": "FP_ARITH_INST_RETIRED.PACKED",
"SampleAfterValue": "2000004",
"UMask": "0x3c"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational scalar floating-point instructions retired. Applies to SSE* and AVX* scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x10",
"BriefDescription": "Number of SSE/AVX computational 256-bit packed double precision floating-point instructions retired. Each count represents 4 computations. Applies to SSE* and AVX* packed double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_DOUBLE", "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x3"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Number of SSE/AVX computational scalar double precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar double precision floating-point instructions: ADD SUB MUL DIV MIN MAX SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x15",
"BriefDescription": "Number of SSE/AVX computational double precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.DOUBLE", "CounterHTOff": "0,1,2,3",
"SampleAfterValue": "2000006", "EventCode": "0xC7",
"CounterHTOff": "0,1,2,3" "EventName": "FP_ARITH_INST_RETIRED.SCALAR_DOUBLE",
"SampleAfterValue": "2000003",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xc7", "BriefDescription": "Number of SSE/AVX computational scalar single precision floating-point instructions retired. Each count represents 1 computation. Applies to SSE* and AVX* scalar single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT FM(N)ADD/SUB. FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"UMask": "0x20",
"BriefDescription": "Number of SSE/AVX computational 256-bit packed single precision floating-point instructions retired. Each count represents 8 computations. Applies to SSE* and AVX* packed single precision floating-point instructions: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.256B_PACKED_SINGLE", "CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SCALAR_SINGLE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x2"
}, },
{ {
"EventCode": "0xC7",
"UMask": "0x2a",
"BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.", "BriefDescription": "Number of SSE/AVX computational single precision floating-point instructions retired. Applies to SSE* and AVX*scalar, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RCP RSQRT SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element. ?.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xC7",
"EventName": "FP_ARITH_INST_RETIRED.SINGLE", "EventName": "FP_ARITH_INST_RETIRED.SINGLE",
"SampleAfterValue": "2000005", "SampleAfterValue": "2000005",
"CounterHTOff": "0,1,2,3" "UMask": "0x2a"
}, },
{ {
"EventCode": "0xC7", "BriefDescription": "Cycles with any input/output SSE or FP assist",
"UMask": "0x3c",
"BriefDescription": "Number of SSE/AVX computational packed floating-point instructions retired. Applies to SSE* and AVX*, packed, double and single precision floating-point: ADD SUB MUL DIV MIN MAX RSQRT RCP SQRT DPP FM(N)ADD/SUB. DPP and FM(N)ADD/SUB instructions count twice as they perform multiple calculations per element.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ARITH_INST_RETIRED.PACKED", "CounterHTOff": "0,1,2,3",
"SampleAfterValue": "2000004", "CounterMask": "1",
"CounterHTOff": "0,1,2,3" "EventCode": "0xCA",
"EventName": "FP_ASSIST.ANY",
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.",
"SampleAfterValue": "100003",
"UMask": "0x1e"
}, },
{ {
"EventCode": "0xCA", "BriefDescription": "Number of SIMD FP assists due to input values",
"UMask": "0x2",
"BriefDescription": "Number of X87 assists due to output value.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ASSIST.X87_OUTPUT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.", "EventCode": "0xCA",
"EventName": "FP_ASSIST.SIMD_INPUT",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA", "EventCode": "0xCA",
"UMask": "0x4", "EventName": "FP_ASSIST.SIMD_OUTPUT",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.",
"SampleAfterValue": "100003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of X87 assists due to input value.", "BriefDescription": "Number of X87 assists due to input value.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_INPUT", "EventName": "FP_ASSIST.X87_INPUT",
"PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.", "PublicDescription": "This event counts x87 floating point (FP) micro-code assist (invalid operation, denormal operand, SNaN operand) when the input value (one of the source operands to an FP instruction) is invalid.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0xCA", "BriefDescription": "Number of X87 assists due to output value.",
"UMask": "0x8",
"BriefDescription": "Number of SIMD FP assists due to Output values",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ASSIST.SIMD_OUTPUT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of SSE* floating point (FP) micro-code assist (numeric overflow/underflow) when the output value (destination register) is invalid. Counting covers only cases involving penalties that require micro-code assist intervention.", "EventCode": "0xCA",
"EventName": "FP_ASSIST.X87_OUTPUT",
"PublicDescription": "This event counts the number of x87 floating point (FP) micro-code assist (numeric overflow/underflow, inexact result) when the output value (destination register) is invalid.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0xCA", "BriefDescription": "Number of SIMD Move Elimination candidate uops that were eliminated.",
"UMask": "0x10",
"BriefDescription": "Number of SIMD FP assists due to input values",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ASSIST.SIMD_INPUT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts any input SSE* FP assist - invalid operation, denormal operand, dividing by zero, SNaN operand. Counting includes only cases involving penalties that required micro-code assist intervention.", "EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_ELIMINATED",
"SampleAfterValue": "1000003",
"UMask": "0x2"
},
{
"BriefDescription": "Number of SIMD Move Elimination candidate uops that were not eliminated.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x58",
"EventName": "MOVE_ELIMINATION.SIMD_NOT_ELIMINATED",
"SampleAfterValue": "1000003",
"UMask": "0x8"
},
{
"BriefDescription": "Number of transitions from AVX-256 to legacy SSE when penalty applicable.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM30",
"EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.AVX_TO_SSE",
"PublicDescription": "This event counts the number of transitions from AVX-256 to legacy SSE when penalty is applicable.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0xCA", "BriefDescription": "Number of transitions from SSE to AVX-256 when penalty applicable.",
"UMask": "0x1e",
"BriefDescription": "Cycles with any input/output SSE or FP assist",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "FP_ASSIST.ANY", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "Errata": "BDM30",
"PublicDescription": "This event counts cycles with any input and output SSE or x87 FP assist. If an input and output assist are detected on the same cycle the event increments by 1.", "EventCode": "0xC1",
"EventName": "OTHER_ASSISTS.SSE_TO_AVX",
"PublicDescription": "This event counts the number of transitions from legacy SSE to AVX-256 when penalty is applicable.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3" "UMask": "0x10"
},
{
"BriefDescription": "Micro-op dispatches cancelled due to insufficient SIMD physical register file read ports",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xA0",
"EventName": "UOP_DISPATCHES_CANCELLED.SIMD_PRF",
"PublicDescription": "This event counts the number of micro-operations cancelled after they were dispatched from the scheduler to the execution units when the total number of physical register read ports across all dispatch ports exceeds the read bandwidth of the physical register file. The SIMD_PRF subevent applies to the following instructions: VDPPS, DPPS, VPCMPESTRI, PCMPESTRI, VPCMPESTRM, PCMPESTRM, VFMADD*, VFMADDSUB*, VFMSUB*, VMSUBADD*, VFNMADD*, VFNMSUB*. See the Broadwell Optimization Guide for more information.",
"SampleAfterValue": "2000003",
"UMask": "0x3"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwellde/frontend.json
View file @ 34cb72ef
[ [
{ {
"EventCode": "0x79", "BriefDescription": "Counts the total number when the front end is resteered, mainly when the BPU cannot provide a correct prediction and this is corrected by other branch handling mechanisms at the front end.",
"UMask": "0x2",
"BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.EMPTY", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.", "EventCode": "0xe6",
"SampleAfterValue": "2000003", "EventName": "BACLEARS.ANY",
"CounterHTOff": "0,1,2,3" "SampleAfterValue": "100003",
"UMask": "0x1f"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"UMask": "0x4",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MITE_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "EventCode": "0xAB",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"UMask": "0x4",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MITE_CYCLES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "EventCode": "0x80",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.", "EventName": "ICACHE.HIT",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"UMask": "0x8",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.DSB_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "EventCode": "0x80",
"EventName": "ICACHE.IFDATA_STALL",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"UMask": "0x8",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.DSB_CYCLES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "EventCode": "0x80",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "EventName": "ICACHE.MISSES",
"SampleAfterValue": "2000003", "PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.",
"CounterHTOff": "0,1,2,3,4,5,6,7" "SampleAfterValue": "200003",
"UMask": "0x2"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"UMask": "0x10",
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_DSB_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "CounterMask": "4",
"EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS",
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x18"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"UMask": "0x10",
"BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_DSB_CYCLES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "EventCode": "0x79",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS",
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x18"
}, },
{ {
"EdgeDetect": "1", "BriefDescription": "Cycles MITE is delivering 4 Uops",
"EventCode": "0x79",
"UMask": "0x10",
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_DSB_OCCUR", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "4",
"PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS",
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x24"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Cycles MITE is delivering any Uop",
"UMask": "0x18",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering 4 Uops",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.ALL_DSB_CYCLES_4_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "4", "CounterMask": "1",
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "EventCode": "0x79",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS",
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x24"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from Decode Stream Buffer (DSB) path",
"UMask": "0x18",
"BriefDescription": "Cycles Decode Stream Buffer (DSB) is delivering any Uop",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.ALL_DSB_CYCLES_ANY_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.", "EventCode": "0x79",
"EventName": "IDQ.DSB_CYCLES",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path",
"UMask": "0x20",
"BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_MITE_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.", "EventCode": "0x79",
"EventName": "IDQ.DSB_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the Decode Stream Buffer (DSB) path. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Instruction Decode Queue (IDQ) empty cycles",
"UMask": "0x24",
"BriefDescription": "Cycles MITE is delivering 4 Uops",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.ALL_MITE_CYCLES_4_UOPS", "CounterHTOff": "0,1,2,3",
"CounterMask": "4", "EventCode": "0x79",
"PublicDescription": "This event counts the number of cycles 4 uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "EventName": "IDQ.EMPTY",
"PublicDescription": "This counts the number of cycles that the instruction decoder queue is empty and can indicate that the application may be bound in the front end. It does not determine whether there are uops being delivered to the Alloc stage since uops can be delivered by bypass skipping the Instruction Decode Queue (IDQ) when it is empty.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x79", "EventCode": "0x79",
"UMask": "0x24", "EventName": "IDQ.MITE_ALL_UOPS",
"BriefDescription": "Cycles MITE is delivering any Uop", "PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003",
"UMask": "0x3c"
},
{
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) from MITE path",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.ALL_MITE_CYCLES_ANY_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"PublicDescription": "This event counts the number of cycles uops were delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "EventCode": "0x79",
"EventName": "IDQ.MITE_CYCLES",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x79", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path",
"UMask": "0x30",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "EventCode": "0x79",
"EventName": "IDQ.MITE_UOPS",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy", "BriefDescription": "Cycles when uops are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_CYCLES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_CYCLES",
"PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.", "PublicDescription": "This event counts cycles during which uops are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x30"
}, },
{ {
"EdgeDetect": "1", "BriefDescription": "Cycles when uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"EventCode": "0x79",
"UMask": "0x30",
"BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MS_SWITCHES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EventCode": "0x79",
"EventName": "IDQ.MS_DSB_CYCLES",
"PublicDescription": "This event counts cycles during which uops initiated by Decode Stream Buffer (DSB) are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"BriefDescription": "Deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x79", "EventCode": "0x79",
"UMask": "0x3c", "EventName": "IDQ.MS_DSB_OCCUR",
"BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) from MITE path", "PublicDescription": "This event counts the number of deliveries to Instruction Decode Queue (IDQ) initiated by Decode Stream Buffer (DSB) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003",
"UMask": "0x10"
},
{
"BriefDescription": "Uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ.MITE_ALL_UOPS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of uops delivered to Instruction Decode Queue (IDQ) from the MITE path. Counting includes uops that may bypass the IDQ. This also means that uops are not being delivered from the Decode Stream Buffer (DSB).", "EventCode": "0x79",
"EventName": "IDQ.MS_DSB_UOPS",
"PublicDescription": "This event counts the number of uops initiated by Decode Stream Buffer (DSB) that are being delivered to Instruction Decode Queue (IDQ) while the Microcode Sequencer (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0x80", "BriefDescription": "Uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"UMask": "0x1",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Reads. both cacheable and noncacheable, including UC fetches",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ICACHE.HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of both cacheable and noncacheable Instruction Cache, Streaming Buffer and Victim Cache Reads including UC fetches.", "EventCode": "0x79",
"EventName": "IDQ.MS_MITE_UOPS",
"PublicDescription": "This event counts the number of uops initiated by MITE and delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x80", "BriefDescription": "Number of switches from DSB (Decode Stream Buffer) or MITE (legacy decode pipeline) to the Microcode Sequencer.",
"UMask": "0x2",
"BriefDescription": "Number of Instruction Cache, Streaming Buffer and Victim Cache Misses. Includes Uncacheable accesses.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ICACHE.MISSES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of instruction cache, streaming buffer and victim cache misses. Counting includes UC accesses.", "CounterMask": "1",
"SampleAfterValue": "200003", "EdgeDetect": "1",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventCode": "0x79",
"EventName": "IDQ.MS_SWITCHES",
"SampleAfterValue": "2000003",
"UMask": "0x30"
}, },
{ {
"EventCode": "0x80", "BriefDescription": "Uops delivered to Instruction Decode Queue (IDQ) while Microcode Sequenser (MS) is busy",
"UMask": "0x4",
"BriefDescription": "Cycles where a code fetch is stalled due to L1 instruction-cache miss.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ICACHE.IFDATA_STALL", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts cycles during which the demand fetch waits for data (wfdM104H) from L2 or iSB (opportunistic hit).", "EventCode": "0x79",
"EventName": "IDQ.MS_UOPS",
"PublicDescription": "This event counts the total number of uops delivered to Instruction Decode Queue (IDQ) while the Microcode Sequenser (MS) is busy. Counting includes uops that may bypass the IDQ. Uops maybe initiated by Decode Stream Buffer (DSB) or MITE.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x30"
}, },
{ {
"EventCode": "0x9C",
"UMask": "0x1",
"BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled", "BriefDescription": "Uops not delivered to Resource Allocation Table (RAT) per thread when backend of the machine is not stalled",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CORE", "EventName": "IDQ_UOPS_NOT_DELIVERED.CORE",
"PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.", "PublicDescription": "This event counts the number of uops not delivered to Resource Allocation Table (RAT) per thread adding 4 x when Resource Allocation Table (RAT) is not stalled and Instruction Decode Queue (IDQ) delivers x uops to Resource Allocation Table (RAT) (where x belongs to {0,1,2,3}). Counting does not cover cases when:\n a. IDQ-Resource Allocation Table (RAT) pipe serves the other thread;\n b. Resource Allocation Table (RAT) is stalled for the thread (including uop drops and clear BE conditions); \n c. Instruction Decode Queue (IDQ) delivers four uops.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"EventCode": "0x9C",
"UMask": "0x1",
"BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 4 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE", "CounterHTOff": "0,1,2,3",
"CounterMask": "4", "CounterMask": "4",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_0_UOPS_DELIV.CORE",
"PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.", "PublicDescription": "This event counts, on the per-thread basis, cycles when no uops are delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core =4.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"CounterMask": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"UMask": "0x1", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"Invert": "1",
"SampleAfterValue": "2000003",
"UMask": "0x1"
},
{
"BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled", "BriefDescription": "Cycles per thread when 3 or more uops are not delivered to Resource Allocation Table (RAT) when backend of the machine is not stalled",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE", "CounterHTOff": "0,1,2,3",
"CounterMask": "3", "CounterMask": "3",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_1_UOP_DELIV.CORE",
"PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.", "PublicDescription": "This event counts, on the per-thread basis, cycles when less than 1 uop is delivered to Resource Allocation Table (RAT). IDQ_Uops_Not_Delivered.core >=3.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"EventCode": "0x9C",
"UMask": "0x1",
"BriefDescription": "Cycles with less than 2 uops delivered by the front end.", "BriefDescription": "Cycles with less than 2 uops delivered by the front end.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE", "CounterHTOff": "0,1,2,3",
"CounterMask": "2", "CounterMask": "2",
"EventCode": "0x9C",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_2_UOP_DELIV.CORE",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"EventCode": "0x9C",
"UMask": "0x1",
"BriefDescription": "Cycles with less than 3 uops delivered by the front end.", "BriefDescription": "Cycles with less than 3 uops delivered by the front end.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE", "CounterHTOff": "0,1,2,3",
"CounterMask": "1", "CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"Invert": "1",
"EventCode": "0x9C", "EventCode": "0x9C",
"UMask": "0x1", "EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_LE_3_UOP_DELIV.CORE",
"BriefDescription": "Counts cycles FE delivered 4 uops or Resource Allocation Table (RAT) was stalling FE.",
"Counter": "0,1,2,3",
"EventName": "IDQ_UOPS_NOT_DELIVERED.CYCLES_FE_WAS_OK",
"CounterMask": "1",
"SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3"
},
{
"EventCode": "0xAB",
"UMask": "0x2",
"BriefDescription": "Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles.",
"Counter": "0,1,2,3",
"EventName": "DSB2MITE_SWITCHES.PENALTY_CYCLES",
"PublicDescription": "This event counts Decode Stream Buffer (DSB)-to-MITE switch true penalty cycles. These cycles do not include uops routed through because of the switch itself, for example, when Instruction Decode Queue (IDQ) pre-allocation is unavailable, or Instruction Decode Queue (IDQ) is full. SBD-to-MITE switch true penalty cycles happen after the merge mux (MM) receives Decode Stream Buffer (DSB) Sync-indication until receiving the first MITE uop. \nMM is placed before Instruction Decode Queue (IDQ) to merge uops being fed from the MITE and Decode Stream Buffer (DSB) paths. Decode Stream Buffer (DSB) inserts the Sync-indication whenever a Decode Stream Buffer (DSB)-to-MITE switch occurs.\nPenalty: A Decode Stream Buffer (DSB) hit followed by a Decode Stream Buffer (DSB) miss can cost up to six cycles in which no uops are delivered to the IDQ. Most often, such switches from the Decode Stream Buffer (DSB) to the legacy pipeline cost 02 cycles.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwellde/memory.json
View file @ 34cb72ef
[ [
{ {
"EventCode": "0x05", "BriefDescription": "Number of times HLE abort was triggered (PEBS)",
"UMask": "0x1",
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MISALIGN_MEM_REF.LOADS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Number of times HLE abort was triggered (PEBS).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x05", "BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"UMask": "0x2",
"BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "MISALIGN_MEM_REF.STORES", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
"UMask": "0x1",
"BriefDescription": "Number of times a TSX line had a cache conflict",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_CONFLICT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX line had a cache conflict.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
"UMask": "0x2",
"BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_CAPACITY_WRITE", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
"UMask": "0x4",
"BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times HLE caused a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
"UMask": "0x8",
"BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x80"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times HLE commit succeeded",
"UMask": "0x10",
"BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.COMMIT",
"PublicDescription": "Number of times HLE commit succeeded.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Number of times we entered an HLE region; does not count nested transactions",
"UMask": "0x20",
"BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.", "EventCode": "0xc8",
"EventName": "HLE_RETIRED.START",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x54", "BriefDescription": "Counts the number of machine clears due to memory order conflicts.",
"UMask": "0x40",
"BriefDescription": "Number of times we could not allocate Lock Buffer",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times we could not allocate Lock Buffer.", "EventCode": "0xC3",
"SampleAfterValue": "2000003", "EventName": "MACHINE_CLEARS.MEMORY_ORDERING",
"CounterHTOff": "0,1,2,3,4,5,6,7" "PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.",
"SampleAfterValue": "100003",
"UMask": "0x2"
}, },
{ {
"EventCode": "0x5d", "BriefDescription": "Loads with latency value being above 128",
"UMask": "0x1", "Counter": "3",
"BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "TX_EXEC.MISC1", "EventCode": "0xCD",
"SampleAfterValue": "2000003", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRIndex": "0x3F6",
"MSRValue": "0x80",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 128.",
"SampleAfterValue": "1009",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0x5d", "BriefDescription": "Loads with latency value being above 16",
"UMask": "0x2", "Counter": "3",
"BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "TX_EXEC.MISC2", "EventCode": "0xCD",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16",
"SampleAfterValue": "2000003", "MSRIndex": "0x3F6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRValue": "0x10",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 16.",
"SampleAfterValue": "20011",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0x5d", "BriefDescription": "Loads with latency value being above 256",
"UMask": "0x4", "Counter": "3",
"BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "TX_EXEC.MISC3", "EventCode": "0xCD",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256",
"SampleAfterValue": "2000003", "MSRIndex": "0x3F6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRValue": "0x100",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 256.",
"SampleAfterValue": "503",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0x5d", "BriefDescription": "Loads with latency value being above 32",
"UMask": "0x8", "Counter": "3",
"BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "TX_EXEC.MISC4", "EventCode": "0xCD",
"PublicDescription": "RTM region detected inside HLE.", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32",
"SampleAfterValue": "2000003", "MSRIndex": "0x3F6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRValue": "0x20",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 32.",
"SampleAfterValue": "100007",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0x5d", "BriefDescription": "Loads with latency value being above 4",
"UMask": "0x10", "Counter": "3",
"BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "TX_EXEC.MISC5", "EventCode": "0xCD",
"SampleAfterValue": "2000003", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRIndex": "0x3F6",
"MSRValue": "0x4",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above four.",
"SampleAfterValue": "100003",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xC3", "BriefDescription": "Loads with latency value being above 512",
"UMask": "0x2", "Counter": "3",
"BriefDescription": "Counts the number of machine clears due to memory order conflicts.", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "MACHINE_CLEARS.MEMORY_ORDERING", "EventCode": "0xCD",
"PublicDescription": "This event counts the number of memory ordering Machine Clears detected. Memory Ordering Machine Clears can result from one of the following:\n1. memory disambiguation,\n2. external snoop, or\n3. cross SMT-HW-thread snoop (stores) hitting load buffer.", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512",
"SampleAfterValue": "100003", "MSRIndex": "0x3F6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRValue": "0x200",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 512.",
"SampleAfterValue": "101",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Loads with latency value being above 64",
"UMask": "0x1", "Counter": "3",
"BriefDescription": "Number of times we entered an HLE region; does not count nested transactions", "CounterHTOff": "3",
"Counter": "0,1,2,3", "Errata": "BDM100, BDM35",
"EventName": "HLE_RETIRED.START", "EventCode": "0xCD",
"PublicDescription": "Number of times we entered an HLE region\n does not count nested transactions.", "EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64",
"SampleAfterValue": "2000003", "MSRIndex": "0x3F6",
"CounterHTOff": "0,1,2,3,4,5,6,7" "MSRValue": "0x40",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above 64.",
"SampleAfterValue": "2003",
"TakenAlone": "1",
"UMask": "0x1"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Loads with latency value being above 8",
"UMask": "0x2", "Counter": "3",
"BriefDescription": "Number of times HLE commit succeeded", "CounterHTOff": "3",
"Errata": "BDM100, BDM35",
"EventCode": "0xCD",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8",
"MSRIndex": "0x3F6",
"MSRValue": "0x8",
"PEBS": "2",
"PublicDescription": "This event counts loads with latency value being above eight.",
"SampleAfterValue": "50021",
"TakenAlone": "1",
"UMask": "0x1"
},
{
"BriefDescription": "Speculative cache line split load uops dispatched to L1 cache",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.COMMIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times HLE commit succeeded.", "EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.LOADS",
"PublicDescription": "This event counts speculative cache-line split load uops dispatched to the L1 cache.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Speculative cache line split STA uops dispatched to L1 cache",
"UMask": "0x4",
"BriefDescription": "Number of times HLE abort was triggered (PEBS)",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times HLE abort was triggered (PEBS).", "EventCode": "0x05",
"EventName": "MISALIGN_MEM_REF.STORES",
"PublicDescription": "This event counts speculative cache line split store-address (STA) uops dispatched to the L1 cache.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Number of times RTM abort was triggered (PEBS)",
"UMask": "0x8",
"BriefDescription": "Number of times an HLE execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED_MISC1", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times an HLE abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED",
"PEBS": "1",
"PublicDescription": "Number of times RTM abort was triggered (PEBS).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"UMask": "0x10",
"BriefDescription": "Number of times an HLE execution aborted due to uncommon conditions",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED_MISC2", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times the TSX watchdog signaled an HLE abort.", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC1",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"UMask": "0x20",
"BriefDescription": "Number of times an HLE execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED_MISC3", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times a disallowed operation caused an HLE abort.", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC2",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"UMask": "0x40",
"BriefDescription": "Number of times an HLE execution aborted due to incompatible memory type",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED_MISC4", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times HLE caused a fault.", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC3",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0xc8", "BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"UMask": "0x80",
"BriefDescription": "Number of times an HLE execution aborted due to none of the previous 4 categories (e.g. interrupts)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "HLE_RETIRED.ABORTED_MISC5", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times HLE aborted and was not due to the abort conditions in subevents 3-6.", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC4",
"PublicDescription": "Number of times a RTM caused a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"UMask": "0x1",
"BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.START", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.ABORTED_MISC5",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x80"
}, },
{ {
"EventCode": "0xc9",
"UMask": "0x2",
"BriefDescription": "Number of times RTM commit succeeded", "BriefDescription": "Number of times RTM commit succeeded",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3",
"EventCode": "0xc9",
"EventName": "RTM_RETIRED.COMMIT", "EventName": "RTM_RETIRED.COMMIT",
"PublicDescription": "Number of times RTM commit succeeded.", "PublicDescription": "Number of times RTM commit succeeded.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x2"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Number of times we entered an RTM region; does not count nested transactions",
"UMask": "0x4",
"BriefDescription": "Number of times RTM abort was triggered (PEBS)",
"PEBS": "1",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED", "CounterHTOff": "0,1,2,3",
"PublicDescription": "Number of times RTM abort was triggered (PEBS).", "EventCode": "0xc9",
"EventName": "RTM_RETIRED.START",
"PublicDescription": "Number of times we entered an RTM region\n does not count nested transactions.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Counts the number of times a class of instructions that may cause a transactional abort was executed. Since this is the count of execution, it may not always cause a transactional abort.",
"UMask": "0x8",
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g. read/write capacity and conflicts)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MISC1", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times an RTM abort was attributed to a Memory condition (See TSX_Memory event for additional details).", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x1"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Counts the number of times a class of instructions (e.g., vzeroupper) that may cause a transactional abort was executed inside a transactional region",
"UMask": "0x10",
"BriefDescription": "Number of times an RTM execution aborted due to various memory events (e.g., read/write capacity and conflicts).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MISC2", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times the TSX watchdog signaled an RTM abort.", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC2",
"PublicDescription": "Unfriendly TSX abort triggered by a vzeroupper instruction.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x2"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Counts the number of times an instruction execution caused the transactional nest count supported to be exceeded",
"UMask": "0x20",
"BriefDescription": "Number of times an RTM execution aborted due to HLE-unfriendly instructions",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MISC3", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a disallowed operation caused an RTM abort.", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC3",
"PublicDescription": "Unfriendly TSX abort triggered by a nest count that is too deep.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x4"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Counts the number of times a XBEGIN instruction was executed inside an HLE transactional region.",
"UMask": "0x40",
"BriefDescription": "Number of times an RTM execution aborted due to incompatible memory type",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MISC4", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times a RTM caused a fault.", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC4",
"PublicDescription": "RTM region detected inside HLE.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x8"
}, },
{ {
"EventCode": "0xc9", "BriefDescription": "Counts the number of times an HLE XACQUIRE instruction was executed inside an RTM transactional region.",
"UMask": "0x80",
"BriefDescription": "Number of times an RTM execution aborted due to none of the previous 4 categories (e.g. interrupt)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "RTM_RETIRED.ABORTED_MISC5", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "Number of times RTM aborted and was not due to the abort conditions in subevents 3-6.", "EventCode": "0x5d",
"EventName": "TX_EXEC.MISC5",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x10"
},
{
"EventCode": "0xCD",
"UMask": "0x1",
"BriefDescription": "Loads with latency value being above 4",
"PEBS": "2",
"MSRValue": "0x4",
"Counter": "3",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_4",
"MSRIndex": "0x3F6",
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above four.",
"TakenAlone": "1",
"SampleAfterValue": "100003",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 8", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x8", "EventName": "TX_MEM.ABORT_CAPACITY_WRITE",
"Counter": "3", "PublicDescription": "Number of times a TSX Abort was triggered due to an evicted line caused by a transaction overflow.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_8", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x2"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above eight.",
"TakenAlone": "1",
"SampleAfterValue": "50021",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX line had a cache conflict",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 16", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x10", "EventName": "TX_MEM.ABORT_CONFLICT",
"Counter": "3", "PublicDescription": "Number of times a TSX line had a cache conflict.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_16", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x1"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 16.",
"TakenAlone": "1",
"SampleAfterValue": "20011",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 32", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x20", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_MISMATCH",
"Counter": "3", "PublicDescription": "Number of times a TSX Abort was triggered due to release/commit but data and address mismatch.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_32", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x10"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 32.",
"TakenAlone": "1",
"SampleAfterValue": "100007",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 64", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x40", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_NOT_EMPTY",
"Counter": "3", "PublicDescription": "Number of times a TSX Abort was triggered due to commit but Lock Buffer not empty.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_64", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x8"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 64.",
"TakenAlone": "1",
"SampleAfterValue": "2003",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 128", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x80", "EventName": "TX_MEM.ABORT_HLE_ELISION_BUFFER_UNSUPPORTED_ALIGNMENT",
"Counter": "3", "PublicDescription": "Number of times a TSX Abort was triggered due to attempting an unsupported alignment from Lock Buffer.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_128", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x20"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 128.",
"TakenAlone": "1",
"SampleAfterValue": "1009",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 256", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x100", "EventName": "TX_MEM.ABORT_HLE_STORE_TO_ELIDED_LOCK",
"Counter": "3", "PublicDescription": "Number of times a TSX Abort was triggered due to a non-release/commit store to lock.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_256", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x4"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 256.",
"TakenAlone": "1",
"SampleAfterValue": "503",
"CounterHTOff": "3"
}, },
{ {
"EventCode": "0xCD", "BriefDescription": "Number of times we could not allocate Lock Buffer",
"UMask": "0x1", "Counter": "0,1,2,3",
"BriefDescription": "Loads with latency value being above 512", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PEBS": "2", "EventCode": "0x54",
"MSRValue": "0x200", "EventName": "TX_MEM.HLE_ELISION_BUFFER_FULL",
"Counter": "3", "PublicDescription": "Number of times we could not allocate Lock Buffer.",
"EventName": "MEM_TRANS_RETIRED.LOAD_LATENCY_GT_512", "SampleAfterValue": "2000003",
"MSRIndex": "0x3F6", "UMask": "0x40"
"Errata": "BDM100, BDM35",
"PublicDescription": "This event counts loads with latency value being above 512.",
"TakenAlone": "1",
"SampleAfterValue": "101",
"CounterHTOff": "3"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwellde/other.json
View file @ 34cb72ef
[ [
{ {
"EventCode": "0x5C",
"UMask": "0x1",
"BriefDescription": "Unhalted core cycles when the thread is in ring 0", "BriefDescription": "Unhalted core cycles when the thread is in ring 0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0", "EventName": "CPL_CYCLES.RING0",
"PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.", "PublicDescription": "This event counts the unhalted core cycles during which the thread is in the ring 0 privileged mode.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EdgeDetect": "1",
"EventCode": "0x5C",
"UMask": "0x1",
"BriefDescription": "Number of intervals between processor halts while thread is in ring 0", "BriefDescription": "Number of intervals between processor halts while thread is in ring 0",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "CPL_CYCLES.RING0_TRANS", "CounterHTOff": "0,1,2,3,4,5,6,7",
"CounterMask": "1", "CounterMask": "1",
"EdgeDetect": "1",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING0_TRANS",
"PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.", "PublicDescription": "This event counts when there is a transition from ring 1,2 or 3 to ring0.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x5C",
"UMask": "0x2",
"BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3", "BriefDescription": "Unhalted core cycles when thread is in rings 1, 2, or 3",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x5C",
"EventName": "CPL_CYCLES.RING123", "EventName": "CPL_CYCLES.RING123",
"PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.", "PublicDescription": "This event counts unhalted core cycles during which the thread is in rings 1, 2, or 3.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0x63",
"UMask": "0x1",
"BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock", "BriefDescription": "Cycles when L1 and L2 are locked due to UC or split lock",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x63",
"EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION", "EventName": "LOCK_CYCLES.SPLIT_LOCK_UC_LOCK_DURATION",
"PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.", "PublicDescription": "This event counts cycles in which the L1 and L2 are locked due to a UC lock or split lock. A lock is asserted in case of locked memory access, due to noncacheable memory, locked operation that spans two cache lines, or a page walk from the noncacheable page table. L1D and L2 locks have a very high performance penalty and it is highly recommended to avoid such access.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
} }
] ]
\ No newline at end of file
tools/perf/pmu-events/arch/x86/broadwellde/pipeline.json
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This source diff could not be displayed because it is too large. You can view the blob instead.
tools/perf/pmu-events/arch/x86/broadwellde/virtual-memory.json
View file @ 34cb72ef
[ [
{ {
"EventCode": "0x08",
"UMask": "0x1",
"BriefDescription": "Load misses in all DTLB levels that cause page walks", "BriefDescription": "Load misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "PublicDescription": "This event counts load misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"UMask": "0x2",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x08",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "EventName": "DTLB_LOAD_MISSES.STLB_HIT",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x60"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"UMask": "0x4",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x08",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"UMask": "0x8",
"BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x08",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x08",
"UMask": "0xe",
"BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes of any page size.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xe"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Load miss in all TLB levels causes a page walk that completes. (1G)",
"UMask": "0x10",
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (2M/4M).",
"UMask": "0x20",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_4K", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Demand load Miss in all translation lookaside buffer (TLB) levels causes a page walk that completes (4K).",
"UMask": "0x40",
"BriefDescription": "Load misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT_2M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "This event counts load misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0x08", "BriefDescription": "Cycles when PMH is busy with page walks",
"UMask": "0x60",
"BriefDescription": "Load operations that miss the first DTLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_LOAD_MISSES.STLB_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x08",
"EventName": "DTLB_LOAD_MISSES.WALK_DURATION",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0x49",
"UMask": "0x1",
"BriefDescription": "Store misses in all DTLB levels that cause page walks", "BriefDescription": "Store misses in all DTLB levels that cause page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"UMask": "0x2",
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x49",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "EventName": "DTLB_STORE_MISSES.STLB_HIT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x60"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"UMask": "0x4",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x49",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "EventName": "DTLB_STORE_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"UMask": "0x8",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x49",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "EventName": "DTLB_STORE_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x49",
"UMask": "0xe",
"BriefDescription": "Store misses in all DTLB levels that cause completed page walks.", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xe"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (1G)",
"UMask": "0x10",
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.", "EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_1G",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store misses in all DTLB levels that cause completed page walks (2M/4M)",
"UMask": "0x20",
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (4K).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_4K", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (4K)",
"UMask": "0x40",
"BriefDescription": "Store misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT_2M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0x49", "BriefDescription": "Cycles when PMH is busy with page walks",
"UMask": "0x60",
"BriefDescription": "Store operations that miss the first TLB level but hit the second and do not cause page walks.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "DTLB_STORE_MISSES.STLB_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x49",
"EventName": "DTLB_STORE_MISSES.WALK_DURATION",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
}, },
{ {
"EventCode": "0x4F",
"UMask": "0x10",
"BriefDescription": "Cycle count for an Extended Page table walk.", "BriefDescription": "Cycle count for an Extended Page table walk.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0x4F",
"EventName": "EPT.WALK_CYCLES", "EventName": "EPT.WALK_CYCLES",
"PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.", "PublicDescription": "This event counts cycles for an extended page table walk. The Extended Page directory cache differs from standard TLB caches by the operating system that use it. Virtual machine operating systems use the extended page directory cache, while guest operating systems use the standard TLB caches.",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x10"
},
{
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xAE",
"EventName": "ITLB.ITLB_FLUSH",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).",
"SampleAfterValue": "100007",
"UMask": "0x1"
}, },
{ {
"EventCode": "0x85",
"UMask": "0x1",
"BriefDescription": "Misses at all ITLB levels that cause page walks", "BriefDescription": "Misses at all ITLB levels that cause page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.MISS_CAUSES_A_WALK",
"PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).", "PublicDescription": "This event counts store misses in all DTLB levels that cause page walks of any page size (4K/2M/4M/1G).",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"UMask": "0x2",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x85",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.", "EventName": "ITLB_MISSES.STLB_HIT",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x60"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"UMask": "0x4",
"BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x85",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.", "EventName": "ITLB_MISSES.STLB_HIT_2M",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x40"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).",
"UMask": "0x8",
"BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED_1G", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "EventCode": "0x85",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.", "EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
}, },
{ {
"EventCode": "0x85",
"UMask": "0xe",
"BriefDescription": "Misses in all ITLB levels that cause completed page walks.", "BriefDescription": "Misses in all ITLB levels that cause completed page walks.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_COMPLETED", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0xe"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Store miss in all TLB levels causes a page walk that completes. (1G)",
"UMask": "0x10",
"BriefDescription": "Cycles when PMH is busy with page walks",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.WALK_DURATION", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69", "Errata": "BDM69",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7"
},
{
"EventCode": "0x85", "EventCode": "0x85",
"UMask": "0x20", "EventName": "ITLB_MISSES.WALK_COMPLETED_1G",
"BriefDescription": "Core misses that miss the DTLB and hit the STLB (4K).", "PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (1G page size). The page walk can end with or without a fault.",
"Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT_4K",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x8"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (2M/4M)",
"UMask": "0x40",
"BriefDescription": "Code misses that miss the DTLB and hit the STLB (2M).",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT_2M", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_2M_4M",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (2M and 4M page sizes). The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x4"
}, },
{ {
"EventCode": "0x85", "BriefDescription": "Code miss in all TLB levels causes a page walk that completes. (4K)",
"UMask": "0x60",
"BriefDescription": "Operations that miss the first ITLB level but hit the second and do not cause any page walks.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB_MISSES.STLB_HIT", "CounterHTOff": "0,1,2,3,4,5,6,7",
"Errata": "BDM69",
"EventCode": "0x85",
"EventName": "ITLB_MISSES.WALK_COMPLETED_4K",
"PublicDescription": "This event counts store misses in all DTLB levels that cause a completed page walk (4K page size). The page walk can end with or without a fault.",
"SampleAfterValue": "100003", "SampleAfterValue": "100003",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x2"
}, },
{ {
"EventCode": "0xAE", "BriefDescription": "Cycles when PMH is busy with page walks",
"UMask": "0x1",
"BriefDescription": "Flushing of the Instruction TLB (ITLB) pages, includes 4k/2M/4M pages.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "ITLB.ITLB_FLUSH", "CounterHTOff": "0,1,2,3,4,5,6,7",
"PublicDescription": "This event counts the number of flushes of the big or small ITLB pages. Counting include both TLB Flush (covering all sets) and TLB Set Clear (set-specific).", "Errata": "BDM69",
"SampleAfterValue": "100007", "EventCode": "0x85",
"CounterHTOff": "0,1,2,3,4,5,6,7" "EventName": "ITLB_MISSES.WALK_DURATION",
"PublicDescription": "This event counts the number of cycles while PMH is busy with the page walk.",
"SampleAfterValue": "100003",
"UMask": "0x10"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x11",
"BriefDescription": "Number of DTLB page walker hits in the L1+FB.", "BriefDescription": "Number of DTLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x11"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x12",
"BriefDescription": "Number of DTLB page walker hits in the L2.", "BriefDescription": "Number of DTLB page walker hits in the L2.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x12"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x14",
"BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of DTLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_L3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x14"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x18",
"BriefDescription": "Number of DTLB page walker hits in Memory.", "BriefDescription": "Number of DTLB page walker hits in Memory.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.DTLB_MEMORY",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x18"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x21",
"BriefDescription": "Number of ITLB page walker hits in the L1+FB.", "BriefDescription": "Number of ITLB page walker hits in the L1+FB.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L1",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x21"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x22",
"BriefDescription": "Number of ITLB page walker hits in the L2.", "BriefDescription": "Number of ITLB page walker hits in the L2.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L2",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x22"
}, },
{ {
"EventCode": "0xBC",
"UMask": "0x24",
"BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.", "BriefDescription": "Number of ITLB page walker hits in the L3 + XSNP.",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3", "CounterHTOff": "0,1,2,3",
"Errata": "BDM69, BDM98", "Errata": "BDM69, BDM98",
"EventCode": "0xBC",
"EventName": "PAGE_WALKER_LOADS.ITLB_L3",
"SampleAfterValue": "2000003", "SampleAfterValue": "2000003",
"CounterHTOff": "0,1,2,3" "UMask": "0x24"
}, },
{ {
"EventCode": "0xBD",
"UMask": "0x1",
"BriefDescription": "DTLB flush attempts of the thread-specific entries", "BriefDescription": "DTLB flush attempts of the thread-specific entries",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.DTLB_THREAD", "EventName": "TLB_FLUSH.DTLB_THREAD",
"PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.", "PublicDescription": "This event counts the number of DTLB flush attempts of the thread-specific entries.",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x1"
}, },
{ {
"EventCode": "0xBD",
"UMask": "0x20",
"BriefDescription": "STLB flush attempts", "BriefDescription": "STLB flush attempts",
"Counter": "0,1,2,3", "Counter": "0,1,2,3",
"CounterHTOff": "0,1,2,3,4,5,6,7",
"EventCode": "0xBD",
"EventName": "TLB_FLUSH.STLB_ANY", "EventName": "TLB_FLUSH.STLB_ANY",
"PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).", "PublicDescription": "This event counts the number of any STLB flush attempts (such as entire, VPID, PCID, InvPage, CR3 write, and so on).",
"SampleAfterValue": "100007", "SampleAfterValue": "100007",
"CounterHTOff": "0,1,2,3,4,5,6,7" "UMask": "0x20"
} }
] ]
\ No newline at end of file
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