Commit 3510a694 authored by Mark Brown's avatar Mark Brown

Merge remote-tracking branches 'asoc/topic/sigmadsp', 'asoc/topic/sirf',...

Merge remote-tracking branches 'asoc/topic/sigmadsp', 'asoc/topic/sirf', 'asoc/topic/spdif', 'asoc/topic/tas2552' and 'asoc/topic/tas5086' into asoc-next
* SiRF SoC USP module
Required properties:
- compatible: "sirf,prima2-usp-pcm"
- reg: Base address and size entries:
- dmas: List of DMA controller phandle and DMA request line ordered pairs.
- dma-names: Identifier string for each DMA request line in the dmas property.
These strings correspond 1:1 with the ordered pairs in dmas.
One of the DMA channels will be responsible for transmission (should be
named "tx") and one for reception (should be named "rx").
- clocks: USP controller clock source
- pinctrl-names: Must contain a "default" entry.
- pinctrl-NNN: One property must exist for each entry in pinctrl-names.
Example:
usp0: usp@b0080000 {
compatible = "sirf,prima2-usp-pcm";
reg = <0xb0080000 0x10000>;
clocks = <&clks 28>;
dmas = <&dmac1 1>, <&dmac1 2>;
dma-names = "rx", "tx";
pinctrl-names = "default";
pinctrl-0 = <&usp0_only_utfs_pins_a>;
};
Texas Instruments - tas2552 Codec module
The tas2552 serial control bus communicates through I2C protocols
Required properties:
- compatible - One of:
"ti,tas2552" - TAS2552
- reg - I2C slave address
- supply-*: Required supply regulators are:
"vbat" battery voltage
"iovdd" I/O Voltage
"avdd" Analog DAC Voltage
Optional properties:
- enable-gpio - gpio pin to enable/disable the device
Example:
tas2552: tas2552@41 {
compatible = "ti,tas2552";
reg = <0x41>;
enable-gpio = <&gpio4 2 GPIO_ACTIVE_HIGH>;
};
For more product information please see the link below:
http://www.ti.com/product/TAS2552
......@@ -31,6 +31,9 @@ Optional properties:
Most systems should not set any of these properties.
- avdd-supply: Power supply for AVDD, providing 3.3V
- dvdd-supply: Power supply for DVDD, providing 3.3V
Examples:
i2c_bus {
......@@ -39,5 +42,7 @@ Examples:
reg = <0x1b>;
reset-gpio = <&gpio 23 0>;
ti,charge-period = <156000>;
avdd-supply = <&vdd_3v3_reg>;
dvdd-supply = <&vdd_3v3_reg>;
};
};
/*
* TAS2552 driver platform header
*
* Copyright (C) 2014 Texas Instruments Inc.
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#ifndef TAS2552_PLAT_H
#define TAS2552_PLAT_H
struct tas2552_platform_data {
int enable_gpio;
};
#endif
......@@ -94,6 +94,7 @@ config SND_SOC_ALL_CODECS
select SND_SOC_STA350 if I2C
select SND_SOC_STA529 if I2C
select SND_SOC_STAC9766 if SND_SOC_AC97_BUS
select SND_SOC_TAS2552 if I2C
select SND_SOC_TAS5086 if I2C
select SND_SOC_TLV320AIC23_I2C if I2C
select SND_SOC_TLV320AIC23_SPI if SPI_MASTER
......@@ -539,6 +540,10 @@ config SND_SOC_STA529
config SND_SOC_STAC9766
tristate
config SND_SOC_TAS2552
tristate "Texas Instruments TAS2552 Mono Audio amplifier"
depends on I2C
config SND_SOC_TAS5086
tristate "Texas Instruments TAS5086 speaker amplifier"
depends on I2C
......
......@@ -165,6 +165,7 @@ snd-soc-wm-hubs-objs := wm_hubs.o
# Amp
snd-soc-max9877-objs := max9877.o
snd-soc-tpa6130a2-objs := tpa6130a2.o
snd-soc-tas2552-objs := tas2552.o
obj-$(CONFIG_SND_SOC_88PM860X) += snd-soc-88pm860x.o
obj-$(CONFIG_SND_SOC_AB8500_CODEC) += snd-soc-ab8500-codec.o
......@@ -261,6 +262,7 @@ obj-$(CONFIG_SND_SOC_STA32X) += snd-soc-sta32x.o
obj-$(CONFIG_SND_SOC_STA350) += snd-soc-sta350.o
obj-$(CONFIG_SND_SOC_STA529) += snd-soc-sta529.o
obj-$(CONFIG_SND_SOC_STAC9766) += snd-soc-stac9766.o
obj-$(CONFIG_SND_SOC_TAS2552) += snd-soc-tas2552.o
obj-$(CONFIG_SND_SOC_TAS5086) += snd-soc-tas5086.o
obj-$(CONFIG_SND_SOC_TLV320AIC23) += snd-soc-tlv320aic23.o
obj-$(CONFIG_SND_SOC_TLV320AIC23_I2C) += snd-soc-tlv320aic23-i2c.o
......
......@@ -471,8 +471,8 @@ static int sirf_audio_codec_driver_probe(struct platform_device *pdev)
mem_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
base = devm_ioremap_resource(&pdev->dev, mem_res);
if (base == NULL)
return -ENOMEM;
if (IS_ERR(base))
return PTR_ERR(base);
sirf_audio_codec->regmap = devm_regmap_init_mmio(&pdev->dev, base,
&sirf_audio_codec_regmap_config);
......
......@@ -24,7 +24,7 @@
#define DRV_NAME "spdif-dit"
#define STUB_RATES SNDRV_PCM_RATE_8000_96000
#define STUB_RATES SNDRV_PCM_RATE_8000_192000
#define STUB_FORMATS (SNDRV_PCM_FMTBIT_S16_LE | \
SNDRV_PCM_FMTBIT_S20_3LE | \
SNDRV_PCM_FMTBIT_S24_LE)
......
This diff is collapsed.
/*
* tas2552.h - ALSA SoC Texas Instruments TAS2552 Mono Audio Amplifier
*
* Copyright (C) 2014 Texas Instruments Incorporated - http://www.ti.com
*
* Author: Dan Murphy <dmurphy@ti.com>
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License
* version 2 as published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful, but
* WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
* General Public License for more details.
*/
#ifndef __TAS2552_H__
#define __TAS2552_H__
/* Register Address Map */
#define TAS2552_DEVICE_STATUS 0x00
#define TAS2552_CFG_1 0x01
#define TAS2552_CFG_2 0x02
#define TAS2552_CFG_3 0x03
#define TAS2552_DOUT 0x04
#define TAS2552_SER_CTRL_1 0x05
#define TAS2552_SER_CTRL_2 0x06
#define TAS2552_OUTPUT_DATA 0x07
#define TAS2552_PLL_CTRL_1 0x08
#define TAS2552_PLL_CTRL_2 0x09
#define TAS2552_PLL_CTRL_3 0x0a
#define TAS2552_BTIP 0x0b
#define TAS2552_BTS_CTRL 0x0c
#define TAS2552_RESERVED_0D 0x0d
#define TAS2552_LIMIT_RATE_HYS 0x0e
#define TAS2552_LIMIT_RELEASE 0x0f
#define TAS2552_LIMIT_INT_COUNT 0x10
#define TAS2552_PDM_CFG 0x11
#define TAS2552_PGA_GAIN 0x12
#define TAS2552_EDGE_RATE_CTRL 0x13
#define TAS2552_BOOST_PT_CTRL 0x14
#define TAS2552_VER_NUM 0x16
#define TAS2552_VBAT_DATA 0x19
#define TAS2552_MAX_REG 0x20
/* CFG1 Register Masks */
#define TAS2552_MUTE_MASK (1 << 2)
#define TAS2552_SWS_MASK (1 << 1)
#define TAS2552_WCLK_MASK 0x07
#define TAS2552_CLASSD_EN_MASK (1 << 7)
/* CFG2 Register Masks */
#define TAS2552_CLASSD_EN (1 << 7)
#define TAS2552_BOOST_EN (1 << 6)
#define TAS2552_APT_EN (1 << 5)
#define TAS2552_PLL_ENABLE (1 << 3)
#define TAS2552_LIM_EN (1 << 2)
#define TAS2552_IVSENSE_EN (1 << 1)
/* CFG3 Register Masks */
#define TAS2552_WORD_CLK_MASK (1 << 7)
#define TAS2552_BIT_CLK_MASK (1 << 6)
#define TAS2552_DATA_FORMAT_MASK (0x11 << 2)
#define TAS2552_DAIFMT_I2S_MASK 0xf3
#define TAS2552_DAIFMT_DSP (1 << 3)
#define TAS2552_DAIFMT_RIGHT_J (1 << 4)
#define TAS2552_DAIFMT_LEFT_J (0x11 << 3)
#define TAS2552_PLL_SRC_MCLK 0x00
#define TAS2552_PLL_SRC_BCLK (1 << 3)
#define TAS2552_PLL_SRC_IVCLKIN (1 << 4)
#define TAS2552_PLL_SRC_1_8_FIXED (0x11 << 3)
#define TAS2552_DIN_SRC_SEL_MUTED 0x00
#define TAS2552_DIN_SRC_SEL_LEFT (1 << 4)
#define TAS2552_DIN_SRC_SEL_RIGHT (1 << 5)
#define TAS2552_DIN_SRC_SEL_AVG_L_R (0x11 << 4)
#define TAS2552_PDM_IN_SEL (1 << 5)
#define TAS2552_I2S_OUT_SEL (1 << 6)
#define TAS2552_ANALOG_IN_SEL (1 << 7)
/* CFG3 WCLK Dividers */
#define TAS2552_8KHZ 0x00
#define TAS2552_11_12KHZ (1 << 1)
#define TAS2552_16KHZ (1 << 2)
#define TAS2552_22_24KHZ (1 << 3)
#define TAS2552_32KHZ (1 << 4)
#define TAS2552_44_48KHZ (1 << 5)
#define TAS2552_88_96KHZ (1 << 6)
#define TAS2552_176_192KHZ (1 << 7)
/* OUTPUT_DATA register */
#define TAS2552_PDM_DATA_I 0x00
#define TAS2552_PDM_DATA_V (1 << 6)
#define TAS2552_PDM_DATA_I_V (1 << 7)
#define TAS2552_PDM_DATA_V_I (0x11 << 6)
/* PDM CFG Register */
#define TAS2552_PDM_DATA_ES_RISE 0x4
#define TAS2552_PDM_PLL_CLK_SEL 0x00
#define TAS2552_PDM_IV_CLK_SEL (1 << 1)
#define TAS2552_PDM_BCLK_SEL (1 << 2)
#define TAS2552_PDM_MCLK_SEL (1 << 3)
/* Boost pass-through register */
#define TAS2552_APT_DELAY_50 0x00
#define TAS2552_APT_DELAY_75 (1 << 1)
#define TAS2552_APT_DELAY_125 (1 << 2)
#define TAS2552_APT_DELAY_200 (1 << 3)
#define TAS2552_APT_THRESH_2_5 0x00
#define TAS2552_APT_THRESH_1_7 (1 << 3)
#define TAS2552_APT_THRESH_1_4_1_1 (1 << 4)
#define TAS2552_APT_THRESH_2_1_7 (0x11 << 2)
/* PLL Control Register */
#define TAS2552_245MHZ_CLK 24576000
#define TAS2552_225MHZ_CLK 22579200
#define TAS2552_PLL_J_MASK 0x7f
#define TAS2552_PLL_D_UPPER_MASK 0x3f
#define TAS2552_PLL_D_LOWER_MASK 0xff
#define TAS2552_PLL_BYPASS_MASK 0x80
#define TAS2552_PLL_BYPASS 0x80
#endif
......@@ -36,6 +36,7 @@
#include <linux/gpio.h>
#include <linux/i2c.h>
#include <linux/regmap.h>
#include <linux/regulator/consumer.h>
#include <linux/spi/spi.h>
#include <linux/of.h>
#include <linux/of_device.h>
......@@ -240,6 +241,10 @@ static int tas5086_reg_read(void *context, unsigned int reg,
return 0;
}
static const char * const supply_names[] = {
"dvdd", "avdd"
};
struct tas5086_private {
struct regmap *regmap;
unsigned int mclk, sclk;
......@@ -251,6 +256,7 @@ struct tas5086_private {
int rate;
/* GPIO driving Reset pin, if any */
int gpio_nreset;
struct regulator_bulk_data supplies[ARRAY_SIZE(supply_names)];
};
static int tas5086_deemph[] = { 0, 32000, 44100, 48000 };
......@@ -773,6 +779,8 @@ static int tas5086_soc_suspend(struct snd_soc_codec *codec)
if (ret < 0)
return ret;
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return 0;
}
......@@ -781,6 +789,10 @@ static int tas5086_soc_resume(struct snd_soc_codec *codec)
struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
int ret;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0)
return ret;
tas5086_reset(priv);
regcache_mark_dirty(priv->regmap);
......@@ -812,6 +824,12 @@ static int tas5086_probe(struct snd_soc_codec *codec)
struct tas5086_private *priv = snd_soc_codec_get_drvdata(codec);
int i, ret;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0) {
dev_err(codec->dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
priv->pwm_start_mid_z = 0;
priv->charge_period = 1300000; /* hardware default is 1300 ms */
......@@ -832,16 +850,22 @@ static int tas5086_probe(struct snd_soc_codec *codec)
}
}
tas5086_reset(priv);
ret = tas5086_init(codec->dev, priv);
if (ret < 0)
return ret;
goto exit_disable_regulators;
/* set master volume to 0 dB */
ret = regmap_write(priv->regmap, TAS5086_MASTER_VOL, 0x30);
if (ret < 0)
return ret;
goto exit_disable_regulators;
return 0;
exit_disable_regulators:
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return ret;
}
static int tas5086_remove(struct snd_soc_codec *codec)
......@@ -852,6 +876,8 @@ static int tas5086_remove(struct snd_soc_codec *codec)
/* Set codec to the reset state */
gpio_set_value(priv->gpio_nreset, 0);
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
return 0;
};
......@@ -900,6 +926,16 @@ static int tas5086_i2c_probe(struct i2c_client *i2c,
if (!priv)
return -ENOMEM;
for (i = 0; i < ARRAY_SIZE(supply_names); i++)
priv->supplies[i].supply = supply_names[i];
ret = devm_regulator_bulk_get(dev, ARRAY_SIZE(priv->supplies),
priv->supplies);
if (ret < 0) {
dev_err(dev, "Failed to get regulators: %d\n", ret);
return ret;
}
priv->regmap = devm_regmap_init(dev, NULL, i2c, &tas5086_regmap);
if (IS_ERR(priv->regmap)) {
ret = PTR_ERR(priv->regmap);
......@@ -919,21 +955,34 @@ static int tas5086_i2c_probe(struct i2c_client *i2c,
gpio_nreset = -EINVAL;
priv->gpio_nreset = gpio_nreset;
ret = regulator_bulk_enable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret < 0) {
dev_err(dev, "Failed to enable regulators: %d\n", ret);
return ret;
}
tas5086_reset(priv);
/* The TAS5086 always returns 0x03 in its TAS5086_DEV_ID register */
ret = regmap_read(priv->regmap, TAS5086_DEV_ID, &i);
if (ret < 0)
return ret;
if (i != 0x3) {
if (ret == 0 && i != 0x3) {
dev_err(dev,
"Failed to identify TAS5086 codec (got %02x)\n", i);
return -ENODEV;
ret = -ENODEV;
}
return snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086,
/*
* The chip has been identified, so we can turn off the power
* again until the dai link is set up.
*/
regulator_bulk_disable(ARRAY_SIZE(priv->supplies), priv->supplies);
if (ret == 0)
ret = snd_soc_register_codec(&i2c->dev, &soc_codec_dev_tas5086,
&tas5086_dai, 1);
return ret;
}
static int tas5086_i2c_remove(struct i2c_client *i2c)
......
......@@ -12,3 +12,9 @@ config SND_SOC_SIRF_AUDIO
config SND_SOC_SIRF_AUDIO_PORT
select REGMAP_MMIO
tristate
config SND_SOC_SIRF_USP
tristate "SoC Audio (I2S protocol) for SiRF SoC USP interface"
depends on SND_SOC_SIRF
select REGMAP_MMIO
tristate
snd-soc-sirf-audio-objs := sirf-audio.o
snd-soc-sirf-audio-port-objs := sirf-audio-port.o
snd-soc-sirf-usp-objs := sirf-usp.o
obj-$(CONFIG_SND_SOC_SIRF_AUDIO) += snd-soc-sirf-audio.o
obj-$(CONFIG_SND_SOC_SIRF_AUDIO_PORT) += snd-soc-sirf-audio-port.o
obj-$(CONFIG_SND_SOC_SIRF_USP) += snd-soc-sirf-usp.o
This diff is collapsed.
/*
* arch/arm/mach-prima2/include/mach/sirfsoc_usp.h
*
* Copyright (c) 2011 Cambridge Silicon Radio Limited, a CSR plc group company.
*
* Licensed under GPLv2 or later.
*/
#ifndef _SIRF_USP_H
#define _SIRF_USP_H
/* USP Registers */
#define USP_MODE1 0x00
#define USP_MODE2 0x04
#define USP_TX_FRAME_CTRL 0x08
#define USP_RX_FRAME_CTRL 0x0C
#define USP_TX_RX_ENABLE 0x10
#define USP_INT_ENABLE 0x14
#define USP_INT_STATUS 0x18
#define USP_PIN_IO_DATA 0x1C
#define USP_RISC_DSP_MODE 0x20
#define USP_AYSNC_PARAM_REG 0x24
#define USP_IRDA_X_MODE_DIV 0x28
#define USP_SM_CFG 0x2C
#define USP_TX_DMA_IO_CTRL 0x100
#define USP_TX_DMA_IO_LEN 0x104
#define USP_TX_FIFO_CTRL 0x108
#define USP_TX_FIFO_LEVEL_CHK 0x10C
#define USP_TX_FIFO_OP 0x110
#define USP_TX_FIFO_STATUS 0x114
#define USP_TX_FIFO_DATA 0x118
#define USP_RX_DMA_IO_CTRL 0x120
#define USP_RX_DMA_IO_LEN 0x124
#define USP_RX_FIFO_CTRL 0x128
#define USP_RX_FIFO_LEVEL_CHK 0x12C
#define USP_RX_FIFO_OP 0x130
#define USP_RX_FIFO_STATUS 0x134
#define USP_RX_FIFO_DATA 0x138
/* USP MODE register-1 */
#define USP_SYNC_MODE 0x00000001
#define USP_CLOCK_MODE_SLAVE 0x00000002
#define USP_LOOP_BACK_EN 0x00000004
#define USP_HPSIR_EN 0x00000008
#define USP_ENDIAN_CTRL_LSBF 0x00000010
#define USP_EN 0x00000020
#define USP_RXD_ACT_EDGE_FALLING 0x00000040
#define USP_TXD_ACT_EDGE_FALLING 0x00000080
#define USP_RFS_ACT_LEVEL_LOGIC1 0x00000100
#define USP_TFS_ACT_LEVEL_LOGIC1 0x00000200
#define USP_SCLK_IDLE_MODE_TOGGLE 0x00000400
#define USP_SCLK_IDLE_LEVEL_LOGIC1 0x00000800
#define USP_SCLK_PIN_MODE_IO 0x00001000
#define USP_RFS_PIN_MODE_IO 0x00002000
#define USP_TFS_PIN_MODE_IO 0x00004000
#define USP_RXD_PIN_MODE_IO 0x00008000
#define USP_TXD_PIN_MODE_IO 0x00010000
#define USP_SCLK_IO_MODE_INPUT 0x00020000
#define USP_RFS_IO_MODE_INPUT 0x00040000
#define USP_TFS_IO_MODE_INPUT 0x00080000
#define USP_RXD_IO_MODE_INPUT 0x00100000
#define USP_TXD_IO_MODE_INPUT 0x00200000
#define USP_IRDA_WIDTH_DIV_MASK 0x3FC00000
#define USP_IRDA_WIDTH_DIV_OFFSET 0
#define USP_IRDA_IDLE_LEVEL_HIGH 0x40000000
#define USP_TX_UFLOW_REPEAT_ZERO 0x80000000
#define USP_TX_ENDIAN_MODE 0x00000020
#define USP_RX_ENDIAN_MODE 0x00000020
/* USP Mode Register-2 */
#define USP_RXD_DELAY_LEN_MASK 0x000000FF
#define USP_RXD_DELAY_LEN_OFFSET 0
#define USP_TXD_DELAY_LEN_MASK 0x0000FF00
#define USP_TXD_DELAY_LEN_OFFSET 8
#define USP_ENA_CTRL_MODE 0x00010000
#define USP_FRAME_CTRL_MODE 0x00020000
#define USP_TFS_SOURCE_MODE 0x00040000
#define USP_TFS_MS_MODE 0x00080000
#define USP_CLK_DIVISOR_MASK 0x7FE00000
#define USP_CLK_DIVISOR_OFFSET 21
#define USP_TFS_CLK_SLAVE_MODE (1<<20)
#define USP_RFS_CLK_SLAVE_MODE (1<<19)
#define USP_IRDA_DATA_WIDTH 0x80000000
/* USP Transmit Frame Control Register */
#define USP_TXC_DATA_LEN_MASK 0x000000FF
#define USP_TXC_DATA_LEN_OFFSET 0
#define USP_TXC_SYNC_LEN_MASK 0x0000FF00
#define USP_TXC_SYNC_LEN_OFFSET 8
#define USP_TXC_FRAME_LEN_MASK 0x00FF0000
#define USP_TXC_FRAME_LEN_OFFSET 16
#define USP_TXC_SHIFTER_LEN_MASK 0x1F000000
#define USP_TXC_SHIFTER_LEN_OFFSET 24
#define USP_TXC_SLAVE_CLK_SAMPLE 0x20000000
#define USP_TXC_CLK_DIVISOR_MASK 0xC0000000
#define USP_TXC_CLK_DIVISOR_OFFSET 30
/* USP Receive Frame Control Register */
#define USP_RXC_DATA_LEN_MASK 0x000000FF
#define USP_RXC_DATA_LEN_OFFSET 0
#define USP_RXC_FRAME_LEN_MASK 0x0000FF00
#define USP_RXC_FRAME_LEN_OFFSET 8
#define USP_RXC_SHIFTER_LEN_MASK 0x001F0000
#define USP_RXC_SHIFTER_LEN_OFFSET 16
#define USP_START_EDGE_MODE 0x00800000
#define USP_I2S_SYNC_CHG 0x00200000
#define USP_RXC_CLK_DIVISOR_MASK 0x0F000000
#define USP_RXC_CLK_DIVISOR_OFFSET 24
#define USP_SINGLE_SYNC_MODE 0x00400000
/* Tx - RX Enable Register */
#define USP_RX_ENA 0x00000001
#define USP_TX_ENA 0x00000002
/* USP Interrupt Enable and status Register */
#define USP_RX_DONE_INT 0x00000001
#define USP_TX_DONE_INT 0x00000002
#define USP_RX_OFLOW_INT 0x00000004
#define USP_TX_UFLOW_INT 0x00000008
#define USP_RX_IO_DMA_INT 0x00000010
#define USP_TX_IO_DMA_INT 0x00000020
#define USP_RXFIFO_FULL_INT 0x00000040
#define USP_TXFIFO_EMPTY_INT 0x00000080
#define USP_RXFIFO_THD_INT 0x00000100
#define USP_TXFIFO_THD_INT 0x00000200
#define USP_UART_FRM_ERR_INT 0x00000400
#define USP_RX_TIMEOUT_INT 0x00000800
#define USP_TX_ALLOUT_INT 0x00001000
#define USP_RXD_BREAK_INT 0x00008000
/* All possible TX interruots */
#define USP_TX_INTERRUPT (USP_TX_DONE_INT|USP_TX_UFLOW_INT|\
USP_TX_IO_DMA_INT|\
USP_TXFIFO_EMPTY_INT|\
USP_TXFIFO_THD_INT)
/* All possible RX interruots */
#define USP_RX_INTERRUPT (USP_RX_DONE_INT|USP_RX_OFLOW_INT|\
USP_RX_IO_DMA_INT|\
USP_RXFIFO_FULL_INT|\
USP_RXFIFO_THD_INT|\
USP_RXFIFO_THD_INT|USP_RX_TIMEOUT_INT)
#define USP_INT_ALL 0x1FFF
/* USP Pin I/O Data Register */
#define USP_RFS_PIN_VALUE_MASK 0x00000001
#define USP_TFS_PIN_VALUE_MASK 0x00000002
#define USP_RXD_PIN_VALUE_MASK 0x00000004
#define USP_TXD_PIN_VALUE_MASK 0x00000008
#define USP_SCLK_PIN_VALUE_MASK 0x00000010
/* USP RISC/DSP Mode Register */
#define USP_RISC_DSP_SEL 0x00000001
/* USP ASYNC PARAMETER Register*/
#define USP_ASYNC_TIMEOUT_MASK 0x0000FFFF
#define USP_ASYNC_TIMEOUT_OFFSET 0
#define USP_ASYNC_TIMEOUT(x) (((x)&USP_ASYNC_TIMEOUT_MASK) \
<<USP_ASYNC_TIMEOUT_OFFSET)
#define USP_ASYNC_DIV2_MASK 0x003F0000
#define USP_ASYNC_DIV2_OFFSET 16
/* USP TX DMA I/O MODE Register */
#define USP_TX_MODE_IO 0x00000001
/* USP TX DMA I/O Length Register */
#define USP_TX_DATA_LEN_MASK 0xFFFFFFFF
#define USP_TX_DATA_LEN_OFFSET 0
/* USP TX FIFO Control Register */
#define USP_TX_FIFO_WIDTH_MASK 0x00000003
#define USP_TX_FIFO_WIDTH_OFFSET 0
#define USP_TX_FIFO_THD_MASK 0x000001FC
#define USP_TX_FIFO_THD_OFFSET 2
/* USP TX FIFO Level Check Register */
#define USP_TX_FIFO_LEVEL_CHECK_MASK 0x1F
#define USP_TX_FIFO_SC_OFFSET 0
#define USP_TX_FIFO_LC_OFFSET 10
#define USP_TX_FIFO_HC_OFFSET 20
#define TX_FIFO_SC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_SC_OFFSET)
#define TX_FIFO_LC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_LC_OFFSET)
#define TX_FIFO_HC(x) (((x) & USP_TX_FIFO_LEVEL_CHECK_MASK) \
<< USP_TX_FIFO_HC_OFFSET)
/* USP TX FIFO Operation Register */
#define USP_TX_FIFO_RESET 0x00000001
#define USP_TX_FIFO_START 0x00000002
/* USP TX FIFO Status Register */
#define USP_TX_FIFO_LEVEL_MASK 0x0000007F
#define USP_TX_FIFO_LEVEL_OFFSET 0
#define USP_TX_FIFO_FULL 0x00000080
#define USP_TX_FIFO_EMPTY 0x00000100
/* USP TX FIFO Data Register */
#define USP_TX_FIFO_DATA_MASK 0xFFFFFFFF
#define USP_TX_FIFO_DATA_OFFSET 0
/* USP RX DMA I/O MODE Register */
#define USP_RX_MODE_IO 0x00000001
#define USP_RX_DMA_FLUSH 0x00000004
/* USP RX DMA I/O Length Register */
#define USP_RX_DATA_LEN_MASK 0xFFFFFFFF
#define USP_RX_DATA_LEN_OFFSET 0
/* USP RX FIFO Control Register */
#define USP_RX_FIFO_WIDTH_MASK 0x00000003
#define USP_RX_FIFO_WIDTH_OFFSET 0
#define USP_RX_FIFO_THD_MASK 0x000001FC
#define USP_RX_FIFO_THD_OFFSET 2
/* USP RX FIFO Level Check Register */
#define USP_RX_FIFO_LEVEL_CHECK_MASK 0x1F
#define USP_RX_FIFO_SC_OFFSET 0
#define USP_RX_FIFO_LC_OFFSET 10
#define USP_RX_FIFO_HC_OFFSET 20
#define RX_FIFO_SC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_SC_OFFSET)
#define RX_FIFO_LC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_LC_OFFSET)
#define RX_FIFO_HC(x) (((x) & USP_RX_FIFO_LEVEL_CHECK_MASK) \
<< USP_RX_FIFO_HC_OFFSET)
/* USP RX FIFO Operation Register */
#define USP_RX_FIFO_RESET 0x00000001
#define USP_RX_FIFO_START 0x00000002
/* USP RX FIFO Status Register */
#define USP_RX_FIFO_LEVEL_MASK 0x0000007F
#define USP_RX_FIFO_LEVEL_OFFSET 0
#define USP_RX_FIFO_FULL 0x00000080
#define USP_RX_FIFO_EMPTY 0x00000100
/* USP RX FIFO Data Register */
#define USP_RX_FIFO_DATA_MASK 0xFFFFFFFF
#define USP_RX_FIFO_DATA_OFFSET 0
/*
* When rx thd irq occur, sender just disable tx empty irq,
* Remaining data in tx fifo wil also be sent out.
*/
#define USP_FIFO_SIZE 128
#define USP_TX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
#define USP_RX_FIFO_THRESHOLD (USP_FIFO_SIZE/2)
/* FIFO_WIDTH for the USP_TX_FIFO_CTRL and USP_RX_FIFO_CTRL registers */
#define USP_FIFO_WIDTH_BYTE 0x00
#define USP_FIFO_WIDTH_WORD 0x01
#define USP_FIFO_WIDTH_DWORD 0x02
#define USP_ASYNC_DIV2 16
#define USP_PLUGOUT_RETRY_CNT 2
#define USP_TX_RX_FIFO_WIDTH_DWORD 2
#define SIRF_USP_DIV_MCLK 0
#define SIRF_USP_I2S_TFS_SYNC 0
#define SIRF_USP_I2S_RFS_SYNC 1
#endif
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