Commit 3526e9fb authored by Rob Clark's avatar Rob Clark

drm/msm/adreno: bit of init refactoring

Push a few bits down into adreno_gpu so they won't have to be duplicated
as support for additional adreno generations is added.
Signed-off-by: default avatarRob Clark <robdclark@gmail.com>
parent e2550b7a
...@@ -35,10 +35,8 @@ ...@@ -35,10 +35,8 @@
A3XX_INT0_CP_AHB_ERROR_HALT | \ A3XX_INT0_CP_AHB_ERROR_HALT | \
A3XX_INT0_UCHE_OOB_ACCESS) A3XX_INT0_UCHE_OOB_ACCESS)
extern bool hang_debug;
static bool hang_debug = false;
MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
module_param_named(hang_debug, hang_debug, bool, 0600);
static void a3xx_dump(struct msm_gpu *gpu); static void a3xx_dump(struct msm_gpu *gpu);
static void a3xx_me_init(struct msm_gpu *gpu) static void a3xx_me_init(struct msm_gpu *gpu)
...@@ -474,7 +472,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) ...@@ -474,7 +472,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
struct msm_gpu *gpu; struct msm_gpu *gpu;
struct msm_drm_private *priv = dev->dev_private; struct msm_drm_private *priv = dev->dev_private;
struct platform_device *pdev = priv->gpu_pdev; struct platform_device *pdev = priv->gpu_pdev;
struct adreno_platform_config *config;
int ret; int ret;
if (!pdev) { if (!pdev) {
...@@ -483,8 +480,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) ...@@ -483,8 +480,6 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
goto fail; goto fail;
} }
config = pdev->dev.platform_data;
a3xx_gpu = kzalloc(sizeof(*a3xx_gpu), GFP_KERNEL); a3xx_gpu = kzalloc(sizeof(*a3xx_gpu), GFP_KERNEL);
if (!a3xx_gpu) { if (!a3xx_gpu) {
ret = -ENOMEM; ret = -ENOMEM;
...@@ -496,20 +491,10 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev) ...@@ -496,20 +491,10 @@ struct msm_gpu *a3xx_gpu_init(struct drm_device *dev)
a3xx_gpu->pdev = pdev; a3xx_gpu->pdev = pdev;
gpu->fast_rate = config->fast_rate;
gpu->slow_rate = config->slow_rate;
gpu->bus_freq = config->bus_freq;
#ifdef CONFIG_MSM_BUS_SCALING
gpu->bus_scale_table = config->bus_scale_table;
#endif
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
gpu->perfcntrs = perfcntrs; gpu->perfcntrs = perfcntrs;
gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs); gpu->num_perfcntrs = ARRAY_SIZE(perfcntrs);
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, config->rev); ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs);
if (ret) if (ret)
goto fail; goto fail;
......
...@@ -23,6 +23,10 @@ ...@@ -23,6 +23,10 @@
#define ANY_ID 0xff #define ANY_ID 0xff
bool hang_debug = false;
MODULE_PARM_DESC(hang_debug, "Dump registers when hang is detected (can be slow!)");
module_param_named(hang_debug, hang_debug, bool, 0600);
struct msm_gpu *a3xx_gpu_init(struct drm_device *dev); struct msm_gpu *a3xx_gpu_init(struct drm_device *dev);
static const struct adreno_info gpulist[] = { static const struct adreno_info gpulist[] = {
......
...@@ -265,39 +265,50 @@ static const char *iommu_ports[] = { ...@@ -265,39 +265,50 @@ static const char *iommu_ports[] = {
}; };
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, struct adreno_gpu *adreno_gpu, const struct adreno_gpu_funcs *funcs)
struct adreno_rev rev)
{ {
struct adreno_platform_config *config = pdev->dev.platform_data;
struct msm_gpu *gpu = &adreno_gpu->base;
struct msm_mmu *mmu; struct msm_mmu *mmu;
int ret; int ret;
gpu->funcs = funcs; adreno_gpu->funcs = funcs;
gpu->info = adreno_info(rev); adreno_gpu->info = adreno_info(config->rev);
gpu->gmem = gpu->info->gmem; adreno_gpu->gmem = adreno_gpu->info->gmem;
gpu->revn = gpu->info->revn; adreno_gpu->revn = adreno_gpu->info->revn;
gpu->rev = rev; adreno_gpu->rev = config->rev;
gpu->fast_rate = config->fast_rate;
gpu->slow_rate = config->slow_rate;
gpu->bus_freq = config->bus_freq;
#ifdef CONFIG_MSM_BUS_SCALING
gpu->bus_scale_table = config->bus_scale_table;
#endif
DBG("fast_rate=%u, slow_rate=%u, bus_freq=%u",
gpu->fast_rate, gpu->slow_rate, gpu->bus_freq);
ret = request_firmware(&gpu->pm4, gpu->info->pm4fw, drm->dev); ret = request_firmware(&adreno_gpu->pm4, adreno_gpu->info->pm4fw, drm->dev);
if (ret) { if (ret) {
dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n", dev_err(drm->dev, "failed to load %s PM4 firmware: %d\n",
gpu->info->pm4fw, ret); adreno_gpu->info->pm4fw, ret);
return ret; return ret;
} }
ret = request_firmware(&gpu->pfp, gpu->info->pfpfw, drm->dev); ret = request_firmware(&adreno_gpu->pfp, adreno_gpu->info->pfpfw, drm->dev);
if (ret) { if (ret) {
dev_err(drm->dev, "failed to load %s PFP firmware: %d\n", dev_err(drm->dev, "failed to load %s PFP firmware: %d\n",
gpu->info->pfpfw, ret); adreno_gpu->info->pfpfw, ret);
return ret; return ret;
} }
ret = msm_gpu_init(drm, pdev, &gpu->base, &funcs->base, ret = msm_gpu_init(drm, pdev, &adreno_gpu->base, &funcs->base,
gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq", adreno_gpu->info->name, "kgsl_3d0_reg_memory", "kgsl_3d0_irq",
RB_SIZE); RB_SIZE);
if (ret) if (ret)
return ret; return ret;
mmu = gpu->base.mmu; mmu = gpu->mmu;
if (mmu) { if (mmu) {
ret = mmu->funcs->attach(mmu, iommu_ports, ret = mmu->funcs->attach(mmu, iommu_ports,
ARRAY_SIZE(iommu_ports)); ARRAY_SIZE(iommu_ports));
...@@ -306,24 +317,24 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, ...@@ -306,24 +317,24 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
} }
mutex_lock(&drm->struct_mutex); mutex_lock(&drm->struct_mutex);
gpu->memptrs_bo = msm_gem_new(drm, sizeof(*gpu->memptrs), adreno_gpu->memptrs_bo = msm_gem_new(drm, sizeof(*adreno_gpu->memptrs),
MSM_BO_UNCACHED); MSM_BO_UNCACHED);
mutex_unlock(&drm->struct_mutex); mutex_unlock(&drm->struct_mutex);
if (IS_ERR(gpu->memptrs_bo)) { if (IS_ERR(adreno_gpu->memptrs_bo)) {
ret = PTR_ERR(gpu->memptrs_bo); ret = PTR_ERR(adreno_gpu->memptrs_bo);
gpu->memptrs_bo = NULL; adreno_gpu->memptrs_bo = NULL;
dev_err(drm->dev, "could not allocate memptrs: %d\n", ret); dev_err(drm->dev, "could not allocate memptrs: %d\n", ret);
return ret; return ret;
} }
gpu->memptrs = msm_gem_vaddr(gpu->memptrs_bo); adreno_gpu->memptrs = msm_gem_vaddr(adreno_gpu->memptrs_bo);
if (!gpu->memptrs) { if (!adreno_gpu->memptrs) {
dev_err(drm->dev, "could not vmap memptrs\n"); dev_err(drm->dev, "could not vmap memptrs\n");
return -ENOMEM; return -ENOMEM;
} }
ret = msm_gem_get_iova(gpu->memptrs_bo, gpu->base.id, ret = msm_gem_get_iova(adreno_gpu->memptrs_bo, gpu->id,
&gpu->memptrs_iova); &adreno_gpu->memptrs_iova);
if (ret) { if (ret) {
dev_err(drm->dev, "could not map memptrs: %d\n", ret); dev_err(drm->dev, "could not map memptrs: %d\n", ret);
return ret; return ret;
......
...@@ -140,8 +140,7 @@ void adreno_dump(struct msm_gpu *gpu); ...@@ -140,8 +140,7 @@ void adreno_dump(struct msm_gpu *gpu);
void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords); void adreno_wait_ring(struct msm_gpu *gpu, uint32_t ndwords);
int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs, struct adreno_gpu *gpu, const struct adreno_gpu_funcs *funcs);
struct adreno_rev rev);
void adreno_gpu_cleanup(struct adreno_gpu *gpu); void adreno_gpu_cleanup(struct adreno_gpu *gpu);
......
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