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Commit 3593eb94 authored by Hendrik Brueckner's avatar Hendrik Brueckner Committed by Martin Schwidefsky
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s390/cpum_cf: add hardware counter support for IBM z14 

Add the hardware counters that are available with z14.  With z14,
the number of problem-state counters is reduced.  The initialization
is updated respectively.
Signed-off-by: default avatarHendrik Brueckner <brueckner@linux.vnet.ibm.com>
Signed-off-by: default avatarMartin Schwidefsky <schwidefsky@de.ibm.com>
parent 9a564108
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Showing with 218 additions and 60 deletions
arch/s390/kernel/perf_cpum_cf_events.c
View file @ 3593eb94
...@@ -9,34 +9,42 @@ ...@@ -9,34 +9,42 @@
/* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */ /* BEGIN: CPUM_CF COUNTER DEFINITIONS =================================== */
CPUMF_EVENT_ATTR(cf, CPU_CYCLES, 0x0000); CPUMF_EVENT_ATTR(cf_fvn1, CPU_CYCLES, 0x0000);
CPUMF_EVENT_ATTR(cf, INSTRUCTIONS, 0x0001); CPUMF_EVENT_ATTR(cf_fvn1, INSTRUCTIONS, 0x0001);
CPUMF_EVENT_ATTR(cf, L1I_DIR_WRITES, 0x0002); CPUMF_EVENT_ATTR(cf_fvn1, L1I_DIR_WRITES, 0x0002);
CPUMF_EVENT_ATTR(cf, L1I_PENALTY_CYCLES, 0x0003); CPUMF_EVENT_ATTR(cf_fvn1, L1I_PENALTY_CYCLES, 0x0003);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_CPU_CYCLES, 0x0020); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES, 0x0020);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_INSTRUCTIONS, 0x0021); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES, 0x0022);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES, 0x0023);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES, 0x0024);
CPUMF_EVENT_ATTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025); CPUMF_EVENT_ATTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES, 0x0025);
CPUMF_EVENT_ATTR(cf, L1D_DIR_WRITES, 0x0004); CPUMF_EVENT_ATTR(cf_fvn1, L1D_DIR_WRITES, 0x0004);
CPUMF_EVENT_ATTR(cf, L1D_PENALTY_CYCLES, 0x0005); CPUMF_EVENT_ATTR(cf_fvn1, L1D_PENALTY_CYCLES, 0x0005);
CPUMF_EVENT_ATTR(cf, PRNG_FUNCTIONS, 0x0040); CPUMF_EVENT_ATTR(cf_fvn3, CPU_CYCLES, 0x0000);
CPUMF_EVENT_ATTR(cf, PRNG_CYCLES, 0x0041); CPUMF_EVENT_ATTR(cf_fvn3, INSTRUCTIONS, 0x0001);
CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_FUNCTIONS, 0x0042); CPUMF_EVENT_ATTR(cf_fvn3, L1I_DIR_WRITES, 0x0002);
CPUMF_EVENT_ATTR(cf, PRNG_BLOCKED_CYCLES, 0x0043); CPUMF_EVENT_ATTR(cf_fvn3, L1I_PENALTY_CYCLES, 0x0003);
CPUMF_EVENT_ATTR(cf, SHA_FUNCTIONS, 0x0044); CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES, 0x0020);
CPUMF_EVENT_ATTR(cf, SHA_CYCLES, 0x0045); CPUMF_EVENT_ATTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS, 0x0021);
CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_FUNCTIONS, 0x0046); CPUMF_EVENT_ATTR(cf_fvn3, L1D_DIR_WRITES, 0x0004);
CPUMF_EVENT_ATTR(cf, SHA_BLOCKED_CYCLES, 0x0047); CPUMF_EVENT_ATTR(cf_fvn3, L1D_PENALTY_CYCLES, 0x0005);
CPUMF_EVENT_ATTR(cf, DEA_FUNCTIONS, 0x0048); CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_FUNCTIONS, 0x0040);
CPUMF_EVENT_ATTR(cf, DEA_CYCLES, 0x0049); CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_CYCLES, 0x0041);
CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_FUNCTIONS, 0x004a); CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS, 0x0042);
CPUMF_EVENT_ATTR(cf, DEA_BLOCKED_CYCLES, 0x004b); CPUMF_EVENT_ATTR(cf_svn_generic, PRNG_BLOCKED_CYCLES, 0x0043);
CPUMF_EVENT_ATTR(cf, AES_FUNCTIONS, 0x004c); CPUMF_EVENT_ATTR(cf_svn_generic, SHA_FUNCTIONS, 0x0044);
CPUMF_EVENT_ATTR(cf, AES_CYCLES, 0x004d); CPUMF_EVENT_ATTR(cf_svn_generic, SHA_CYCLES, 0x0045);
CPUMF_EVENT_ATTR(cf, AES_BLOCKED_FUNCTIONS, 0x004e); CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS, 0x0046);
CPUMF_EVENT_ATTR(cf, AES_BLOCKED_CYCLES, 0x004f); CPUMF_EVENT_ATTR(cf_svn_generic, SHA_BLOCKED_CYCLES, 0x0047);
CPUMF_EVENT_ATTR(cf_svn_generic, DEA_FUNCTIONS, 0x0048);
CPUMF_EVENT_ATTR(cf_svn_generic, DEA_CYCLES, 0x0049);
CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS, 0x004a);
CPUMF_EVENT_ATTR(cf_svn_generic, DEA_BLOCKED_CYCLES, 0x004b);
CPUMF_EVENT_ATTR(cf_svn_generic, AES_FUNCTIONS, 0x004c);
CPUMF_EVENT_ATTR(cf_svn_generic, AES_CYCLES, 0x004d);
CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS, 0x004e);
CPUMF_EVENT_ATTR(cf_svn_generic, AES_BLOCKED_CYCLES, 0x004f);
CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080); CPUMF_EVENT_ATTR(cf_z10, L1I_L2_SOURCED_WRITES, 0x0080);
CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081); CPUMF_EVENT_ATTR(cf_z10, L1D_L2_SOURCED_WRITES, 0x0081);
CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082); CPUMF_EVENT_ATTR(cf_z10, L1I_L3_LOCAL_WRITES, 0x0082);
...@@ -170,36 +178,105 @@ CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db); ...@@ -170,36 +178,105 @@ CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_NO_SPECIAL, 0x00db);
CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc); CPUMF_EVENT_ATTR(cf_z13, TX_C_TABORT_SPECIAL, 0x00dc);
CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0); CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1); CPUMF_EVENT_ATTR(cf_z13, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
CPUMF_EVENT_ATTR(cf_z14, L1D_WRITES_RO_EXCL, 0x0080);
CPUMF_EVENT_ATTR(cf_z14, DTLB2_WRITES, 0x0081);
CPUMF_EVENT_ATTR(cf_z14, DTLB2_MISSES, 0x0082);
CPUMF_EVENT_ATTR(cf_z14, DTLB2_HPAGE_WRITES, 0x0083);
CPUMF_EVENT_ATTR(cf_z14, DTLB2_GPAGE_WRITES, 0x0084);
CPUMF_EVENT_ATTR(cf_z14, L1D_L2D_SOURCED_WRITES, 0x0085);
CPUMF_EVENT_ATTR(cf_z14, ITLB2_WRITES, 0x0086);
CPUMF_EVENT_ATTR(cf_z14, ITLB2_MISSES, 0x0087);
CPUMF_EVENT_ATTR(cf_z14, L1I_L2I_SOURCED_WRITES, 0x0088);
CPUMF_EVENT_ATTR(cf_z14, TLB2_PTE_WRITES, 0x0089);
CPUMF_EVENT_ATTR(cf_z14, TLB2_CRSTE_WRITES, 0x008a);
CPUMF_EVENT_ATTR(cf_z14, TLB2_ENGINES_BUSY, 0x008b);
CPUMF_EVENT_ATTR(cf_z14, TX_C_TEND, 0x008c);
CPUMF_EVENT_ATTR(cf_z14, TX_NC_TEND, 0x008d);
CPUMF_EVENT_ATTR(cf_z14, L1C_TLB2_MISSES, 0x008f);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES, 0x0090);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES, 0x0091);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV, 0x0092);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES, 0x0093);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x0094);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x0095);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES, 0x0096);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x0097);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x0098);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES, 0x0099);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x009a);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x009b);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES, 0x009c);
CPUMF_EVENT_ATTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES, 0x009d);
CPUMF_EVENT_ATTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO, 0x009e);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES, 0x00a2);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES, 0x00a3);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV, 0x00a4);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES, 0x00a5);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES, 0x00a6);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV, 0x00a7);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES, 0x00a8);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES, 0x00a9);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV, 0x00aa);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES, 0x00ab);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES, 0x00ac);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV, 0x00ad);
CPUMF_EVENT_ATTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES, 0x00ae);
CPUMF_EVENT_ATTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES, 0x00af);
CPUMF_EVENT_ATTR(cf_z14, BCD_DFP_EXECUTION_SLOTS, 0x00e0);
CPUMF_EVENT_ATTR(cf_z14, VX_BCD_EXECUTION_SLOTS, 0x00e1);
CPUMF_EVENT_ATTR(cf_z14, DECIMAL_INSTRUCTIONS, 0x00e2);
CPUMF_EVENT_ATTR(cf_z14, LAST_HOST_TRANSLATIONS, 0x00e9);
CPUMF_EVENT_ATTR(cf_z14, TX_NC_TABORT, 0x00f3);
CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_NO_SPECIAL, 0x00f4);
CPUMF_EVENT_ATTR(cf_z14, TX_C_TABORT_SPECIAL, 0x00f5);
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE, 0x01c0);
CPUMF_EVENT_ATTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE, 0x01c1);
static struct attribute *cpumcf_pmu_event_attr[] __initdata = { static struct attribute *cpumcf_fvn1_pmu_event_attr[] __initdata = {
CPUMF_EVENT_PTR(cf, CPU_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, CPU_CYCLES),
CPUMF_EVENT_PTR(cf, INSTRUCTIONS), CPUMF_EVENT_PTR(cf_fvn1, INSTRUCTIONS),
CPUMF_EVENT_PTR(cf, L1I_DIR_WRITES), CPUMF_EVENT_PTR(cf_fvn1, L1I_DIR_WRITES),
CPUMF_EVENT_PTR(cf, L1I_PENALTY_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, L1I_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_CPU_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_CPU_CYCLES),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_INSTRUCTIONS), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_INSTRUCTIONS),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_DIR_WRITES), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_DIR_WRITES),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1I_PENALTY_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1I_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_DIR_WRITES), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_DIR_WRITES),
CPUMF_EVENT_PTR(cf, PROBLEM_STATE_L1D_PENALTY_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, PROBLEM_STATE_L1D_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, L1D_DIR_WRITES), CPUMF_EVENT_PTR(cf_fvn1, L1D_DIR_WRITES),
CPUMF_EVENT_PTR(cf, L1D_PENALTY_CYCLES), CPUMF_EVENT_PTR(cf_fvn1, L1D_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, PRNG_FUNCTIONS), NULL,
CPUMF_EVENT_PTR(cf, PRNG_CYCLES), };
CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf, PRNG_BLOCKED_CYCLES), static struct attribute *cpumcf_fvn3_pmu_event_attr[] __initdata = {
CPUMF_EVENT_PTR(cf, SHA_FUNCTIONS), CPUMF_EVENT_PTR(cf_fvn3, CPU_CYCLES),
CPUMF_EVENT_PTR(cf, SHA_CYCLES), CPUMF_EVENT_PTR(cf_fvn3, INSTRUCTIONS),
CPUMF_EVENT_PTR(cf, SHA_BLOCKED_FUNCTIONS), CPUMF_EVENT_PTR(cf_fvn3, L1I_DIR_WRITES),
CPUMF_EVENT_PTR(cf, SHA_BLOCKED_CYCLES), CPUMF_EVENT_PTR(cf_fvn3, L1I_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, DEA_FUNCTIONS), CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_CPU_CYCLES),
CPUMF_EVENT_PTR(cf, DEA_CYCLES), CPUMF_EVENT_PTR(cf_fvn3, PROBLEM_STATE_INSTRUCTIONS),
CPUMF_EVENT_PTR(cf, DEA_BLOCKED_FUNCTIONS), CPUMF_EVENT_PTR(cf_fvn3, L1D_DIR_WRITES),
CPUMF_EVENT_PTR(cf, DEA_BLOCKED_CYCLES), CPUMF_EVENT_PTR(cf_fvn3, L1D_PENALTY_CYCLES),
CPUMF_EVENT_PTR(cf, AES_FUNCTIONS), NULL,
CPUMF_EVENT_PTR(cf, AES_CYCLES), };
CPUMF_EVENT_PTR(cf, AES_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf, AES_BLOCKED_CYCLES), static struct attribute *cpumcf_svn_generic_pmu_event_attr[] __initdata = {
CPUMF_EVENT_PTR(cf_svn_generic, PRNG_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, PRNG_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, PRNG_BLOCKED_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, SHA_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, SHA_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, SHA_BLOCKED_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, DEA_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, DEA_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, DEA_BLOCKED_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, AES_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, AES_CYCLES),
CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_FUNCTIONS),
CPUMF_EVENT_PTR(cf_svn_generic, AES_BLOCKED_CYCLES),
NULL, NULL,
}; };
...@@ -352,6 +429,63 @@ static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = { ...@@ -352,6 +429,63 @@ static struct attribute *cpumcf_z13_pmu_event_attr[] __initdata = {
NULL, NULL,
}; };
static struct attribute *cpumcf_z14_pmu_event_attr[] __initdata = {
CPUMF_EVENT_PTR(cf_z14, L1D_WRITES_RO_EXCL),
CPUMF_EVENT_PTR(cf_z14, DTLB2_WRITES),
CPUMF_EVENT_PTR(cf_z14, DTLB2_MISSES),
CPUMF_EVENT_PTR(cf_z14, DTLB2_HPAGE_WRITES),
CPUMF_EVENT_PTR(cf_z14, DTLB2_GPAGE_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_L2D_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, ITLB2_WRITES),
CPUMF_EVENT_PTR(cf_z14, ITLB2_MISSES),
CPUMF_EVENT_PTR(cf_z14, L1I_L2I_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, TLB2_PTE_WRITES),
CPUMF_EVENT_PTR(cf_z14, TLB2_CRSTE_WRITES),
CPUMF_EVENT_PTR(cf_z14, TLB2_ENGINES_BUSY),
CPUMF_EVENT_PTR(cf_z14, TX_C_TEND),
CPUMF_EVENT_PTR(cf_z14, TX_NC_TEND),
CPUMF_EVENT_PTR(cf_z14, L1C_TLB2_MISSES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCLUSTER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFCLUSTER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1D_ONDRAWER_L4_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_OFFDRAWER_L4_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1D_ONCHIP_L3_SOURCED_WRITES_RO),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCHIP_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_ONCLUSTER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFCLUSTER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_MEMORY_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L3_SOURCED_WRITES_IV),
CPUMF_EVENT_PTR(cf_z14, L1I_ONDRAWER_L4_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, L1I_OFFDRAWER_L4_SOURCED_WRITES),
CPUMF_EVENT_PTR(cf_z14, BCD_DFP_EXECUTION_SLOTS),
CPUMF_EVENT_PTR(cf_z14, VX_BCD_EXECUTION_SLOTS),
CPUMF_EVENT_PTR(cf_z14, DECIMAL_INSTRUCTIONS),
CPUMF_EVENT_PTR(cf_z14, LAST_HOST_TRANSLATIONS),
CPUMF_EVENT_PTR(cf_z14, TX_NC_TABORT),
CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_NO_SPECIAL),
CPUMF_EVENT_PTR(cf_z14, TX_C_TABORT_SPECIAL),
CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_ONE_THR_ACTIVE),
CPUMF_EVENT_PTR(cf_z14, MT_DIAG_CYCLES_TWO_THR_ACTIVE),
NULL,
};
/* END: CPUM_CF COUNTER DEFINITIONS ===================================== */ /* END: CPUM_CF COUNTER DEFINITIONS ===================================== */
static struct attribute_group cpumcf_pmu_events_group = { static struct attribute_group cpumcf_pmu_events_group = {
...@@ -378,7 +512,8 @@ static const struct attribute_group *cpumcf_pmu_attr_groups[] = { ...@@ -378,7 +512,8 @@ static const struct attribute_group *cpumcf_pmu_attr_groups[] = {
static __init struct attribute **merge_attr(struct attribute **a, static __init struct attribute **merge_attr(struct attribute **a,
struct attribute **b) struct attribute **b,
struct attribute **c)
{ {
struct attribute **new; struct attribute **new;
int j, i; int j, i;
...@@ -387,6 +522,8 @@ static __init struct attribute **merge_attr(struct attribute **a, ...@@ -387,6 +522,8 @@ static __init struct attribute **merge_attr(struct attribute **a,
; ;
for (i = 0; b[i]; i++) for (i = 0; b[i]; i++)
j++; j++;
for (i = 0; c[i]; i++)
j++;
j++; j++;
new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL); new = kmalloc(sizeof(struct attribute *) * j, GFP_KERNEL);
...@@ -397,6 +534,8 @@ static __init struct attribute **merge_attr(struct attribute **a, ...@@ -397,6 +534,8 @@ static __init struct attribute **merge_attr(struct attribute **a,
new[j++] = a[i]; new[j++] = a[i];
for (i = 0; b[i]; i++) for (i = 0; b[i]; i++)
new[j++] = b[i]; new[j++] = b[i];
for (i = 0; c[i]; i++)
new[j++] = c[i];
new[j] = NULL; new[j] = NULL;
return new; return new;
...@@ -404,10 +543,26 @@ static __init struct attribute **merge_attr(struct attribute **a, ...@@ -404,10 +543,26 @@ static __init struct attribute **merge_attr(struct attribute **a,
__init const struct attribute_group **cpumf_cf_event_group(void) __init const struct attribute_group **cpumf_cf_event_group(void)
{ {
struct attribute **combined, **model; struct attribute **combined, **model, **cfvn, **csvn;
struct attribute *none[] = { NULL }; struct attribute *none[] = { NULL };
struct cpumf_ctr_info ci;
struct cpuid cpu_id; struct cpuid cpu_id;
/* Determine generic counters set(s) */
qctri(&ci);
switch (ci.cfvn) {
case 1:
cfvn = cpumcf_fvn1_pmu_event_attr;
break;
case 3:
cfvn = cpumcf_fvn3_pmu_event_attr;
break;
default:
cfvn = none;
}
csvn = cpumcf_svn_generic_pmu_event_attr;
/* Determine model-specific counter set(s) */
get_cpu_id(&cpu_id); get_cpu_id(&cpu_id);
switch (cpu_id.machine) { switch (cpu_id.machine) {
case 0x2097: case 0x2097:
...@@ -426,12 +581,15 @@ __init const struct attribute_group **cpumf_cf_event_group(void) ...@@ -426,12 +581,15 @@ __init const struct attribute_group **cpumf_cf_event_group(void)
case 0x2965: case 0x2965:
model = cpumcf_z13_pmu_event_attr; model = cpumcf_z13_pmu_event_attr;
break; break;
case 0x3906:
model = cpumcf_z14_pmu_event_attr;
break;
default: default:
model = none; model = none;
break; break;
} }
combined = merge_attr(cpumcf_pmu_event_attr, model); combined = merge_attr(cfvn, csvn, model);
if (combined) if (combined)
cpumcf_pmu_events_group.attrs = combined; cpumcf_pmu_events_group.attrs = combined;
return cpumcf_pmu_attr_groups; return cpumcf_pmu_attr_groups;
......
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