Commit 362ed48d authored by Linus Torvalds's avatar Linus Torvalds

Merge tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux

Pull clock framework update from Michael Turquette:
 "The common clock framework changes for 3.10 include many fixes for
  existing platforms, as well as adoption of the framework by new
  platforms and devices.

  Some long-needed fixes to the core framework are here as well as new
  features such as improved initialization of clocks from DT as well as
  framework reentrancy for nested clock operations."

* tag 'clk-for-linus-3.10' of git://git.linaro.org/people/mturquette/linux: (44 commits)
  clk: add clk_ignore_unused option to keep boot clocks on
  clk: ux500: fix mismatched types
  clk: vexpress: Add separate SP810 driver
  clk: si5351: make clk-si5351 depend on CONFIG_OF
  clk: export __clk_get_flags for modular clock providers
  clk: vt8500: Missing breaks in vtwm_pll_round_rate/_set_rate.
  clk: sunxi: Unify oscillator clock
  clk: composite: allow fixed rates & fixed dividers
  clk: composite: rename 'div' references to 'rate'
  clk: add si5351 i2c common clock driver
  clk: add device tree fixed-factor-clock binding support
  clk: Properly handle notifier return values
  clk: ux500: abx500: Define clock tree for ab850x
  clk: ux500: Add support for sysctrl clocks
  clk: mvebu: Fix valid value range checking for cpu_freq_select
  clk: Fixup locking issues for clk_set_parent
  clk: Fixup errorhandling for clk_set_parent
  clk: Restructure code for __clk_reparent
  clk: sunxi: drop an unnecesary kmalloc
  clk: sunxi: drop CLK_IGNORE_UNUSED
  ...
parents 61f3d0a9 1e435256
Frequently asked questions about the sunxi clock system
=======================================================
This document contains useful bits of information that people tend to ask
about the sunxi clock system, as well as accompanying ASCII art when adequate.
Q: Why is the main 24MHz oscillator gatable? Wouldn't that break the
system?
A: The 24MHz oscillator allows gating to save power. Indeed, if gated
carelessly the system would stop functioning, but with the right
steps, one can gate it and keep the system running. Consider this
simplified suspend example:
While the system is operational, you would see something like
24MHz 32kHz
|
PLL1
\
\_ CPU Mux
|
[CPU]
When you are about to suspend, you switch the CPU Mux to the 32kHz
oscillator:
24Mhz 32kHz
| |
PLL1 |
/
CPU Mux _/
|
[CPU]
Finally you can gate the main oscillator
32kHz
|
|
/
CPU Mux _/
|
[CPU]
Q: Were can I learn more about the sunxi clocks?
A: The linux-sunxi wiki contains a page documenting the clock registers,
you can find it at
http://linux-sunxi.org/A10/CCM
The authoritative source for information at this time is the ccmu driver
released by Allwinner, you can find it at
https://github.com/linux-sunxi/linux-sunxi/tree/sunxi-3.0/arch/arm/mach-sun4i/clock/ccmu
...@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw) ...@@ -174,9 +174,9 @@ int clk_foo_enable(struct clk_hw *hw)
}; };
Below is a matrix detailing which clk_ops are mandatory based upon the Below is a matrix detailing which clk_ops are mandatory based upon the
hardware capbilities of that clock. A cell marked as "y" means hardware capabilities of that clock. A cell marked as "y" means
mandatory, a cell marked as "n" implies that either including that mandatory, a cell marked as "n" implies that either including that
callback is invalid or otherwise uneccesary. Empty cells are either callback is invalid or otherwise unnecessary. Empty cells are either
optional or must be evaluated on a case-by-case basis. optional or must be evaluated on a case-by-case basis.
clock hardware characteristics clock hardware characteristics
...@@ -231,3 +231,14 @@ To better enforce this policy, always follow this simple rule: any ...@@ -231,3 +231,14 @@ To better enforce this policy, always follow this simple rule: any
statically initialized clock data MUST be defined in a separate file statically initialized clock data MUST be defined in a separate file
from the logic that implements its ops. Basically separate the logic from the logic that implements its ops. Basically separate the logic
from the data and all is well. from the data and all is well.
Part 6 - Disabling clock gating of unused clocks
Sometimes during development it can be useful to be able to bypass the
default disabling of unused clocks. For example, if drivers aren't enabling
clocks properly but rely on them being on from the bootloader, bypassing
the disabling means that the driver will remain functional while the issues
are sorted out.
To bypass this disabling, include "clk_ignore_unused" in the bootargs to the
kernel.
Binding for the axi-clkgen clock generator
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "adi,axi-clkgen".
- #clock-cells : from common clock binding; Should always be set to 0.
- reg : Address and length of the axi-clkgen register set.
- clocks : Phandle and clock specifier for the parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock@0xff000000 {
compatible = "adi,axi-clkgen";
#clock-cells = <0>;
reg = <0xff000000 0x1000>;
clocks = <&osc 1>;
};
Binding for simple fixed factor rate clock sources.
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be "fixed-factor-clock".
- #clock-cells : from common clock binding; shall be set to 0.
- clock-div: fixed divider.
- clock-mult: fixed multiplier.
- clocks: parent clock.
Optional properties:
- clock-output-names : From common clock binding.
Example:
clock {
compatible = "fixed-factor-clock";
clocks = <&parentclk>;
#clock-cells = <0>;
div = <2>;
mult = <1>;
};
Binding for Silicon Labs Si5351a/b/c programmable i2c clock generator.
Reference
[1] Si5351A/B/C Data Sheet
http://www.silabs.com/Support%20Documents/TechnicalDocs/Si5351.pdf
The Si5351a/b/c are programmable i2c clock generators with upto 8 output
clocks. Si5351a also has a reduced pin-count package (MSOP10) where only
3 output clocks are accessible. The internal structure of the clock
generators can be found in [1].
==I2C device node==
Required properties:
- compatible: shall be one of "silabs,si5351{a,a-msop,b,c}".
- reg: i2c device address, shall be 0x60 or 0x61.
- #clock-cells: from common clock binding; shall be set to 1.
- clocks: from common clock binding; list of parent clock
handles, shall be xtal reference clock or xtal and clkin for
si5351c only.
- #address-cells: shall be set to 1.
- #size-cells: shall be set to 0.
Optional properties:
- silabs,pll-source: pair of (number, source) for each pll. Allows
to overwrite clock source of pll A (number=0) or B (number=1).
==Child nodes==
Each of the clock outputs can be overwritten individually by
using a child node to the I2C device node. If a child node for a clock
output is not set, the eeprom configuration is not overwritten.
Required child node properties:
- reg: number of clock output.
Optional child node properties:
- silabs,clock-source: source clock of the output divider stage N, shall be
0 = multisynth N
1 = multisynth 0 for output clocks 0-3, else multisynth4
2 = xtal
3 = clkin (si5351c only)
- silabs,drive-strength: output drive strength in mA, shall be one of {2,4,6,8}.
- silabs,multisynth-source: source pll A(0) or B(1) of corresponding multisynth
divider.
- silabs,pll-master: boolean, multisynth can change pll frequency.
==Example==
/* 25MHz reference crystal */
ref25: ref25M {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <25000000>;
};
i2c-master-node {
/* Si5351a msop10 i2c clock generator */
si5351a: clock-generator@60 {
compatible = "silabs,si5351a-msop";
reg = <0x60>;
#address-cells = <1>;
#size-cells = <0>;
#clock-cells = <1>;
/* connect xtal input to 25MHz reference */
clocks = <&ref25>;
/* connect xtal input as source of pll0 and pll1 */
silabs,pll-source = <0 0>, <1 0>;
/*
* overwrite clkout0 configuration with:
* - 8mA output drive strength
* - pll0 as clock source of multisynth0
* - multisynth0 as clock source of output divider
* - multisynth0 can change pll0
* - set initial clock frequency of 74.25MHz
*/
clkout0 {
reg = <0>;
silabs,drive-strength = <8>;
silabs,multisynth-source = <0>;
silabs,clock-source = <0>;
silabs,pll-master;
clock-frequency = <74250000>;
};
/*
* overwrite clkout1 configuration with:
* - 4mA output drive strength
* - pll1 as clock source of multisynth1
* - multisynth1 as clock source of output divider
* - multisynth1 can change pll1
*/
clkout1 {
reg = <1>;
silabs,drive-strength = <4>;
silabs,multisynth-source = <1>;
silabs,clock-source = <0>;
pll-master;
};
/*
* overwrite clkout2 configuration with:
* - xtal as clock source of output divider
*/
clkout2 {
reg = <2>;
silabs,clock-source = <2>;
};
};
};
Device Tree Clock bindings for arch-sunxi
This binding uses the common clock binding[1].
[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
Required properties:
- compatible : shall be one of the following:
"allwinner,sun4i-osc-clk" - for a gatable oscillator
"allwinner,sun4i-pll1-clk" - for the main PLL clock
"allwinner,sun4i-cpu-clk" - for the CPU multiplexer clock
"allwinner,sun4i-axi-clk" - for the AXI clock
"allwinner,sun4i-axi-gates-clk" - for the AXI gates
"allwinner,sun4i-ahb-clk" - for the AHB clock
"allwinner,sun4i-ahb-gates-clk" - for the AHB gates
"allwinner,sun4i-apb0-clk" - for the APB0 clock
"allwinner,sun4i-apb0-gates-clk" - for the APB0 gates
"allwinner,sun4i-apb1-clk" - for the APB1 clock
"allwinner,sun4i-apb1-mux-clk" - for the APB1 clock muxing
"allwinner,sun4i-apb1-gates-clk" - for the APB1 gates
Required properties for all clocks:
- reg : shall be the control register address for the clock.
- clocks : shall be the input parent clock(s) phandle for the clock
- #clock-cells : from common clock binding; shall be set to 0 except for
"allwinner,sun4i-*-gates-clk" where it shall be set to 1
Additionally, "allwinner,sun4i-*-gates-clk" clocks require:
- clock-output-names : the corresponding gate names that the clock controls
For example:
osc24M: osc24M@01c20050 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-osc-clk";
reg = <0x01c20050 0x4>;
clocks = <&osc24M_fixed>;
};
pll1: pll1@01c20000 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-pll1-clk";
reg = <0x01c20000 0x4>;
clocks = <&osc24M>;
};
cpu: cpu@01c20054 {
#clock-cells = <0>;
compatible = "allwinner,sun4i-cpu-clk";
reg = <0x01c20054 0x4>;
clocks = <&osc32k>, <&osc24M>, <&pll1>;
};
Gate clock outputs
The "allwinner,sun4i-*-gates-clk" clocks provide several gatable outputs;
their corresponding offsets as present on sun4i are listed below. Note that
some of these gates are not present on sun5i.
* AXI gates ("allwinner,sun4i-axi-gates-clk")
DRAM 0
* AHB gates ("allwinner,sun4i-ahb-gates-clk")
USB0 0
EHCI0 1
OHCI0 2*
EHCI1 3
OHCI1 4*
SS 5
DMA 6
BIST 7
MMC0 8
MMC1 9
MMC2 10
MMC3 11
MS 12**
NAND 13
SDRAM 14
ACE 16
EMAC 17
TS 18
SPI0 20
SPI1 21
SPI2 22
SPI3 23
PATA 24
SATA 25**
GPS 26*
VE 32
TVD 33
TVE0 34
TVE1 35
LCD0 36
LCD1 37
CSI0 40
CSI1 41
HDMI 43
DE_BE0 44
DE_BE1 45
DE_FE0 46
DE_FE1 47
MP 50
MALI400 52
* APB0 gates ("allwinner,sun4i-apb0-gates-clk")
CODEC 0
SPDIF 1*
AC97 2
IIS 3
PIO 5
IR0 6
IR1 7
KEYPAD 10
* APB1 gates ("allwinner,sun4i-apb1-gates-clk")
I2C0 0
I2C1 1
I2C2 2
CAN 4
SCR 5
PS20 6
PS21 7
UART0 16
UART1 17
UART2 18
UART3 19
UART4 20
UART5 21
UART6 22
UART7 23
Notation:
[*]: The datasheet didn't mention these, but they are present on AW code
[**]: The datasheet had this marked as "NC" but they are used on AW code
...@@ -49,6 +49,7 @@ samsung Samsung Semiconductor ...@@ -49,6 +49,7 @@ samsung Samsung Semiconductor
sbs Smart Battery System sbs Smart Battery System
schindler Schindler schindler Schindler
sil Silicon Image sil Silicon Image
silabs Silicon Laboratories
simtek simtek
sirf SiRF Technology, Inc. sirf SiRF Technology, Inc.
snps Synopsys, Inc. snps Synopsys, Inc.
......
...@@ -44,6 +44,7 @@ parameter is applicable: ...@@ -44,6 +44,7 @@ parameter is applicable:
AVR32 AVR32 architecture is enabled. AVR32 AVR32 architecture is enabled.
AX25 Appropriate AX.25 support is enabled. AX25 Appropriate AX.25 support is enabled.
BLACKFIN Blackfin architecture is enabled. BLACKFIN Blackfin architecture is enabled.
CLK Common clock infrastructure is enabled.
DRM Direct Rendering Management support is enabled. DRM Direct Rendering Management support is enabled.
DYNAMIC_DEBUG Build in debug messages and enable them at runtime DYNAMIC_DEBUG Build in debug messages and enable them at runtime
EDD BIOS Enhanced Disk Drive Services (EDD) is enabled EDD BIOS Enhanced Disk Drive Services (EDD) is enabled
...@@ -472,6 +473,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted. ...@@ -472,6 +473,13 @@ bytes respectively. Such letter suffixes can also be entirely omitted.
cio_ignore= [S390] cio_ignore= [S390]
See Documentation/s390/CommonIO for details. See Documentation/s390/CommonIO for details.
clk_ignore_unused
[CLK]
Keep all clocks already enabled by bootloader on,
even if no driver has claimed them. This is useful
for debug and development, but should not be
needed on a platform with proper driver support.
For more information, see Documentation/clk.txt.
clock= [BUGS=X86-32, HW] gettimeofday clocksource override. clock= [BUGS=X86-32, HW] gettimeofday clocksource override.
[Deprecated] [Deprecated]
......
...@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift, ...@@ -169,7 +169,7 @@ struct clk *imx_clk_busy_mux(const char *name, void __iomem *reg, u8 shift,
busy->mux.reg = reg; busy->mux.reg = reg;
busy->mux.shift = shift; busy->mux.shift = shift;
busy->mux.width = width; busy->mux.mask = BIT(width) - 1;
busy->mux.lock = &imx_ccm_lock; busy->mux.lock = &imx_ccm_lock;
busy->mux_ops = &clk_mux_ops; busy->mux_ops = &clk_mux_ops;
......
...@@ -21,6 +21,8 @@ ...@@ -21,6 +21,8 @@
#include <linux/regulator/fixed.h> #include <linux/regulator/fixed.h>
#include <linux/regulator/machine.h> #include <linux/regulator/machine.h>
#include <linux/vexpress.h> #include <linux/vexpress.h>
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#include <asm/arch_timer.h> #include <asm/arch_timer.h>
#include <asm/mach-types.h> #include <asm/mach-types.h>
...@@ -433,7 +435,7 @@ static void __init v2m_dt_timer_init(void) ...@@ -433,7 +435,7 @@ static void __init v2m_dt_timer_init(void)
{ {
struct device_node *node = NULL; struct device_node *node = NULL;
vexpress_clk_of_init(); of_clk_init(NULL);
do { do {
node = of_find_compatible_node(node, NULL, "arm,sp804"); node = of_find_compatible_node(node, NULL, "arm,sp804");
...@@ -441,6 +443,10 @@ static void __init v2m_dt_timer_init(void) ...@@ -441,6 +443,10 @@ static void __init v2m_dt_timer_init(void)
if (node) { if (node) {
pr_info("Using SP804 '%s' as a clock & events source\n", pr_info("Using SP804 '%s' as a clock & events source\n",
node->full_name); node->full_name);
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken1"), "v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(of_clk_get_by_name(node,
"timclken2"), "v2m-timer1", "sp804"));
v2m_sp804_init(of_iomap(node, 0), v2m_sp804_init(of_iomap(node, 0),
irq_of_parse_and_map(node, 0)); irq_of_parse_and_map(node, 0));
} }
......
...@@ -55,6 +55,16 @@ config COMMON_CLK_MAX77686 ...@@ -55,6 +55,16 @@ config COMMON_CLK_MAX77686
---help--- ---help---
This driver supports Maxim 77686 crystal oscillator clock. This driver supports Maxim 77686 crystal oscillator clock.
config COMMON_CLK_SI5351
tristate "Clock driver for SiLabs 5351A/B/C"
depends on I2C
depends on OF
select REGMAP_I2C
select RATIONAL
---help---
This driver supports Silicon Labs 5351A/B/C programmable clock
generators.
config CLK_TWL6040 config CLK_TWL6040
tristate "External McPDM functional clock from twl6040" tristate "External McPDM functional clock from twl6040"
depends on TWL6040_CORE depends on TWL6040_CORE
...@@ -63,6 +73,14 @@ config CLK_TWL6040 ...@@ -63,6 +73,14 @@ config CLK_TWL6040
McPDM. McPDM module is using the external bit clock on the McPDM bus McPDM. McPDM module is using the external bit clock on the McPDM bus
as functional clock. as functional clock.
config COMMON_CLK_AXI_CLKGEN
tristate "AXI clkgen driver"
depends on ARCH_ZYNQ || MICROBLAZE
help
---help---
Support for the Analog Devices axi-clkgen pcore clock generator for Xilinx
FPGAs. It is commonly used in Analog Devices' reference designs.
endmenu endmenu
source "drivers/clk/mvebu/Kconfig" source "drivers/clk/mvebu/Kconfig"
...@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o ...@@ -7,6 +7,7 @@ obj-$(CONFIG_COMMON_CLK) += clk-fixed-factor.o
obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o obj-$(CONFIG_COMMON_CLK) += clk-fixed-rate.o
obj-$(CONFIG_COMMON_CLK) += clk-gate.o obj-$(CONFIG_COMMON_CLK) += clk-gate.o
obj-$(CONFIG_COMMON_CLK) += clk-mux.o obj-$(CONFIG_COMMON_CLK) += clk-mux.o
obj-$(CONFIG_COMMON_CLK) += clk-composite.o
# SoCs specific # SoCs specific
obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o obj-$(CONFIG_ARCH_BCM2835) += clk-bcm2835.o
...@@ -23,6 +24,7 @@ ifeq ($(CONFIG_COMMON_CLK), y) ...@@ -23,6 +24,7 @@ ifeq ($(CONFIG_COMMON_CLK), y)
obj-$(CONFIG_ARCH_MMP) += mmp/ obj-$(CONFIG_ARCH_MMP) += mmp/
endif endif
obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o obj-$(CONFIG_MACH_LOONGSON1) += clk-ls1x.o
obj-$(CONFIG_ARCH_SUNXI) += sunxi/
obj-$(CONFIG_ARCH_U8500) += ux500/ obj-$(CONFIG_ARCH_U8500) += ux500/
obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o obj-$(CONFIG_ARCH_VT8500) += clk-vt8500.o
obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o obj-$(CONFIG_ARCH_ZYNQ) += clk-zynq.o
...@@ -31,6 +33,8 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/ ...@@ -31,6 +33,8 @@ obj-$(CONFIG_ARCH_TEGRA) += tegra/
obj-$(CONFIG_X86) += x86/ obj-$(CONFIG_X86) += x86/
# Chip specific # Chip specific
obj-$(CONFIG_COMMON_CLK_AXI_CLKGEN) += clk-axi-clkgen.o
obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o obj-$(CONFIG_COMMON_CLK_WM831X) += clk-wm831x.o
obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o obj-$(CONFIG_COMMON_CLK_MAX77686) += clk-max77686.o
obj-$(CONFIG_COMMON_CLK_SI5351) += clk-si5351.o
obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o obj-$(CONFIG_CLK_TWL6040) += clk-twl6040.o
/*
* AXI clkgen driver
*
* Copyright 2012-2013 Analog Devices Inc.
* Author: Lars-Peter Clausen <lars@metafoo.de>
*
* Licensed under the GPL-2.
*
*/
#include <linux/platform_device.h>
#include <linux/clk-provider.h>
#include <linux/clk.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/of.h>
#include <linux/module.h>
#include <linux/err.h>
#define AXI_CLKGEN_REG_UPDATE_ENABLE 0x04
#define AXI_CLKGEN_REG_CLK_OUT1 0x08
#define AXI_CLKGEN_REG_CLK_OUT2 0x0c
#define AXI_CLKGEN_REG_CLK_DIV 0x10
#define AXI_CLKGEN_REG_CLK_FB1 0x14
#define AXI_CLKGEN_REG_CLK_FB2 0x18
#define AXI_CLKGEN_REG_LOCK1 0x1c
#define AXI_CLKGEN_REG_LOCK2 0x20
#define AXI_CLKGEN_REG_LOCK3 0x24
#define AXI_CLKGEN_REG_FILTER1 0x28
#define AXI_CLKGEN_REG_FILTER2 0x2c
struct axi_clkgen {
void __iomem *base;
struct clk_hw clk_hw;
};
static uint32_t axi_clkgen_lookup_filter(unsigned int m)
{
switch (m) {
case 0:
return 0x01001990;
case 1:
return 0x01001190;
case 2:
return 0x01009890;
case 3:
return 0x01001890;
case 4:
return 0x01008890;
case 5 ... 8:
return 0x01009090;
case 9 ... 11:
return 0x01000890;
case 12:
return 0x08009090;
case 13 ... 22:
return 0x01001090;
case 23 ... 36:
return 0x01008090;
case 37 ... 46:
return 0x08001090;
default:
return 0x08008090;
}
}
static const uint32_t axi_clkgen_lock_table[] = {
0x060603e8, 0x060603e8, 0x080803e8, 0x0b0b03e8,
0x0e0e03e8, 0x111103e8, 0x131303e8, 0x161603e8,
0x191903e8, 0x1c1c03e8, 0x1f1f0384, 0x1f1f0339,
0x1f1f02ee, 0x1f1f02bc, 0x1f1f028a, 0x1f1f0271,
0x1f1f023f, 0x1f1f0226, 0x1f1f020d, 0x1f1f01f4,
0x1f1f01db, 0x1f1f01c2, 0x1f1f01a9, 0x1f1f0190,
0x1f1f0190, 0x1f1f0177, 0x1f1f015e, 0x1f1f015e,
0x1f1f0145, 0x1f1f0145, 0x1f1f012c, 0x1f1f012c,
0x1f1f012c, 0x1f1f0113, 0x1f1f0113, 0x1f1f0113,
};
static uint32_t axi_clkgen_lookup_lock(unsigned int m)
{
if (m < ARRAY_SIZE(axi_clkgen_lock_table))
return axi_clkgen_lock_table[m];
return 0x1f1f00fa;
}
static const unsigned int fpfd_min = 10000;
static const unsigned int fpfd_max = 300000;
static const unsigned int fvco_min = 600000;
static const unsigned int fvco_max = 1200000;
static void axi_clkgen_calc_params(unsigned long fin, unsigned long fout,
unsigned int *best_d, unsigned int *best_m, unsigned int *best_dout)
{
unsigned long d, d_min, d_max, _d_min, _d_max;
unsigned long m, m_min, m_max;
unsigned long f, dout, best_f, fvco;
fin /= 1000;
fout /= 1000;
best_f = ULONG_MAX;
*best_d = 0;
*best_m = 0;
*best_dout = 0;
d_min = max_t(unsigned long, DIV_ROUND_UP(fin, fpfd_max), 1);
d_max = min_t(unsigned long, fin / fpfd_min, 80);
m_min = max_t(unsigned long, DIV_ROUND_UP(fvco_min, fin) * d_min, 1);
m_max = min_t(unsigned long, fvco_max * d_max / fin, 64);
for (m = m_min; m <= m_max; m++) {
_d_min = max(d_min, DIV_ROUND_UP(fin * m, fvco_max));
_d_max = min(d_max, fin * m / fvco_min);
for (d = _d_min; d <= _d_max; d++) {
fvco = fin * m / d;
dout = DIV_ROUND_CLOSEST(fvco, fout);
dout = clamp_t(unsigned long, dout, 1, 128);
f = fvco / dout;
if (abs(f - fout) < abs(best_f - fout)) {
best_f = f;
*best_d = d;
*best_m = m;
*best_dout = dout;
if (best_f == fout)
return;
}
}
}
}
static void axi_clkgen_calc_clk_params(unsigned int divider, unsigned int *low,
unsigned int *high, unsigned int *edge, unsigned int *nocount)
{
if (divider == 1)
*nocount = 1;
else
*nocount = 0;
*high = divider / 2;
*edge = divider % 2;
*low = divider - *high;
}
static void axi_clkgen_write(struct axi_clkgen *axi_clkgen,
unsigned int reg, unsigned int val)
{
writel(val, axi_clkgen->base + reg);
}
static void axi_clkgen_read(struct axi_clkgen *axi_clkgen,
unsigned int reg, unsigned int *val)
{
*val = readl(axi_clkgen->base + reg);
}
static struct axi_clkgen *clk_hw_to_axi_clkgen(struct clk_hw *clk_hw)
{
return container_of(clk_hw, struct axi_clkgen, clk_hw);
}
static int axi_clkgen_set_rate(struct clk_hw *clk_hw,
unsigned long rate, unsigned long parent_rate)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
unsigned int d, m, dout;
unsigned int nocount;
unsigned int high;
unsigned int edge;
unsigned int low;
uint32_t filter;
uint32_t lock;
if (parent_rate == 0 || rate == 0)
return -EINVAL;
axi_clkgen_calc_params(parent_rate, rate, &d, &m, &dout);
if (d == 0 || dout == 0 || m == 0)
return -EINVAL;
filter = axi_clkgen_lookup_filter(m - 1);
lock = axi_clkgen_lookup_lock(m - 1);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 0);
axi_clkgen_calc_clk_params(dout, &low, &high, &edge, &nocount);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1,
(high << 6) | low);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT2,
(edge << 7) | (nocount << 6));
axi_clkgen_calc_clk_params(d, &low, &high, &edge, &nocount);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV,
(edge << 13) | (nocount << 12) | (high << 6) | low);
axi_clkgen_calc_clk_params(m, &low, &high, &edge, &nocount);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1,
(high << 6) | low);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_CLK_FB2,
(edge << 7) | (nocount << 6));
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK1, lock & 0x3ff);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK2,
(((lock >> 16) & 0x1f) << 10) | 0x1);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_LOCK3,
(((lock >> 24) & 0x1f) << 10) | 0x3e9);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER1, filter >> 16);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_FILTER2, filter);
axi_clkgen_write(axi_clkgen, AXI_CLKGEN_REG_UPDATE_ENABLE, 1);
return 0;
}
static long axi_clkgen_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
unsigned int d, m, dout;
axi_clkgen_calc_params(*parent_rate, rate, &d, &m, &dout);
if (d == 0 || dout == 0 || m == 0)
return -EINVAL;
return *parent_rate / d * m / dout;
}
static unsigned long axi_clkgen_recalc_rate(struct clk_hw *clk_hw,
unsigned long parent_rate)
{
struct axi_clkgen *axi_clkgen = clk_hw_to_axi_clkgen(clk_hw);
unsigned int d, m, dout;
unsigned int reg;
unsigned long long tmp;
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_OUT1, &reg);
dout = (reg & 0x3f) + ((reg >> 6) & 0x3f);
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_DIV, &reg);
d = (reg & 0x3f) + ((reg >> 6) & 0x3f);
axi_clkgen_read(axi_clkgen, AXI_CLKGEN_REG_CLK_FB1, &reg);
m = (reg & 0x3f) + ((reg >> 6) & 0x3f);
if (d == 0 || dout == 0)
return 0;
tmp = (unsigned long long)(parent_rate / d) * m;
do_div(tmp, dout);
if (tmp > ULONG_MAX)
return ULONG_MAX;
return tmp;
}
static const struct clk_ops axi_clkgen_ops = {
.recalc_rate = axi_clkgen_recalc_rate,
.round_rate = axi_clkgen_round_rate,
.set_rate = axi_clkgen_set_rate,
};
static int axi_clkgen_probe(struct platform_device *pdev)
{
struct axi_clkgen *axi_clkgen;
struct clk_init_data init;
const char *parent_name;
const char *clk_name;
struct resource *mem;
struct clk *clk;
axi_clkgen = devm_kzalloc(&pdev->dev, sizeof(*axi_clkgen), GFP_KERNEL);
if (!axi_clkgen)
return -ENOMEM;
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
axi_clkgen->base = devm_ioremap_resource(&pdev->dev, mem);
if (IS_ERR(axi_clkgen->base))
return PTR_ERR(axi_clkgen->base);
parent_name = of_clk_get_parent_name(pdev->dev.of_node, 0);
if (!parent_name)
return -EINVAL;
clk_name = pdev->dev.of_node->name;
of_property_read_string(pdev->dev.of_node, "clock-output-names",
&clk_name);
init.name = clk_name;
init.ops = &axi_clkgen_ops;
init.flags = 0;
init.parent_names = &parent_name;
init.num_parents = 1;
axi_clkgen->clk_hw.init = &init;
clk = devm_clk_register(&pdev->dev, &axi_clkgen->clk_hw);
if (IS_ERR(clk))
return PTR_ERR(clk);
return of_clk_add_provider(pdev->dev.of_node, of_clk_src_simple_get,
clk);
}
static int axi_clkgen_remove(struct platform_device *pdev)
{
of_clk_del_provider(pdev->dev.of_node);
return 0;
}
static const struct of_device_id axi_clkgen_ids[] = {
{ .compatible = "adi,axi-clkgen-1.00.a" },
{ },
};
MODULE_DEVICE_TABLE(of, axi_clkgen_ids);
static struct platform_driver axi_clkgen_driver = {
.driver = {
.name = "adi-axi-clkgen",
.owner = THIS_MODULE,
.of_match_table = axi_clkgen_ids,
},
.probe = axi_clkgen_probe,
.remove = axi_clkgen_remove,
};
module_platform_driver(axi_clkgen_driver);
MODULE_LICENSE("GPL v2");
MODULE_AUTHOR("Lars-Peter Clausen <lars@metafoo.de>");
MODULE_DESCRIPTION("Driver for the Analog Devices' AXI clkgen pcore clock generator");
/*
* Copyright (c) 2013 NVIDIA CORPORATION. All rights reserved.
*
* This program is free software; you can redistribute it and/or modify it
* under the terms and conditions of the GNU General Public License,
* version 2, as published by the Free Software Foundation.
*
* This program is distributed in the hope it will be useful, but WITHOUT
* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
* more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/>.
*/
#include <linux/clk.h>
#include <linux/clk-provider.h>
#include <linux/err.h>
#include <linux/slab.h>
#define to_clk_composite(_hw) container_of(_hw, struct clk_composite, hw)
static u8 clk_composite_get_parent(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk_hw *mux_hw = composite->mux_hw;
mux_hw->clk = hw->clk;
return mux_ops->get_parent(mux_hw);
}
static int clk_composite_set_parent(struct clk_hw *hw, u8 index)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *mux_ops = composite->mux_ops;
struct clk_hw *mux_hw = composite->mux_hw;
mux_hw->clk = hw->clk;
return mux_ops->set_parent(mux_hw, index);
}
static unsigned long clk_composite_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
rate_hw->clk = hw->clk;
return rate_ops->recalc_rate(rate_hw, parent_rate);
}
static long clk_composite_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *prate)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
rate_hw->clk = hw->clk;
return rate_ops->round_rate(rate_hw, rate, prate);
}
static int clk_composite_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *rate_ops = composite->rate_ops;
struct clk_hw *rate_hw = composite->rate_hw;
rate_hw->clk = hw->clk;
return rate_ops->set_rate(rate_hw, rate, parent_rate);
}
static int clk_composite_is_enabled(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
return gate_ops->is_enabled(gate_hw);
}
static int clk_composite_enable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
return gate_ops->enable(gate_hw);
}
static void clk_composite_disable(struct clk_hw *hw)
{
struct clk_composite *composite = to_clk_composite(hw);
const struct clk_ops *gate_ops = composite->gate_ops;
struct clk_hw *gate_hw = composite->gate_hw;
gate_hw->clk = hw->clk;
gate_ops->disable(gate_hw);
}
struct clk *clk_register_composite(struct device *dev, const char *name,
const char **parent_names, int num_parents,
struct clk_hw *mux_hw, const struct clk_ops *mux_ops,
struct clk_hw *rate_hw, const struct clk_ops *rate_ops,
struct clk_hw *gate_hw, const struct clk_ops *gate_ops,
unsigned long flags)
{
struct clk *clk;
struct clk_init_data init;
struct clk_composite *composite;
struct clk_ops *clk_composite_ops;
composite = kzalloc(sizeof(*composite), GFP_KERNEL);
if (!composite) {
pr_err("%s: could not allocate composite clk\n", __func__);
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.flags = flags | CLK_IS_BASIC;
init.parent_names = parent_names;
init.num_parents = num_parents;
clk_composite_ops = &composite->ops;
if (mux_hw && mux_ops) {
if (!mux_ops->get_parent || !mux_ops->set_parent) {
clk = ERR_PTR(-EINVAL);
goto err;
}
composite->mux_hw = mux_hw;
composite->mux_ops = mux_ops;
clk_composite_ops->get_parent = clk_composite_get_parent;
clk_composite_ops->set_parent = clk_composite_set_parent;
}
if (rate_hw && rate_ops) {
if (!rate_ops->recalc_rate) {
clk = ERR_PTR(-EINVAL);
goto err;
}
/* .round_rate is a prerequisite for .set_rate */
if (rate_ops->round_rate) {
clk_composite_ops->round_rate = clk_composite_round_rate;
if (rate_ops->set_rate) {
clk_composite_ops->set_rate = clk_composite_set_rate;
}
} else {
WARN(rate_ops->set_rate,
"%s: missing round_rate op is required\n",
__func__);
}
composite->rate_hw = rate_hw;
composite->rate_ops = rate_ops;
clk_composite_ops->recalc_rate = clk_composite_recalc_rate;
}
if (gate_hw && gate_ops) {
if (!gate_ops->is_enabled || !gate_ops->enable ||
!gate_ops->disable) {
clk = ERR_PTR(-EINVAL);
goto err;
}
composite->gate_hw = gate_hw;
composite->gate_ops = gate_ops;
clk_composite_ops->is_enabled = clk_composite_is_enabled;
clk_composite_ops->enable = clk_composite_enable;
clk_composite_ops->disable = clk_composite_disable;
}
init.ops = clk_composite_ops;
composite->hw.init = &init;
clk = clk_register(dev, &composite->hw);
if (IS_ERR(clk))
goto err;
if (composite->mux_hw)
composite->mux_hw->clk = clk;
if (composite->rate_hw)
composite->rate_hw->clk = clk;
if (composite->gate_hw)
composite->gate_hw->clk = clk;
return clk;
err:
kfree(composite);
return clk;
}
...@@ -109,8 +109,9 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw, ...@@ -109,8 +109,9 @@ static unsigned long clk_divider_recalc_rate(struct clk_hw *hw,
div = _get_div(divider, val); div = _get_div(divider, val);
if (!div) { if (!div) {
WARN(1, "%s: Invalid divisor for clock %s\n", __func__, WARN(!(divider->flags & CLK_DIVIDER_ALLOW_ZERO),
__clk_get_name(hw->clk)); "%s: Zero divisor and CLK_DIVIDER_ALLOW_ZERO not set\n",
__clk_get_name(hw->clk));
return parent_rate; return parent_rate;
} }
......
...@@ -11,6 +11,7 @@ ...@@ -11,6 +11,7 @@
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/of.h>
/* /*
* DOC: basic fixed multiplier and divider clock that cannot gate * DOC: basic fixed multiplier and divider clock that cannot gate
...@@ -96,3 +97,38 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name, ...@@ -96,3 +97,38 @@ struct clk *clk_register_fixed_factor(struct device *dev, const char *name,
return clk; return clk;
} }
#ifdef CONFIG_OF
/**
* of_fixed_factor_clk_setup() - Setup function for simple fixed factor clock
*/
void __init of_fixed_factor_clk_setup(struct device_node *node)
{
struct clk *clk;
const char *clk_name = node->name;
const char *parent_name;
u32 div, mult;
if (of_property_read_u32(node, "clock-div", &div)) {
pr_err("%s Fixed factor clock <%s> must have a clock-div property\n",
__func__, node->name);
return;
}
if (of_property_read_u32(node, "clock-mult", &mult)) {
pr_err("%s Fixed factor clock <%s> must have a clokc-mult property\n",
__func__, node->name);
return;
}
of_property_read_string(node, "clock-output-names", &clk_name);
parent_name = of_clk_get_parent_name(node, 0);
clk = clk_register_fixed_factor(NULL, clk_name, parent_name, 0,
mult, div);
if (!IS_ERR(clk))
of_clk_add_provider(node, of_clk_src_simple_get, clk);
}
EXPORT_SYMBOL_GPL(of_fixed_factor_clk_setup);
CLK_OF_DECLARE(fixed_factor_clk, "fixed-factor-clock",
of_fixed_factor_clk_setup);
#endif
...@@ -32,6 +32,7 @@ ...@@ -32,6 +32,7 @@
static u8 clk_mux_get_parent(struct clk_hw *hw) static u8 clk_mux_get_parent(struct clk_hw *hw)
{ {
struct clk_mux *mux = to_clk_mux(hw); struct clk_mux *mux = to_clk_mux(hw);
int num_parents = __clk_get_num_parents(hw->clk);
u32 val; u32 val;
/* /*
...@@ -42,7 +43,16 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) ...@@ -42,7 +43,16 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
* val = 0x4 really means "bit 2, index starts at bit 0" * val = 0x4 really means "bit 2, index starts at bit 0"
*/ */
val = readl(mux->reg) >> mux->shift; val = readl(mux->reg) >> mux->shift;
val &= (1 << mux->width) - 1; val &= mux->mask;
if (mux->table) {
int i;
for (i = 0; i < num_parents; i++)
if (mux->table[i] == val)
return i;
return -EINVAL;
}
if (val && (mux->flags & CLK_MUX_INDEX_BIT)) if (val && (mux->flags & CLK_MUX_INDEX_BIT))
val = ffs(val) - 1; val = ffs(val) - 1;
...@@ -50,7 +60,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw) ...@@ -50,7 +60,7 @@ static u8 clk_mux_get_parent(struct clk_hw *hw)
if (val && (mux->flags & CLK_MUX_INDEX_ONE)) if (val && (mux->flags & CLK_MUX_INDEX_ONE))
val--; val--;
if (val >= __clk_get_num_parents(hw->clk)) if (val >= num_parents)
return -EINVAL; return -EINVAL;
return val; return val;
...@@ -62,17 +72,22 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index) ...@@ -62,17 +72,22 @@ static int clk_mux_set_parent(struct clk_hw *hw, u8 index)
u32 val; u32 val;
unsigned long flags = 0; unsigned long flags = 0;
if (mux->flags & CLK_MUX_INDEX_BIT) if (mux->table)
index = (1 << ffs(index)); index = mux->table[index];
if (mux->flags & CLK_MUX_INDEX_ONE) else {
index++; if (mux->flags & CLK_MUX_INDEX_BIT)
index = (1 << ffs(index));
if (mux->flags & CLK_MUX_INDEX_ONE)
index++;
}
if (mux->lock) if (mux->lock)
spin_lock_irqsave(mux->lock, flags); spin_lock_irqsave(mux->lock, flags);
val = readl(mux->reg); val = readl(mux->reg);
val &= ~(((1 << mux->width) - 1) << mux->shift); val &= ~(mux->mask << mux->shift);
val |= index << mux->shift; val |= index << mux->shift;
writel(val, mux->reg); writel(val, mux->reg);
...@@ -88,10 +103,10 @@ const struct clk_ops clk_mux_ops = { ...@@ -88,10 +103,10 @@ const struct clk_ops clk_mux_ops = {
}; };
EXPORT_SYMBOL_GPL(clk_mux_ops); EXPORT_SYMBOL_GPL(clk_mux_ops);
struct clk *clk_register_mux(struct device *dev, const char *name, struct clk *clk_register_mux_table(struct device *dev, const char *name,
const char **parent_names, u8 num_parents, unsigned long flags, const char **parent_names, u8 num_parents, unsigned long flags,
void __iomem *reg, u8 shift, u8 width, void __iomem *reg, u8 shift, u32 mask,
u8 clk_mux_flags, spinlock_t *lock) u8 clk_mux_flags, u32 *table, spinlock_t *lock)
{ {
struct clk_mux *mux; struct clk_mux *mux;
struct clk *clk; struct clk *clk;
...@@ -113,9 +128,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name, ...@@ -113,9 +128,10 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
/* struct clk_mux assignments */ /* struct clk_mux assignments */
mux->reg = reg; mux->reg = reg;
mux->shift = shift; mux->shift = shift;
mux->width = width; mux->mask = mask;
mux->flags = clk_mux_flags; mux->flags = clk_mux_flags;
mux->lock = lock; mux->lock = lock;
mux->table = table;
mux->hw.init = &init; mux->hw.init = &init;
clk = clk_register(dev, &mux->hw); clk = clk_register(dev, &mux->hw);
...@@ -125,3 +141,15 @@ struct clk *clk_register_mux(struct device *dev, const char *name, ...@@ -125,3 +141,15 @@ struct clk *clk_register_mux(struct device *dev, const char *name,
return clk; return clk;
} }
struct clk *clk_register_mux(struct device *dev, const char *name,
const char **parent_names, u8 num_parents, unsigned long flags,
void __iomem *reg, u8 shift, u8 width,
u8 clk_mux_flags, spinlock_t *lock)
{
u32 mask = BIT(width) - 1;
return clk_register_mux_table(dev, name, parent_names, num_parents,
flags, reg, shift, mask, clk_mux_flags,
NULL, lock);
}
...@@ -1113,7 +1113,7 @@ void __init sirfsoc_of_clk_init(void) ...@@ -1113,7 +1113,7 @@ void __init sirfsoc_of_clk_init(void)
for (i = pll1; i < maxclk; i++) { for (i = pll1; i < maxclk; i++) {
prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]); prima2_clks[i] = clk_register(NULL, prima2_clk_hw_array[i]);
BUG_ON(!prima2_clks[i]); BUG_ON(IS_ERR(prima2_clks[i]));
} }
clk_register_clkdev(prima2_clks[cpu], NULL, "cpu"); clk_register_clkdev(prima2_clks[cpu], NULL, "cpu");
clk_register_clkdev(prima2_clks[io], NULL, "io"); clk_register_clkdev(prima2_clks[io], NULL, "io");
......
This diff is collapsed.
/*
* clk-si5351.h: Silicon Laboratories Si5351A/B/C I2C Clock Generator
*
* Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
* Rabeeh Khoury <rabeeh@solid-run.com>
*
* This program is free software; you can redistribute it and/or modify it
* under the terms of the GNU General Public License as published by the
* Free Software Foundation; either version 2 of the License, or (at your
* option) any later version.
*/
#ifndef _CLK_SI5351_H_
#define _CLK_SI5351_H_
#define SI5351_BUS_BASE_ADDR 0x60
#define SI5351_PLL_VCO_MIN 600000000
#define SI5351_PLL_VCO_MAX 900000000
#define SI5351_MULTISYNTH_MIN_FREQ 1000000
#define SI5351_MULTISYNTH_DIVBY4_FREQ 150000000
#define SI5351_MULTISYNTH_MAX_FREQ 160000000
#define SI5351_MULTISYNTH67_MAX_FREQ SI5351_MULTISYNTH_DIVBY4_FREQ
#define SI5351_CLKOUT_MIN_FREQ 8000
#define SI5351_CLKOUT_MAX_FREQ SI5351_MULTISYNTH_MAX_FREQ
#define SI5351_CLKOUT67_MAX_FREQ SI5351_MULTISYNTH67_MAX_FREQ
#define SI5351_PLL_A_MIN 15
#define SI5351_PLL_A_MAX 90
#define SI5351_PLL_B_MAX (SI5351_PLL_C_MAX-1)
#define SI5351_PLL_C_MAX 1048575
#define SI5351_MULTISYNTH_A_MIN 6
#define SI5351_MULTISYNTH_A_MAX 1800
#define SI5351_MULTISYNTH67_A_MAX 254
#define SI5351_MULTISYNTH_B_MAX (SI5351_MULTISYNTH_C_MAX-1)
#define SI5351_MULTISYNTH_C_MAX 1048575
#define SI5351_MULTISYNTH_P1_MAX ((1<<18)-1)
#define SI5351_MULTISYNTH_P2_MAX ((1<<20)-1)
#define SI5351_MULTISYNTH_P3_MAX ((1<<20)-1)
#define SI5351_DEVICE_STATUS 0
#define SI5351_INTERRUPT_STATUS 1
#define SI5351_INTERRUPT_MASK 2
#define SI5351_STATUS_SYS_INIT (1<<7)
#define SI5351_STATUS_LOL_B (1<<6)
#define SI5351_STATUS_LOL_A (1<<5)
#define SI5351_STATUS_LOS (1<<4)
#define SI5351_OUTPUT_ENABLE_CTRL 3
#define SI5351_OEB_PIN_ENABLE_CTRL 9
#define SI5351_PLL_INPUT_SOURCE 15
#define SI5351_CLKIN_DIV_MASK (3<<6)
#define SI5351_CLKIN_DIV_1 (0<<6)
#define SI5351_CLKIN_DIV_2 (1<<6)
#define SI5351_CLKIN_DIV_4 (2<<6)
#define SI5351_CLKIN_DIV_8 (3<<6)
#define SI5351_PLLB_SOURCE (1<<3)
#define SI5351_PLLA_SOURCE (1<<2)
#define SI5351_CLK0_CTRL 16
#define SI5351_CLK1_CTRL 17
#define SI5351_CLK2_CTRL 18
#define SI5351_CLK3_CTRL 19
#define SI5351_CLK4_CTRL 20
#define SI5351_CLK5_CTRL 21
#define SI5351_CLK6_CTRL 22
#define SI5351_CLK7_CTRL 23
#define SI5351_CLK_POWERDOWN (1<<7)
#define SI5351_CLK_INTEGER_MODE (1<<6)
#define SI5351_CLK_PLL_SELECT (1<<5)
#define SI5351_CLK_INVERT (1<<4)
#define SI5351_CLK_INPUT_MASK (3<<2)
#define SI5351_CLK_INPUT_XTAL (0<<2)
#define SI5351_CLK_INPUT_CLKIN (1<<2)
#define SI5351_CLK_INPUT_MULTISYNTH_0_4 (2<<2)
#define SI5351_CLK_INPUT_MULTISYNTH_N (3<<2)
#define SI5351_CLK_DRIVE_STRENGTH_MASK (3<<0)
#define SI5351_CLK_DRIVE_STRENGTH_2MA (0<<0)
#define SI5351_CLK_DRIVE_STRENGTH_4MA (1<<0)
#define SI5351_CLK_DRIVE_STRENGTH_6MA (2<<0)
#define SI5351_CLK_DRIVE_STRENGTH_8MA (3<<0)
#define SI5351_CLK3_0_DISABLE_STATE 24
#define SI5351_CLK7_4_DISABLE_STATE 25
#define SI5351_CLK_DISABLE_STATE_LOW 0
#define SI5351_CLK_DISABLE_STATE_HIGH 1
#define SI5351_CLK_DISABLE_STATE_FLOAT 2
#define SI5351_CLK_DISABLE_STATE_NEVER 3
#define SI5351_PARAMETERS_LENGTH 8
#define SI5351_PLLA_PARAMETERS 26
#define SI5351_PLLB_PARAMETERS 34
#define SI5351_CLK0_PARAMETERS 42
#define SI5351_CLK1_PARAMETERS 50
#define SI5351_CLK2_PARAMETERS 58
#define SI5351_CLK3_PARAMETERS 66
#define SI5351_CLK4_PARAMETERS 74
#define SI5351_CLK5_PARAMETERS 82
#define SI5351_CLK6_PARAMETERS 90
#define SI5351_CLK7_PARAMETERS 91
#define SI5351_CLK6_7_OUTPUT_DIVIDER 92
#define SI5351_OUTPUT_CLK_DIV_MASK (7 << 4)
#define SI5351_OUTPUT_CLK6_DIV_MASK (7 << 0)
#define SI5351_OUTPUT_CLK_DIV_SHIFT 4
#define SI5351_OUTPUT_CLK_DIV6_SHIFT 0
#define SI5351_OUTPUT_CLK_DIV_1 0
#define SI5351_OUTPUT_CLK_DIV_2 1
#define SI5351_OUTPUT_CLK_DIV_4 2
#define SI5351_OUTPUT_CLK_DIV_8 3
#define SI5351_OUTPUT_CLK_DIV_16 4
#define SI5351_OUTPUT_CLK_DIV_32 5
#define SI5351_OUTPUT_CLK_DIV_64 6
#define SI5351_OUTPUT_CLK_DIV_128 7
#define SI5351_OUTPUT_CLK_DIVBY4 (3<<2)
#define SI5351_SSC_PARAM0 149
#define SI5351_SSC_PARAM1 150
#define SI5351_SSC_PARAM2 151
#define SI5351_SSC_PARAM3 152
#define SI5351_SSC_PARAM4 153
#define SI5351_SSC_PARAM5 154
#define SI5351_SSC_PARAM6 155
#define SI5351_SSC_PARAM7 156
#define SI5351_SSC_PARAM8 157
#define SI5351_SSC_PARAM9 158
#define SI5351_SSC_PARAM10 159
#define SI5351_SSC_PARAM11 160
#define SI5351_SSC_PARAM12 161
#define SI5351_VXCO_PARAMETERS_LOW 162
#define SI5351_VXCO_PARAMETERS_MID 163
#define SI5351_VXCO_PARAMETERS_HIGH 164
#define SI5351_CLK0_PHASE_OFFSET 165
#define SI5351_CLK1_PHASE_OFFSET 166
#define SI5351_CLK2_PHASE_OFFSET 167
#define SI5351_CLK3_PHASE_OFFSET 168
#define SI5351_CLK4_PHASE_OFFSET 169
#define SI5351_CLK5_PHASE_OFFSET 170
#define SI5351_PLL_RESET 177
#define SI5351_PLL_RESET_B (1<<7)
#define SI5351_PLL_RESET_A (1<<5)
#define SI5351_CRYSTAL_LOAD 183
#define SI5351_CRYSTAL_LOAD_MASK (3<<6)
#define SI5351_CRYSTAL_LOAD_6PF (1<<6)
#define SI5351_CRYSTAL_LOAD_8PF (2<<6)
#define SI5351_CRYSTAL_LOAD_10PF (3<<6)
#define SI5351_FANOUT_ENABLE 187
#define SI5351_CLKIN_ENABLE (1<<7)
#define SI5351_XTAL_ENABLE (1<<6)
#define SI5351_MULTISYNTH_ENABLE (1<<4)
#endif
...@@ -488,6 +488,7 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -488,6 +488,7 @@ static int vtwm_pll_set_rate(struct clk_hw *hw, unsigned long rate,
case PLL_TYPE_WM8750: case PLL_TYPE_WM8750:
wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2); wm8750_find_pll_bits(rate, parent_rate, &filter, &mul, &div1, &div2);
pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2); pll_val = WM8750_BITS_TO_VAL(filter, mul, div1, div2);
break;
default: default:
pr_err("%s: invalid pll type\n", __func__); pr_err("%s: invalid pll type\n", __func__);
return 0; return 0;
...@@ -523,6 +524,7 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate, ...@@ -523,6 +524,7 @@ static long vtwm_pll_round_rate(struct clk_hw *hw, unsigned long rate,
case PLL_TYPE_WM8750: case PLL_TYPE_WM8750:
wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2); wm8750_find_pll_bits(rate, *prate, &filter, &mul, &div1, &div2);
round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2); round_rate = WM8750_BITS_TO_FREQ(*prate, mul, div1, div2);
break;
default: default:
round_rate = 0; round_rate = 0;
} }
......
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
#include <linux/slab.h> #include <linux/slab.h>
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/clk/zynq.h>
static void __iomem *slcr_base; static void __iomem *slcr_base;
......
This diff is collapsed.
...@@ -156,7 +156,7 @@ static u32 __init armada_370_get_cpu_freq(void __iomem *sar) ...@@ -156,7 +156,7 @@ static u32 __init armada_370_get_cpu_freq(void __iomem *sar)
cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) & cpu_freq_select = ((readl(sar) >> SARL_A370_PCLK_FREQ_OPT) &
SARL_A370_PCLK_FREQ_OPT_MASK); SARL_A370_PCLK_FREQ_OPT_MASK);
if (cpu_freq_select > ARRAY_SIZE(armada_370_cpu_frequencies)) { if (cpu_freq_select >= ARRAY_SIZE(armada_370_cpu_frequencies)) {
pr_err("CPU freq select unsuported %d\n", cpu_freq_select); pr_err("CPU freq select unsuported %d\n", cpu_freq_select);
cpu_freq = 0; cpu_freq = 0;
} else } else
...@@ -278,7 +278,7 @@ static u32 __init armada_xp_get_cpu_freq(void __iomem *sar) ...@@ -278,7 +278,7 @@ static u32 __init armada_xp_get_cpu_freq(void __iomem *sar)
cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) & cpu_freq_select |= (((readl(sar+4) >> SARH_AXP_PCLK_FREQ_OPT) &
SARH_AXP_PCLK_FREQ_OPT_MASK) SARH_AXP_PCLK_FREQ_OPT_MASK)
<< SARH_AXP_PCLK_FREQ_OPT_SHIFT); << SARH_AXP_PCLK_FREQ_OPT_SHIFT);
if (cpu_freq_select > ARRAY_SIZE(armada_xp_cpu_frequencies)) { if (cpu_freq_select >= ARRAY_SIZE(armada_xp_cpu_frequencies)) {
pr_err("CPU freq select unsuported: %d\n", cpu_freq_select); pr_err("CPU freq select unsuported: %d\n", cpu_freq_select);
cpu_freq = 0; cpu_freq = 0;
} else } else
......
...@@ -16,7 +16,6 @@ ...@@ -16,7 +16,6 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/of.h> #include <linux/of.h>
#include <linux/delay.h> #include <linux/delay.h>
#include "clk-cpu.h"
#define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0 #define SYS_CTRL_CLK_DIVIDER_CTRL_OFFSET 0x0
#define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC #define SYS_CTRL_CLK_DIVIDER_VALUE_OFFSET 0xC
...@@ -173,17 +172,5 @@ void __init of_cpu_clk_setup(struct device_node *node) ...@@ -173,17 +172,5 @@ void __init of_cpu_clk_setup(struct device_node *node)
kfree(cpuclk); kfree(cpuclk);
} }
static const __initconst struct of_device_id clk_cpu_match[] = { CLK_OF_DECLARE(armada_xp_cpu_clock, "marvell,armada-xp-cpu-clock",
{ of_cpu_clk_setup);
.compatible = "marvell,armada-xp-cpu-clock",
.data = of_cpu_clk_setup,
},
{
/* sentinel */
},
};
void __init mvebu_cpu_clk_init(void)
{
of_clk_init(clk_cpu_match);
}
/*
* Marvell MVEBU CPU clock handling.
*
* Copyright (C) 2012 Marvell
*
* Gregory CLEMENT <gregory.clement@free-electrons.com>
*
* This file is licensed under the terms of the GNU General Public
* License version 2. This program is licensed "as is" without any
* warranty of any kind, whether express or implied.
*/
#ifndef __MVEBU_CLK_CPU_H
#define __MVEBU_CLK_CPU_H
#ifdef CONFIG_MVEBU_CLK_CPU
void __init mvebu_cpu_clk_init(void);
#else
static inline void mvebu_cpu_clk_init(void) {}
#endif
#endif
...@@ -10,18 +10,14 @@ ...@@ -10,18 +10,14 @@
* warranty of any kind, whether express or implied. * warranty of any kind, whether express or implied.
*/ */
#include <linux/kernel.h> #include <linux/kernel.h>
#include <linux/clk.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/of_address.h>
#include <linux/clk/mvebu.h>
#include <linux/of.h> #include <linux/of.h>
#include "clk-core.h" #include "clk-core.h"
#include "clk-cpu.h"
#include "clk-gating-ctrl.h" #include "clk-gating-ctrl.h"
void __init mvebu_clocks_init(void) void __init mvebu_clocks_init(void)
{ {
mvebu_core_clk_init(); mvebu_core_clk_init();
mvebu_gating_clk_init(); mvebu_gating_clk_init();
mvebu_cpu_clk_init(); of_clk_init(NULL);
} }
...@@ -13,6 +13,7 @@ ...@@ -13,6 +13,7 @@
#include <linux/io.h> #include <linux/io.h>
#include <linux/jiffies.h> #include <linux/jiffies.h>
#include <linux/spinlock.h> #include <linux/spinlock.h>
#include "clk.h"
DEFINE_SPINLOCK(mxs_lock); DEFINE_SPINLOCK(mxs_lock);
......
...@@ -960,47 +960,47 @@ void __init spear1340_clk_init(void) ...@@ -960,47 +960,47 @@ void __init spear1340_clk_init(void)
SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock); SPEAR1340_SPDIF_IN_CLK_ENB, 0, &_lock);
clk_register_clkdev(clk, NULL, "d0100000.spdif-in"); clk_register_clkdev(clk, NULL, "d0100000.spdif-in");
clk = clk_register_gate(NULL, "acp_clk", "acp_mclk", 0, clk = clk_register_gate(NULL, "acp_clk", "ahb_clk", 0,
SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0, SPEAR1340_PERIP2_CLK_ENB, SPEAR1340_ACP_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "acp_clk"); clk_register_clkdev(clk, NULL, "acp_clk");
clk = clk_register_gate(NULL, "plgpio_clk", "plgpio_mclk", 0, clk = clk_register_gate(NULL, "plgpio_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_PLGPIO_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "e2800000.gpio"); clk_register_clkdev(clk, NULL, "e2800000.gpio");
clk = clk_register_gate(NULL, "video_dec_clk", "video_dec_mclk", 0, clk = clk_register_gate(NULL, "video_dec_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_DEC_CLK_ENB,
0, &_lock); 0, &_lock);
clk_register_clkdev(clk, NULL, "video_dec"); clk_register_clkdev(clk, NULL, "video_dec");
clk = clk_register_gate(NULL, "video_enc_clk", "video_enc_mclk", 0, clk = clk_register_gate(NULL, "video_enc_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_ENC_CLK_ENB,
0, &_lock); 0, &_lock);
clk_register_clkdev(clk, NULL, "video_enc"); clk_register_clkdev(clk, NULL, "video_enc");
clk = clk_register_gate(NULL, "video_in_clk", "video_in_mclk", 0, clk = clk_register_gate(NULL, "video_in_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_VIDEO_IN_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "spear_vip"); clk_register_clkdev(clk, NULL, "spear_vip");
clk = clk_register_gate(NULL, "cam0_clk", "cam0_mclk", 0, clk = clk_register_gate(NULL, "cam0_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM0_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "d0200000.cam0"); clk_register_clkdev(clk, NULL, "d0200000.cam0");
clk = clk_register_gate(NULL, "cam1_clk", "cam1_mclk", 0, clk = clk_register_gate(NULL, "cam1_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM1_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "d0300000.cam1"); clk_register_clkdev(clk, NULL, "d0300000.cam1");
clk = clk_register_gate(NULL, "cam2_clk", "cam2_mclk", 0, clk = clk_register_gate(NULL, "cam2_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM2_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "d0400000.cam2"); clk_register_clkdev(clk, NULL, "d0400000.cam2");
clk = clk_register_gate(NULL, "cam3_clk", "cam3_mclk", 0, clk = clk_register_gate(NULL, "cam3_clk", "ahb_clk", 0,
SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0, SPEAR1340_PERIP3_CLK_ENB, SPEAR1340_CAM3_CLK_ENB, 0,
&_lock); &_lock);
clk_register_clkdev(clk, NULL, "d0500000.cam3"); clk_register_clkdev(clk, NULL, "d0500000.cam3");
......
#
# Makefile for sunxi specific clk
#
obj-y += clk-sunxi.o clk-factors.o
/*
* Copyright (C) 2013 Emilio López <emilio@elopez.com.ar>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* Adjustable factor-based clock implementation
*/
#include <linux/clk-provider.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/io.h>
#include <linux/err.h>
#include <linux/string.h>
#include <linux/delay.h>
#include "clk-factors.h"
/*
* DOC: basic adjustable factor-based clock that cannot gate
*
* Traits of this clock:
* prepare - clk_prepare only ensures that parents are prepared
* enable - clk_enable only ensures that parents are enabled
* rate - rate is adjustable.
* clk->rate = (parent->rate * N * (K + 1) >> P) / (M + 1)
* parent - fixed parent. No clk_set_parent support
*/
struct clk_factors {
struct clk_hw hw;
void __iomem *reg;
struct clk_factors_config *config;
void (*get_factors) (u32 *rate, u32 parent, u8 *n, u8 *k, u8 *m, u8 *p);
spinlock_t *lock;
};
#define to_clk_factors(_hw) container_of(_hw, struct clk_factors, hw)
#define SETMASK(len, pos) (((-1U) >> (31-len)) << (pos))
#define CLRMASK(len, pos) (~(SETMASK(len, pos)))
#define FACTOR_GET(bit, len, reg) (((reg) & SETMASK(len, bit)) >> (bit))
#define FACTOR_SET(bit, len, reg, val) \
(((reg) & CLRMASK(len, bit)) | (val << (bit)))
static unsigned long clk_factors_recalc_rate(struct clk_hw *hw,
unsigned long parent_rate)
{
u8 n = 1, k = 0, p = 0, m = 0;
u32 reg;
unsigned long rate;
struct clk_factors *factors = to_clk_factors(hw);
struct clk_factors_config *config = factors->config;
/* Fetch the register value */
reg = readl(factors->reg);
/* Get each individual factor if applicable */
if (config->nwidth != SUNXI_FACTORS_NOT_APPLICABLE)
n = FACTOR_GET(config->nshift, config->nwidth, reg);
if (config->kwidth != SUNXI_FACTORS_NOT_APPLICABLE)
k = FACTOR_GET(config->kshift, config->kwidth, reg);
if (config->mwidth != SUNXI_FACTORS_NOT_APPLICABLE)
m = FACTOR_GET(config->mshift, config->mwidth, reg);
if (config->pwidth != SUNXI_FACTORS_NOT_APPLICABLE)
p = FACTOR_GET(config->pshift, config->pwidth, reg);
/* Calculate the rate */
rate = (parent_rate * n * (k + 1) >> p) / (m + 1);
return rate;
}
static long clk_factors_round_rate(struct clk_hw *hw, unsigned long rate,
unsigned long *parent_rate)
{
struct clk_factors *factors = to_clk_factors(hw);
factors->get_factors((u32 *)&rate, (u32)*parent_rate,
NULL, NULL, NULL, NULL);
return rate;
}
static int clk_factors_set_rate(struct clk_hw *hw, unsigned long rate,
unsigned long parent_rate)
{
u8 n, k, m, p;
u32 reg;
struct clk_factors *factors = to_clk_factors(hw);
struct clk_factors_config *config = factors->config;
unsigned long flags = 0;
factors->get_factors((u32 *)&rate, (u32)parent_rate, &n, &k, &m, &p);
if (factors->lock)
spin_lock_irqsave(factors->lock, flags);
/* Fetch the register value */
reg = readl(factors->reg);
/* Set up the new factors - macros do not do anything if width is 0 */
reg = FACTOR_SET(config->nshift, config->nwidth, reg, n);
reg = FACTOR_SET(config->kshift, config->kwidth, reg, k);
reg = FACTOR_SET(config->mshift, config->mwidth, reg, m);
reg = FACTOR_SET(config->pshift, config->pwidth, reg, p);
/* Apply them now */
writel(reg, factors->reg);
/* delay 500us so pll stabilizes */
__delay((rate >> 20) * 500 / 2);
if (factors->lock)
spin_unlock_irqrestore(factors->lock, flags);
return 0;
}
static const struct clk_ops clk_factors_ops = {
.recalc_rate = clk_factors_recalc_rate,
.round_rate = clk_factors_round_rate,
.set_rate = clk_factors_set_rate,
};
/**
* clk_register_factors - register a factors clock with
* the clock framework
* @dev: device registering this clock
* @name: name of this clock
* @parent_name: name of clock's parent
* @flags: framework-specific flags
* @reg: register address to adjust factors
* @config: shift and width of factors n, k, m and p
* @get_factors: function to calculate the factors for a given frequency
* @lock: shared register lock for this clock
*/
struct clk *clk_register_factors(struct device *dev, const char *name,
const char *parent_name,
unsigned long flags, void __iomem *reg,
struct clk_factors_config *config,
void (*get_factors)(u32 *rate, u32 parent,
u8 *n, u8 *k, u8 *m, u8 *p),
spinlock_t *lock)
{
struct clk_factors *factors;
struct clk *clk;
struct clk_init_data init;
/* allocate the factors */
factors = kzalloc(sizeof(struct clk_factors), GFP_KERNEL);
if (!factors) {
pr_err("%s: could not allocate factors clk\n", __func__);
return ERR_PTR(-ENOMEM);
}
init.name = name;
init.ops = &clk_factors_ops;
init.flags = flags;
init.parent_names = (parent_name ? &parent_name : NULL);
init.num_parents = (parent_name ? 1 : 0);
/* struct clk_factors assignments */
factors->reg = reg;
factors->config = config;
factors->lock = lock;
factors->hw.init = &init;
factors->get_factors = get_factors;
/* register the clock */
clk = clk_register(dev, &factors->hw);
if (IS_ERR(clk))
kfree(factors);
return clk;
}
#ifndef __MACH_SUNXI_CLK_FACTORS_H
#define __MACH_SUNXI_CLK_FACTORS_H
#include <linux/clk-provider.h>
#include <linux/clkdev.h>
#define SUNXI_FACTORS_NOT_APPLICABLE (0)
struct clk_factors_config {
u8 nshift;
u8 nwidth;
u8 kshift;
u8 kwidth;
u8 mshift;
u8 mwidth;
u8 pshift;
u8 pwidth;
};
struct clk *clk_register_factors(struct device *dev, const char *name,
const char *parent_name,
unsigned long flags, void __iomem *reg,
struct clk_factors_config *config,
void (*get_factors) (u32 *rate, u32 parent_rate,
u8 *n, u8 *k, u8 *m, u8 *p),
spinlock_t *lock);
#endif
This diff is collapsed.
...@@ -355,15 +355,16 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name, ...@@ -355,15 +355,16 @@ struct clk *tegra_clk_register_periph_nodiv(const char *name,
struct tegra_clk_periph *periph, void __iomem *clk_base, struct tegra_clk_periph *periph, void __iomem *clk_base,
u32 offset); u32 offset);
#define TEGRA_CLK_PERIPH(_mux_shift, _mux_width, _mux_flags, \ #define TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, _mux_flags, \
_div_shift, _div_width, _div_frac_width, \ _div_shift, _div_width, _div_frac_width, \
_div_flags, _clk_num, _enb_refcnt, _regs, \ _div_flags, _clk_num, _enb_refcnt, _regs, \
_gate_flags) \ _gate_flags, _table) \
{ \ { \
.mux = { \ .mux = { \
.flags = _mux_flags, \ .flags = _mux_flags, \
.shift = _mux_shift, \ .shift = _mux_shift, \
.width = _mux_width, \ .mask = _mux_mask, \
.table = _table, \
}, \ }, \
.divider = { \ .divider = { \
.flags = _div_flags, \ .flags = _div_flags, \
...@@ -393,26 +394,36 @@ struct tegra_periph_init_data { ...@@ -393,26 +394,36 @@ struct tegra_periph_init_data {
const char *dev_id; const char *dev_id;
}; };
#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset, \ #define TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
_mux_shift, _mux_width, _mux_flags, _div_shift, \ _mux_shift, _mux_mask, _mux_flags, _div_shift, \
_div_width, _div_frac_width, _div_flags, _regs, \ _div_width, _div_frac_width, _div_flags, _regs, \
_clk_num, _enb_refcnt, _gate_flags, _clk_id) \ _clk_num, _enb_refcnt, _gate_flags, _clk_id, _table) \
{ \ { \
.name = _name, \ .name = _name, \
.clk_id = _clk_id, \ .clk_id = _clk_id, \
.parent_names = _parent_names, \ .parent_names = _parent_names, \
.num_parents = ARRAY_SIZE(_parent_names), \ .num_parents = ARRAY_SIZE(_parent_names), \
.periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_width, \ .periph = TEGRA_CLK_PERIPH(_mux_shift, _mux_mask, \
_mux_flags, _div_shift, \ _mux_flags, _div_shift, \
_div_width, _div_frac_width, \ _div_width, _div_frac_width, \
_div_flags, _clk_num, \ _div_flags, _clk_num, \
_enb_refcnt, _regs, \ _enb_refcnt, _regs, \
_gate_flags), \ _gate_flags, _table), \
.offset = _offset, \ .offset = _offset, \
.con_id = _con_id, \ .con_id = _con_id, \
.dev_id = _dev_id, \ .dev_id = _dev_id, \
} }
#define TEGRA_INIT_DATA(_name, _con_id, _dev_id, _parent_names, _offset,\
_mux_shift, _mux_width, _mux_flags, _div_shift, \
_div_width, _div_frac_width, _div_flags, _regs, \
_clk_num, _enb_refcnt, _gate_flags, _clk_id) \
TEGRA_INIT_DATA_TABLE(_name, _con_id, _dev_id, _parent_names, _offset,\
_mux_shift, BIT(_mux_width) - 1, _mux_flags, \
_div_shift, _div_width, _div_frac_width, _div_flags, \
_regs, _clk_num, _enb_refcnt, _gate_flags, _clk_id,\
NULL)
/** /**
* struct clk_super_mux - super clock * struct clk_super_mux - super clock
* *
......
...@@ -5,6 +5,7 @@ ...@@ -5,6 +5,7 @@
# Clock types # Clock types
obj-y += clk-prcc.o obj-y += clk-prcc.o
obj-y += clk-prcmu.o obj-y += clk-prcmu.o
obj-y += clk-sysctrl.o
# Clock definitions # Clock definitions
obj-y += u8500_clk.o obj-y += u8500_clk.o
......
...@@ -12,13 +12,78 @@ ...@@ -12,13 +12,78 @@
#include <linux/device.h> #include <linux/device.h>
#include <linux/platform_device.h> #include <linux/platform_device.h>
#include <linux/mfd/abx500/ab8500.h> #include <linux/mfd/abx500/ab8500.h>
#include <linux/mfd/abx500/ab8500-sysctrl.h>
/* TODO: Add clock implementations here */ #include <linux/clk.h>
#include <linux/clkdev.h>
#include <linux/clk-provider.h>
#include <linux/mfd/dbx500-prcmu.h>
#include "clk.h"
/* Clock definitions for ab8500 */ /* Clock definitions for ab8500 */
static int ab8500_reg_clks(struct device *dev) static int ab8500_reg_clks(struct device *dev)
{ {
int ret;
struct clk *clk;
const char *intclk_parents[] = {"ab8500_sysclk", "ulpclk"};
u16 intclk_reg_sel[] = {0 , AB8500_SYSULPCLKCTRL1};
u8 intclk_reg_mask[] = {0 , AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_MASK};
u8 intclk_reg_bits[] = {
0 ,
(1 << AB8500_SYSULPCLKCTRL1_SYSULPCLKINTSEL_SHIFT)
};
dev_info(dev, "register clocks for ab850x\n");
/* Enable SWAT */
ret = ab8500_sysctrl_set(AB8500_SWATCTRL, AB8500_SWATCTRL_SWATENABLE);
if (ret)
return ret;
/* ab8500_sysclk */
clk = clk_reg_prcmu_gate("ab8500_sysclk", NULL, PRCMU_SYSCLK,
CLK_IS_ROOT);
clk_register_clkdev(clk, "sysclk", "ab8500-usb.0");
clk_register_clkdev(clk, "sysclk", "ab-iddet.0");
clk_register_clkdev(clk, "sysclk", "ab85xx-codec.0");
clk_register_clkdev(clk, "sysclk", "shrm_bus");
/* ab8500_sysclk2 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk2", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF2REQ, 0, 0);
clk_register_clkdev(clk, "sysclk", "0-0070");
/* ab8500_sysclk3 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk3", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF3REQ, 0, 0);
clk_register_clkdev(clk, "sysclk", "cg1960_core.0");
/* ab8500_sysclk4 */
clk = clk_reg_sysctrl_gate(dev , "ab8500_sysclk4", "ab8500_sysclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ,
AB8500_SYSULPCLKCTRL1_SYSCLKBUF4REQ, 0, 0);
/* ab_ulpclk */
clk = clk_reg_sysctrl_gate_fixed_rate(dev, "ulpclk", NULL,
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
AB8500_SYSULPCLKCTRL1_ULPCLKREQ,
38400000, 9000, CLK_IS_ROOT);
clk_register_clkdev(clk, "ulpclk", "ab85xx-codec.0");
/* ab8500_intclk */
clk = clk_reg_sysctrl_set_parent(dev , "intclk", intclk_parents, 2,
intclk_reg_sel, intclk_reg_mask, intclk_reg_bits, 0);
clk_register_clkdev(clk, "intclk", "ab85xx-codec.0");
clk_register_clkdev(clk, NULL, "ab8500-pwm.1");
/* ab8500_audioclk */
clk = clk_reg_sysctrl_gate(dev , "audioclk", "intclk",
AB8500_SYSULPCLKCTRL1, AB8500_SYSULPCLKCTRL1_AUDIOCLKENA,
AB8500_SYSULPCLKCTRL1_AUDIOCLKENA, 0, 0);
clk_register_clkdev(clk, "audioclk", "ab85xx-codec.0");
return 0; return 0;
} }
......
...@@ -20,15 +20,23 @@ ...@@ -20,15 +20,23 @@
struct clk_prcmu { struct clk_prcmu {
struct clk_hw hw; struct clk_hw hw;
u8 cg_sel; u8 cg_sel;
int is_prepared;
int is_enabled; int is_enabled;
int opp_requested;
}; };
/* PRCMU clock operations. */ /* PRCMU clock operations. */
static int clk_prcmu_prepare(struct clk_hw *hw) static int clk_prcmu_prepare(struct clk_hw *hw)
{ {
int ret;
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
return prcmu_request_clock(clk->cg_sel, true);
ret = prcmu_request_clock(clk->cg_sel, true);
if (!ret)
clk->is_prepared = 1;
return ret;;
} }
static void clk_prcmu_unprepare(struct clk_hw *hw) static void clk_prcmu_unprepare(struct clk_hw *hw)
...@@ -36,7 +44,15 @@ static void clk_prcmu_unprepare(struct clk_hw *hw) ...@@ -36,7 +44,15 @@ static void clk_prcmu_unprepare(struct clk_hw *hw)
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
if (prcmu_request_clock(clk->cg_sel, false)) if (prcmu_request_clock(clk->cg_sel, false))
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
hw->init->name); __clk_get_name(hw->clk));
else
clk->is_prepared = 0;
}
static int clk_prcmu_is_prepared(struct clk_hw *hw)
{
struct clk_prcmu *clk = to_clk_prcmu(hw);
return clk->is_prepared;
} }
static int clk_prcmu_enable(struct clk_hw *hw) static int clk_prcmu_enable(struct clk_hw *hw)
...@@ -79,58 +95,52 @@ static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate, ...@@ -79,58 +95,52 @@ static int clk_prcmu_set_rate(struct clk_hw *hw, unsigned long rate,
return prcmu_set_clock_rate(clk->cg_sel, rate); return prcmu_set_clock_rate(clk->cg_sel, rate);
} }
static int request_ape_opp100(bool enable)
{
static int reqs;
int err = 0;
if (enable) {
if (!reqs)
err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
"clock", 100);
if (!err)
reqs++;
} else {
reqs--;
if (!reqs)
prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
"clock");
}
return err;
}
static int clk_prcmu_opp_prepare(struct clk_hw *hw) static int clk_prcmu_opp_prepare(struct clk_hw *hw)
{ {
int err; int err;
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
err = request_ape_opp100(true); if (!clk->opp_requested) {
if (err) { err = prcmu_qos_add_requirement(PRCMU_QOS_APE_OPP,
pr_err("clk_prcmu: %s failed to request APE OPP100 for %s.\n", (char *)__clk_get_name(hw->clk),
__func__, hw->init->name); 100);
return err; if (err) {
pr_err("clk_prcmu: %s fail req APE OPP for %s.\n",
__func__, __clk_get_name(hw->clk));
return err;
}
clk->opp_requested = 1;
} }
err = prcmu_request_clock(clk->cg_sel, true); err = prcmu_request_clock(clk->cg_sel, true);
if (err) if (err) {
request_ape_opp100(false); prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
(char *)__clk_get_name(hw->clk));
clk->opp_requested = 0;
return err;
}
return err; clk->is_prepared = 1;
return 0;
} }
static void clk_prcmu_opp_unprepare(struct clk_hw *hw) static void clk_prcmu_opp_unprepare(struct clk_hw *hw)
{ {
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
if (prcmu_request_clock(clk->cg_sel, false)) if (prcmu_request_clock(clk->cg_sel, false)) {
goto out_error; pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
if (request_ape_opp100(false)) __clk_get_name(hw->clk));
goto out_error; return;
return; }
out_error: if (clk->opp_requested) {
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, prcmu_qos_remove_requirement(PRCMU_QOS_APE_OPP,
hw->init->name); (char *)__clk_get_name(hw->clk));
clk->opp_requested = 0;
}
clk->is_prepared = 0;
} }
static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw) static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
...@@ -138,38 +148,49 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw) ...@@ -138,38 +148,49 @@ static int clk_prcmu_opp_volt_prepare(struct clk_hw *hw)
int err; int err;
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
err = prcmu_request_ape_opp_100_voltage(true); if (!clk->opp_requested) {
if (err) { err = prcmu_request_ape_opp_100_voltage(true);
pr_err("clk_prcmu: %s failed to request APE OPP VOLT for %s.\n", if (err) {
__func__, hw->init->name); pr_err("clk_prcmu: %s fail req APE OPP VOLT for %s.\n",
return err; __func__, __clk_get_name(hw->clk));
return err;
}
clk->opp_requested = 1;
} }
err = prcmu_request_clock(clk->cg_sel, true); err = prcmu_request_clock(clk->cg_sel, true);
if (err) if (err) {
prcmu_request_ape_opp_100_voltage(false); prcmu_request_ape_opp_100_voltage(false);
clk->opp_requested = 0;
return err;
}
return err; clk->is_prepared = 1;
return 0;
} }
static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw) static void clk_prcmu_opp_volt_unprepare(struct clk_hw *hw)
{ {
struct clk_prcmu *clk = to_clk_prcmu(hw); struct clk_prcmu *clk = to_clk_prcmu(hw);
if (prcmu_request_clock(clk->cg_sel, false)) if (prcmu_request_clock(clk->cg_sel, false)) {
goto out_error; pr_err("clk_prcmu: %s failed to disable %s.\n", __func__,
if (prcmu_request_ape_opp_100_voltage(false)) __clk_get_name(hw->clk));
goto out_error; return;
return; }
out_error: if (clk->opp_requested) {
pr_err("clk_prcmu: %s failed to disable %s.\n", __func__, prcmu_request_ape_opp_100_voltage(false);
hw->init->name); clk->opp_requested = 0;
}
clk->is_prepared = 0;
} }
static struct clk_ops clk_prcmu_scalable_ops = { static struct clk_ops clk_prcmu_scalable_ops = {
.prepare = clk_prcmu_prepare, .prepare = clk_prcmu_prepare,
.unprepare = clk_prcmu_unprepare, .unprepare = clk_prcmu_unprepare,
.is_prepared = clk_prcmu_is_prepared,
.enable = clk_prcmu_enable, .enable = clk_prcmu_enable,
.disable = clk_prcmu_disable, .disable = clk_prcmu_disable,
.is_enabled = clk_prcmu_is_enabled, .is_enabled = clk_prcmu_is_enabled,
...@@ -181,6 +202,7 @@ static struct clk_ops clk_prcmu_scalable_ops = { ...@@ -181,6 +202,7 @@ static struct clk_ops clk_prcmu_scalable_ops = {
static struct clk_ops clk_prcmu_gate_ops = { static struct clk_ops clk_prcmu_gate_ops = {
.prepare = clk_prcmu_prepare, .prepare = clk_prcmu_prepare,
.unprepare = clk_prcmu_unprepare, .unprepare = clk_prcmu_unprepare,
.is_prepared = clk_prcmu_is_prepared,
.enable = clk_prcmu_enable, .enable = clk_prcmu_enable,
.disable = clk_prcmu_disable, .disable = clk_prcmu_disable,
.is_enabled = clk_prcmu_is_enabled, .is_enabled = clk_prcmu_is_enabled,
...@@ -202,6 +224,7 @@ static struct clk_ops clk_prcmu_rate_ops = { ...@@ -202,6 +224,7 @@ static struct clk_ops clk_prcmu_rate_ops = {
static struct clk_ops clk_prcmu_opp_gate_ops = { static struct clk_ops clk_prcmu_opp_gate_ops = {
.prepare = clk_prcmu_opp_prepare, .prepare = clk_prcmu_opp_prepare,
.unprepare = clk_prcmu_opp_unprepare, .unprepare = clk_prcmu_opp_unprepare,
.is_prepared = clk_prcmu_is_prepared,
.enable = clk_prcmu_enable, .enable = clk_prcmu_enable,
.disable = clk_prcmu_disable, .disable = clk_prcmu_disable,
.is_enabled = clk_prcmu_is_enabled, .is_enabled = clk_prcmu_is_enabled,
...@@ -211,6 +234,7 @@ static struct clk_ops clk_prcmu_opp_gate_ops = { ...@@ -211,6 +234,7 @@ static struct clk_ops clk_prcmu_opp_gate_ops = {
static struct clk_ops clk_prcmu_opp_volt_scalable_ops = { static struct clk_ops clk_prcmu_opp_volt_scalable_ops = {
.prepare = clk_prcmu_opp_volt_prepare, .prepare = clk_prcmu_opp_volt_prepare,
.unprepare = clk_prcmu_opp_volt_unprepare, .unprepare = clk_prcmu_opp_volt_unprepare,
.is_prepared = clk_prcmu_is_prepared,
.enable = clk_prcmu_enable, .enable = clk_prcmu_enable,
.disable = clk_prcmu_disable, .disable = clk_prcmu_disable,
.is_enabled = clk_prcmu_is_enabled, .is_enabled = clk_prcmu_is_enabled,
...@@ -242,7 +266,9 @@ static struct clk *clk_reg_prcmu(const char *name, ...@@ -242,7 +266,9 @@ static struct clk *clk_reg_prcmu(const char *name,
} }
clk->cg_sel = cg_sel; clk->cg_sel = cg_sel;
clk->is_prepared = 1;
clk->is_enabled = 1; clk->is_enabled = 1;
clk->opp_requested = 0;
/* "rate" can be used for changing the initial frequency */ /* "rate" can be used for changing the initial frequency */
if (rate) if (rate)
prcmu_set_clock_rate(cg_sel, rate); prcmu_set_clock_rate(cg_sel, rate);
......
This diff is collapsed.
...@@ -11,16 +11,18 @@ ...@@ -11,16 +11,18 @@
#define __UX500_CLK_H #define __UX500_CLK_H
#include <linux/clk.h> #include <linux/clk.h>
#include <linux/device.h>
#include <linux/types.h>
struct clk *clk_reg_prcc_pclk(const char *name, struct clk *clk_reg_prcc_pclk(const char *name,
const char *parent_name, const char *parent_name,
unsigned int phy_base, resource_size_t phy_base,
u32 cg_sel, u32 cg_sel,
unsigned long flags); unsigned long flags);
struct clk *clk_reg_prcc_kclk(const char *name, struct clk *clk_reg_prcc_kclk(const char *name,
const char *parent_name, const char *parent_name,
unsigned int phy_base, resource_size_t phy_base,
u32 cg_sel, u32 cg_sel,
unsigned long flags); unsigned long flags);
...@@ -57,4 +59,32 @@ struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name, ...@@ -57,4 +59,32 @@ struct clk *clk_reg_prcmu_opp_volt_scalable(const char *name,
unsigned long rate, unsigned long rate,
unsigned long flags); unsigned long flags);
struct clk *clk_reg_sysctrl_gate(struct device *dev,
const char *name,
const char *parent_name,
u16 reg_sel,
u8 reg_mask,
u8 reg_bits,
unsigned long enable_delay_us,
unsigned long flags);
struct clk *clk_reg_sysctrl_gate_fixed_rate(struct device *dev,
const char *name,
const char *parent_name,
u16 reg_sel,
u8 reg_mask,
u8 reg_bits,
unsigned long rate,
unsigned long enable_delay_us,
unsigned long flags);
struct clk *clk_reg_sysctrl_set_parent(struct device *dev,
const char *name,
const char **parent_names,
u8 num_parents,
u16 *reg_sel,
u8 *reg_mask,
u8 *reg_bits,
unsigned long flags);
#endif /* __UX500_CLK_H */ #endif /* __UX500_CLK_H */
...@@ -3,5 +3,5 @@ obj-$(CONFIG_ICST) += clk-icst.o ...@@ -3,5 +3,5 @@ obj-$(CONFIG_ICST) += clk-icst.o
obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o obj-$(CONFIG_ARCH_INTEGRATOR) += clk-integrator.o
obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o obj-$(CONFIG_INTEGRATOR_IMPD1) += clk-impd1.o
obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o obj-$(CONFIG_ARCH_REALVIEW) += clk-realview.o
obj-$(CONFIG_ARCH_VEXPRESS) += clk-vexpress.o obj-$(CONFIG_ARCH_VEXPRESS) += clk-vexpress.o clk-sp810.o
obj-$(CONFIG_VEXPRESS_CONFIG) += clk-vexpress-osc.o obj-$(CONFIG_VEXPRESS_CONFIG) += clk-vexpress-osc.o
This diff is collapsed.
...@@ -15,8 +15,6 @@ ...@@ -15,8 +15,6 @@
#include <linux/clkdev.h> #include <linux/clkdev.h>
#include <linux/clk-provider.h> #include <linux/clk-provider.h>
#include <linux/err.h> #include <linux/err.h>
#include <linux/of.h>
#include <linux/of_address.h>
#include <linux/vexpress.h> #include <linux/vexpress.h>
static struct clk *vexpress_sp810_timerclken[4]; static struct clk *vexpress_sp810_timerclken[4];
...@@ -86,50 +84,3 @@ void __init vexpress_clk_init(void __iomem *sp810_base) ...@@ -86,50 +84,3 @@ void __init vexpress_clk_init(void __iomem *sp810_base)
WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1], WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
"v2m-timer1", "sp804")); "v2m-timer1", "sp804"));
} }
#if defined(CONFIG_OF)
struct clk *vexpress_sp810_of_get(struct of_phandle_args *clkspec, void *data)
{
if (WARN_ON(clkspec->args_count != 1 || clkspec->args[0] >
ARRAY_SIZE(vexpress_sp810_timerclken)))
return NULL;
return vexpress_sp810_timerclken[clkspec->args[0]];
}
void __init vexpress_clk_of_init(void)
{
struct device_node *node;
struct clk *clk;
struct clk *refclk, *timclk;
of_clk_init(NULL);
node = of_find_compatible_node(NULL, NULL, "arm,sp810");
vexpress_sp810_init(of_iomap(node, 0));
of_clk_add_provider(node, vexpress_sp810_of_get, NULL);
/* Select "better" (faster) parent for SP804 timers */
refclk = of_clk_get_by_name(node, "refclk");
timclk = of_clk_get_by_name(node, "timclk");
if (!WARN_ON(IS_ERR(refclk) || IS_ERR(timclk))) {
int i = 0;
if (clk_get_rate(refclk) > clk_get_rate(timclk))
clk = refclk;
else
clk = timclk;
for (i = 0; i < ARRAY_SIZE(vexpress_sp810_timerclken); i++)
WARN_ON(clk_set_parent(vexpress_sp810_timerclken[i],
clk));
}
WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[0],
"v2m-timer0", "sp804"));
WARN_ON(clk_register_clkdev(vexpress_sp810_timerclken[1],
"v2m-timer1", "sp804"));
}
#endif
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
#include <linux/of_address.h> #include <linux/of_address.h>
#include <linux/of_irq.h> #include <linux/of_irq.h>
#include <linux/sunxi_timer.h> #include <linux/sunxi_timer.h>
#include <linux/clk-provider.h> #include <linux/clk/sunxi.h>
#define TIMER_CTL_REG 0x00 #define TIMER_CTL_REG 0x00
#define TIMER_CTL_ENABLE (1 << 0) #define TIMER_CTL_ENABLE (1 << 0)
...@@ -123,7 +123,7 @@ void __init sunxi_timer_init(void) ...@@ -123,7 +123,7 @@ void __init sunxi_timer_init(void)
if (irq <= 0) if (irq <= 0)
panic("Can't parse IRQ"); panic("Can't parse IRQ");
of_clk_init(NULL); sunxi_init_clocks();
clk = of_clk_get(node, 0); clk = of_clk_get(node, 0);
if (IS_ERR(clk)) if (IS_ERR(clk))
......
...@@ -152,7 +152,7 @@ struct clk { ...@@ -152,7 +152,7 @@ struct clk {
}, \ }, \
.reg = _reg, \ .reg = _reg, \
.shift = _shift, \ .shift = _shift, \
.width = _width, \ .mask = BIT(_width) - 1, \
.flags = _mux_flags, \ .flags = _mux_flags, \
.lock = _lock, \ .lock = _lock, \
}; \ }; \
......
This diff is collapsed.
...@@ -28,16 +28,16 @@ struct clk; ...@@ -28,16 +28,16 @@ struct clk;
* PRE_RATE_CHANGE - called immediately before the clk rate is changed, * PRE_RATE_CHANGE - called immediately before the clk rate is changed,
* to indicate that the rate change will proceed. Drivers must * to indicate that the rate change will proceed. Drivers must
* immediately terminate any operations that will be affected by the * immediately terminate any operations that will be affected by the
* rate change. Callbacks may either return NOTIFY_DONE or * rate change. Callbacks may either return NOTIFY_DONE, NOTIFY_OK,
* NOTIFY_STOP. * NOTIFY_STOP or NOTIFY_BAD.
* *
* ABORT_RATE_CHANGE: called if the rate change failed for some reason * ABORT_RATE_CHANGE: called if the rate change failed for some reason
* after PRE_RATE_CHANGE. In this case, all registered notifiers on * after PRE_RATE_CHANGE. In this case, all registered notifiers on
* the clk will be called with ABORT_RATE_CHANGE. Callbacks must * the clk will be called with ABORT_RATE_CHANGE. Callbacks must
* always return NOTIFY_DONE. * always return NOTIFY_DONE or NOTIFY_OK.
* *
* POST_RATE_CHANGE - called after the clk rate change has successfully * POST_RATE_CHANGE - called after the clk rate change has successfully
* completed. Callbacks must always return NOTIFY_DONE. * completed. Callbacks must always return NOTIFY_DONE or NOTIFY_OK.
* *
*/ */
#define PRE_RATE_CHANGE BIT(0) #define PRE_RATE_CHANGE BIT(0)
......
/*
* Copyright 2012 Maxime Ripard
*
* Maxime Ripard <maxime.ripard@free-electrons.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef __LINUX_CLK_SUNXI_H_
#define __LINUX_CLK_SUNXI_H_
void __init sunxi_init_clocks(void);
#endif
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