Commit 37f43248 authored by Bob Zhou's avatar Bob Zhou Committed by Alex Deucher

drm/amdgpu: fix the overflowed constant warning for RREG32_SOC15()

To fix potential overflowed constant warning reported by Coverity,
modify the variables to uint32_t.
Signed-off-by: default avatarBob Zhou <bob.zhou@amd.com>
Acked-by: default avatarChristian König <christian.koenig@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 18f2525d
...@@ -119,7 +119,8 @@ static int imu_v12_0_load_microcode(struct amdgpu_device *adev) ...@@ -119,7 +119,8 @@ static int imu_v12_0_load_microcode(struct amdgpu_device *adev)
static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
{ {
int i, imu_reg_val = 0; u32 imu_reg_val = 0;
int i;
for (i = 0; i < adev->usec_timeout; i++) { for (i = 0; i < adev->usec_timeout; i++) {
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL); imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_GFX_RESET_CTRL);
...@@ -138,7 +139,7 @@ static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev) ...@@ -138,7 +139,7 @@ static int imu_v12_0_wait_for_reset_status(struct amdgpu_device *adev)
static void imu_v12_0_setup(struct amdgpu_device *adev) static void imu_v12_0_setup(struct amdgpu_device *adev)
{ {
int imu_reg_val; u32 imu_reg_val;
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff); WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL0, 0xffffff);
WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff); WREG32_SOC15(GC, 0, regGFX_IMU_C2PMSG_ACCESS_CTRL1, 0xffff);
...@@ -157,7 +158,7 @@ static void imu_v12_0_setup(struct amdgpu_device *adev) ...@@ -157,7 +158,7 @@ static void imu_v12_0_setup(struct amdgpu_device *adev)
static int imu_v12_0_start(struct amdgpu_device *adev) static int imu_v12_0_start(struct amdgpu_device *adev)
{ {
int imu_reg_val; u32 imu_reg_val;
imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL); imu_reg_val = RREG32_SOC15(GC, 0, regGFX_IMU_CORE_CTRL);
imu_reg_val &= 0xfffffffe; imu_reg_val &= 0xfffffffe;
......
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