Commit 384258f2 authored by Roger Quadros's avatar Roger Quadros

memory: omap-gpmc: Implement IRQ domain for NAND IRQs

GPMC provides 2 interrupts for NAND use. i.e. fifoevent and termcount.
Use IRQ domain for this. NAND device tree node can then
get the necessary interrupts by using gpmc as the interrupt parent.

Legacy boot uses gpmc_get_client_irq to get the
NAND interrupts from the GPMC IRQ domain.
Get rid of custom bitmasks and use IRQ domain for that
as well.
Signed-off-by: default avatarRoger Quadros <rogerq@ti.com>
Acked-by: default avatarRob Herring <robh@kernel.org>
Acked-by: default avatarTony Lindgren <tony@atomide.com>
parent 512d73d1
...@@ -32,6 +32,12 @@ Required properties: ...@@ -32,6 +32,12 @@ Required properties:
bootloader) are used for the physical address decoding. bootloader) are used for the physical address decoding.
As this will change in the future, filling correct As this will change in the future, filling correct
values here is a requirement. values here is a requirement.
- interrupt-controller: The GPMC driver implements and interrupt controller for
the NAND events "fifoevent" and "termcount".
The interrupt number mapping is as follows
0 - NAND_fifoevent
1 - NAND_termcount
- interrupt-cells: Must be set to 2
Timing properties for child nodes. All are optional and default to 0. Timing properties for child nodes. All are optional and default to 0.
...@@ -130,6 +136,8 @@ Example for an AM33xx board: ...@@ -130,6 +136,8 @@ Example for an AM33xx board:
#address-cells = <2>; #address-cells = <2>;
#size-cells = <1>; #size-cells = <1>;
ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */ ranges = <0 0 0x08000000 0x10000000>; /* CS0 @addr 0x8000000, size 0x10000000 */
interrupt-controller;
#interrupt-cells = <2>;
/* child nodes go here */ /* child nodes go here */
}; };
This diff is collapsed.
...@@ -11,8 +11,9 @@ ...@@ -11,8 +11,9 @@
#define GPMC_CONFIG_WP 0x00000005 #define GPMC_CONFIG_WP 0x00000005
#define GPMC_IRQ_FIFOEVENTENABLE 0x01 /* IRQ numbers in GPMC IRQ domain for legacy boot use */
#define GPMC_IRQ_COUNT_EVENT 0x02 #define GPMC_IRQ_FIFOEVENTENABLE 0
#define GPMC_IRQ_COUNT_EVENT 1
/** /**
* gpmc_nand_ops - Interface between NAND and GPMC * gpmc_nand_ops - Interface between NAND and GPMC
......
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