arm64/sysreg: Align pointer auth enumeration defines with architecture

The defines used for the pointer authentication feature enumerations do not
follow the naming convention we've decided to use where we name things
after the architecture feature that introduced. Prepare for generating the
defines for the ISA ID registers by updating to use the feature names.
No functional changes.
Signed-off-by: Mark Brown <broonie@kernel.org>
Link: https://lore.kernel.org/r/20220704170302.2609529-10-broonie@kernel.orgSigned-off-by: Will Deacon <will@kernel.org>

arch/arm64/include/asm/sysreg.h

@@ -721,21 +721,21 @@
 #define ID_AA64ISAR1_DPB_SHIFT		0
 
 #define ID_AA64ISAR1_APA_NI			0x0
-#define ID_AA64ISAR1_APA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_APA_PAuth			0x1
 #define ID_AA64ISAR1_APA_ARCH_EPAC		0x2
-#define ID_AA64ISAR1_APA_ARCH_EPAC2		0x3
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_APA_ARCH_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_APA_Pauth2			0x3
+#define ID_AA64ISAR1_APA_FPAC			0x4
+#define ID_AA64ISAR1_APA_FPACCOMBINE		0x5
 #define ID_AA64ISAR1_API_NI			0x0
-#define ID_AA64ISAR1_API_IMP_DEF		0x1
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC		0x2
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2		0x3
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC	0x4
-#define ID_AA64ISAR1_API_IMP_DEF_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR1_API_PAuth			0x1
+#define ID_AA64ISAR1_API_EPAC			0x2
+#define ID_AA64ISAR1_API_PAuth2			0x3
+#define ID_AA64ISAR1_API_FPAC			0x4
+#define ID_AA64ISAR1_API_FPACCOMBINE		0x5
 #define ID_AA64ISAR1_GPA_NI			0x0
-#define ID_AA64ISAR1_GPA_ARCHITECTED		0x1
+#define ID_AA64ISAR1_GPA_IMP			0x1
 #define ID_AA64ISAR1_GPI_NI			0x0
-#define ID_AA64ISAR1_GPI_IMP_DEF		0x1
+#define ID_AA64ISAR1_GPI_IMP			0x1
 
 /* id_aa64isar2 */
 #define ID_AA64ISAR2_CLEARBHB_SHIFT	28
@@ -755,14 +755,14 @@
 #define ID_AA64ISAR2_WFXT_SUPPORTED	0x2
 
 #define ID_AA64ISAR2_APA3_NI			0x0
-#define ID_AA64ISAR2_APA3_ARCHITECTED		0x1
-#define ID_AA64ISAR2_APA3_ARCH_EPAC		0x2
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2		0x3
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC	0x4
-#define ID_AA64ISAR2_APA3_ARCH_EPAC2_FPAC_CMB	0x5
+#define ID_AA64ISAR2_APA3_PAuth			0x1
+#define ID_AA64ISAR2_APA3_EPAC			0x2
+#define ID_AA64ISAR2_APA3_PAuth2		0x3
+#define ID_AA64ISAR2_APA3_FPAC			0x4
+#define ID_AA64ISAR2_APA3_FPACCOMBINE		0x5
 
 #define ID_AA64ISAR2_GPA3_NI			0x0
-#define ID_AA64ISAR2_GPA3_ARCHITECTED		0x1
+#define ID_AA64ISAR2_GPA3_IMP			0x1
 
 /* id_aa64pfr0 */
 #define ID_AA64PFR0_CSV3_SHIFT		60

arch/arm64/kernel/cpufeature.c

@@ -2317,7 +2317,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_APA_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_APA_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR1_APA_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2328,7 +2328,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR2_APA3_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR2_APA3_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR2_APA3_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2339,7 +2339,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_API_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_API_IMP_DEF,
+		.min_field_value = ID_AA64ISAR1_API_PAuth,
 		.matches = has_address_auth_cpucap,
 	},
 	{
@@ -2355,7 +2355,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_GPA_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_GPA_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR1_GPA_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2366,7 +2366,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR2_GPA3_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR2_GPA3_ARCHITECTED,
+		.min_field_value = ID_AA64ISAR2_GPA3_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2377,7 +2377,7 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
 		.sign = FTR_UNSIGNED,
 		.field_pos = ID_AA64ISAR1_GPI_SHIFT,
 		.field_width = 4,
-		.min_field_value = ID_AA64ISAR1_GPI_IMP_DEF,
+		.min_field_value = ID_AA64ISAR1_GPI_IMP,
 		.matches = has_cpuid_feature,
 	},
 	{
@@ -2562,15 +2562,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_APA_SHIFT,
 				  4, FTR_UNSIGNED,
-				  ID_AA64ISAR1_APA_ARCHITECTED)
+				  ID_AA64ISAR1_APA_PAuth)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_APA3_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR2_APA3_PAuth)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_API_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_API_IMP_DEF)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_API_PAuth)
 	},
 	{},
 };
@@ -2578,15 +2578,15 @@ static const struct arm64_cpu_capabilities ptr_auth_hwcap_addr_matches[] = {
 static const struct arm64_cpu_capabilities ptr_auth_hwcap_gen_matches[] = {
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPA_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPA_IMP)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR2_EL1, ID_AA64ISAR2_GPA3_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_ARCHITECTED)
+				  4, FTR_UNSIGNED, ID_AA64ISAR2_GPA3_IMP)
 	},
 	{
 		HWCAP_CPUID_MATCH(SYS_ID_AA64ISAR1_EL1, ID_AA64ISAR1_GPI_SHIFT,
-				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP_DEF)
+				  4, FTR_UNSIGNED, ID_AA64ISAR1_GPI_IMP)
 	},
 	{},
 };