Commit 38e48b71 authored by Christophe Leroy's avatar Christophe Leroy Committed by Wim Van Sebroeck

watchdog: mpc8xxx: provide boot status

mpc8xxx watchdog driver supports the following platforms:
- mpc8xx
- mpc83xx
- mpc86xx

Those three platforms have a 32 bits register which provides the
reason of the last boot, including whether it was caused by the
watchdog.

mpc8xx: Register RSR, bit SWRS (bit 3)
mpc83xx: Register RSR, bit SWRS (bit 28)
mpc86xx: Register RSTRSCR, bit WDT_RR (bit 11)

This patch maps the register as defined in the device tree and updates
wdt.bootstatus based on the value of the watchdog related bit. Then
the information can be retrieved via the WDIOC_GETBOOTSTATUS ioctl.

Hereunder is an example of devicetree for mpc8xx,
the Reset Status Register being at offset 0x288:

		WDT: watchdog@0 {
			compatible = "fsl,mpc823-wdt";
			reg = <0x0 0x10 0x288 0x4>;
		};

On the mpc83xx, RSR is at offset 0x910
On the mpc86xx, RSTRSCR is at offset 0xe0094
Suggested-by: default avatarRadu Rendec <radu.rendec@gmail.com>
Tested-by: Christophe Leroy <christophe.leroy@c-s.fr> # On mpc885
Signed-off-by: default avatarChristophe Leroy <christophe.leroy@c-s.fr>
Reviewed-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarGuenter Roeck <linux@roeck-us.net>
Signed-off-by: default avatarWim Van Sebroeck <wim@linux-watchdog.org>
parent 59c66636
...@@ -47,6 +47,7 @@ struct mpc8xxx_wdt { ...@@ -47,6 +47,7 @@ struct mpc8xxx_wdt {
struct mpc8xxx_wdt_type { struct mpc8xxx_wdt_type {
int prescaler; int prescaler;
bool hw_enabled; bool hw_enabled;
u32 rsr_mask;
}; };
struct mpc8xxx_wdt_ddata { struct mpc8xxx_wdt_ddata {
...@@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev) ...@@ -159,6 +160,24 @@ static int mpc8xxx_wdt_probe(struct platform_device *ofdev)
return -ENODEV; return -ENODEV;
} }
res = platform_get_resource(ofdev, IORESOURCE_MEM, 1);
if (res) {
bool status;
u32 __iomem *rsr = ioremap(res->start, resource_size(res));
if (!rsr)
return -ENOMEM;
status = in_be32(rsr) & wdt_type->rsr_mask;
ddata->wdd.bootstatus = status ? WDIOF_CARDRESET : 0;
/* clear reset status bits related to watchdog timer */
out_be32(rsr, wdt_type->rsr_mask);
iounmap(rsr);
dev_info(dev, "Last boot was %scaused by watchdog\n",
status ? "" : "not ");
}
spin_lock_init(&ddata->lock); spin_lock_init(&ddata->lock);
ddata->wdd.info = &mpc8xxx_wdt_info, ddata->wdd.info = &mpc8xxx_wdt_info,
...@@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { ...@@ -216,6 +235,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = {
.compatible = "mpc83xx_wdt", .compatible = "mpc83xx_wdt",
.data = &(struct mpc8xxx_wdt_type) { .data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x10000, .prescaler = 0x10000,
.rsr_mask = BIT(3), /* RSR Bit SWRS */
}, },
}, },
{ {
...@@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { ...@@ -223,6 +243,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = {
.data = &(struct mpc8xxx_wdt_type) { .data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x10000, .prescaler = 0x10000,
.hw_enabled = true, .hw_enabled = true,
.rsr_mask = BIT(20), /* RSTRSCR Bit WDT_RR */
}, },
}, },
{ {
...@@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = { ...@@ -230,6 +251,7 @@ static const struct of_device_id mpc8xxx_wdt_match[] = {
.data = &(struct mpc8xxx_wdt_type) { .data = &(struct mpc8xxx_wdt_type) {
.prescaler = 0x800, .prescaler = 0x800,
.hw_enabled = true, .hw_enabled = true,
.rsr_mask = BIT(28), /* RSR Bit SWRS */
}, },
}, },
{}, {},
......
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