Commit 38ed7b09 authored by Nirmoy Das's avatar Nirmoy Das Committed by Alex Deucher

drm/powerplay: label internally used symbols as static

Used sparse(make C=1) to find these loose ends.
Signed-off-by: default avatarNirmoy Das <nirmoy.das@amd.com>
Reviewed-by: default avatarAlex Deucher <alexander.deucher@amd.com>
Signed-off-by: default avatarAlex Deucher <alexander.deucher@amd.com>
parent 204d8998
......@@ -1695,7 +1695,7 @@ static int smu_enable_umd_pstate(void *handle,
return 0;
}
int smu_adjust_power_state_dynamic(struct smu_context *smu,
static int smu_adjust_power_state_dynamic(struct smu_context *smu,
enum amd_dpm_forced_level level,
bool skip_display_settings)
{
......
......@@ -1487,7 +1487,7 @@ static int smu7_update_avfs(struct pp_hwmgr *hwmgr)
return 0;
}
int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
static int smu7_disable_dpm_tasks(struct pp_hwmgr *hwmgr)
{
int tmp_result, result = 0;
......
......@@ -1879,7 +1879,7 @@ static int smu8_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
return 0;
}
int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
static int smu8_dpm_update_uvd_dpm(struct pp_hwmgr *hwmgr, bool bgate)
{
struct smu8_hwmgr *data = hwmgr->backend;
struct phm_uvd_clock_voltage_dependency_table *ptable =
......
......@@ -90,7 +90,7 @@ typedef enum {
static const ULONG PhwVega10_Magic = (ULONG)(PHM_VIslands_Magic);
struct vega10_power_state *cast_phw_vega10_power_state(
static struct vega10_power_state *cast_phw_vega10_power_state(
struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
......@@ -100,7 +100,7 @@ struct vega10_power_state *cast_phw_vega10_power_state(
return (struct vega10_power_state *)hw_ps;
}
const struct vega10_power_state *cast_const_phw_vega10_power_state(
static const struct vega10_power_state *cast_const_phw_vega10_power_state(
const struct pp_hw_power_state *hw_ps)
{
PP_ASSERT_WITH_CODE((PhwVega10_Magic == hw_ps->magic),
......@@ -3905,7 +3905,7 @@ static void vega10_notify_smc_display_change(struct pp_hwmgr *hwmgr,
NULL);
}
int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
static int vega10_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req)
{
int result = 0;
......@@ -4672,7 +4672,7 @@ static int vega10_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
return result;
}
int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int vega10_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega10_hwmgr *data = hwmgr->backend;
......
......@@ -499,7 +499,7 @@ int vega10_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
static int vega10_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{
int ret;
struct vega10_hwmgr *data = hwmgr->backend;
......@@ -602,7 +602,7 @@ int vega10_enable_mgpu_fan_boost(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
static int vega10_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
/* If the fantable setup has failed we could have disabled
* PHM_PlatformCaps_MicrocodeFanControl even after
......
......@@ -1436,7 +1436,7 @@ static int vega12_notify_smc_display_change(struct pp_hwmgr *hwmgr,
return 0;
}
int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
static int vega12_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req)
{
int result = 0;
......@@ -2404,7 +2404,7 @@ static int vega12_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
return result;
}
int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int vega12_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega12_hwmgr *data =
(struct vega12_hwmgr *)(hwmgr->backend);
......
......@@ -263,7 +263,7 @@ static int init_powerplay_table_information(
return result;
}
int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
static int vega12_pp_tables_initialize(struct pp_hwmgr *hwmgr)
{
int result = 0;
const ATOM_Vega12_POWERPLAYTABLE *powerplay_table;
......
......@@ -251,7 +251,7 @@ int vega12_thermal_stop_thermal_controller(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
static int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
{
int ret;
struct vega12_hwmgr *data = (struct vega12_hwmgr *)(hwmgr->backend);
......@@ -274,7 +274,7 @@ int vega12_thermal_setup_fan_table(struct pp_hwmgr *hwmgr)
* @param Result the last failure code
* @return result from set temperature range routine
*/
int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
static int vega12_thermal_start_smc_fan_control(struct pp_hwmgr *hwmgr)
{
/* If the fantable setup has failed we could have disabled
* PHM_PlatformCaps_MicrocodeFanControl even after
......
......@@ -1981,7 +1981,7 @@ static int vega20_upload_dpm_max_level(struct pp_hwmgr *hwmgr, uint32_t feature_
return ret;
}
int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int vega20_enable_disable_vce_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
......@@ -2253,7 +2253,7 @@ static int vega20_read_sensor(struct pp_hwmgr *hwmgr, int idx,
return ret;
}
int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
static int vega20_display_clock_voltage_request(struct pp_hwmgr *hwmgr,
struct pp_display_clock_request *clock_req)
{
int result = 0;
......@@ -3589,7 +3589,7 @@ static int vega20_display_configuration_changed_task(struct pp_hwmgr *hwmgr)
return result;
}
int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
static int vega20_enable_disable_uvd_dpm(struct pp_hwmgr *hwmgr, bool enable)
{
struct vega20_hwmgr *data =
(struct vega20_hwmgr *)(hwmgr->backend);
......
......@@ -1805,7 +1805,7 @@ static int sienna_cichlid_update_pcie_parameters(struct smu_context *smu,
return 0;
}
int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
static int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t *min, uint32_t *max)
{
......@@ -1821,7 +1821,7 @@ int sienna_cichlid_get_dpm_ultimate_freq(struct smu_context *smu,
return ret;
}
int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
static int sienna_cichlid_set_soft_freq_limited_range(struct smu_context *smu,
enum smu_clk_type clk_type,
uint32_t min, uint32_t max)
{
......
......@@ -183,7 +183,7 @@ static int ci_program_jump_on_start(struct pp_hwmgr *hwmgr)
return 0;
}
bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
static bool ci_is_smc_ram_running(struct pp_hwmgr *hwmgr)
{
return ((0 == PHM_READ_VFPF_INDIRECT_FIELD(hwmgr->device,
CGS_IND_REG__SMC, SMC_SYSCON_CLOCK_CNTL_0, ck_disable))
......
......@@ -1083,7 +1083,7 @@ static int tonga_populate_single_memory_level(
return result;
}
int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
static int tonga_populate_all_memory_levels(struct pp_hwmgr *hwmgr)
{
struct smu7_hwmgr *data = (struct smu7_hwmgr *)(hwmgr->backend);
struct tonga_smumgr *smu_data =
......
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