Commit 3a3173b9 authored by Sasha Neftin's avatar Sasha Neftin Committed by Jeff Kirsher

e1000e: Initial Support for CannonLake

i219 (6) and i219 (7) are the next LOM generations that will be
available on the nextIntel Client platform (CannonLake)
This patch provides the initial support for these devices
Signed-off-by: default avatarSasha Neftin <sasha.neftin@intel.com>
Reviewed-by: default avatarRaanan Avargil <raanan.avargil@intel.com>
Reviewed-by: default avatarDima Ruinskiy <dima.ruinskiy@intel.com>
Tested-by: default avatarAaron Brown <aaron.f.brown@intel.com>
Signed-off-by: default avatarJeff Kirsher <jeffrey.t.kirsher@intel.com>
parent 10ed1e0b
...@@ -135,7 +135,8 @@ enum e1000_boards { ...@@ -135,7 +135,8 @@ enum e1000_boards {
board_pchlan, board_pchlan,
board_pch2lan, board_pch2lan,
board_pch_lpt, board_pch_lpt,
board_pch_spt board_pch_spt,
board_pch_cnp
}; };
struct e1000_ps_page { struct e1000_ps_page {
...@@ -515,6 +516,7 @@ extern const struct e1000_info e1000_pch_info; ...@@ -515,6 +516,7 @@ extern const struct e1000_info e1000_pch_info;
extern const struct e1000_info e1000_pch2_info; extern const struct e1000_info e1000_pch2_info;
extern const struct e1000_info e1000_pch_lpt_info; extern const struct e1000_info e1000_pch_lpt_info;
extern const struct e1000_info e1000_pch_spt_info; extern const struct e1000_info e1000_pch_spt_info;
extern const struct e1000_info e1000_pch_cnp_info;
extern const struct e1000_info e1000_es2_info; extern const struct e1000_info e1000_es2_info;
void e1000e_ptp_init(struct e1000_adapter *adapter); void e1000e_ptp_init(struct e1000_adapter *adapter);
......
...@@ -96,6 +96,10 @@ struct e1000_hw; ...@@ -96,6 +96,10 @@ struct e1000_hw;
#define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8 #define E1000_DEV_ID_PCH_SPT_I219_V4 0x15D8
#define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3 #define E1000_DEV_ID_PCH_SPT_I219_LM5 0x15E3
#define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6 #define E1000_DEV_ID_PCH_SPT_I219_V5 0x15D6
#define E1000_DEV_ID_PCH_CNP_I219_LM6 0x15BD
#define E1000_DEV_ID_PCH_CNP_I219_V6 0x15BE
#define E1000_DEV_ID_PCH_CNP_I219_LM7 0x15BB
#define E1000_DEV_ID_PCH_CNP_I219_V7 0x15BC
#define E1000_REVISION_4 4 #define E1000_REVISION_4 4
...@@ -118,6 +122,7 @@ enum e1000_mac_type { ...@@ -118,6 +122,7 @@ enum e1000_mac_type {
e1000_pch2lan, e1000_pch2lan,
e1000_pch_lpt, e1000_pch_lpt,
e1000_pch_spt, e1000_pch_spt,
e1000_pch_cnp,
}; };
enum e1000_media_type { enum e1000_media_type {
......
...@@ -5915,3 +5915,23 @@ const struct e1000_info e1000_pch_spt_info = { ...@@ -5915,3 +5915,23 @@ const struct e1000_info e1000_pch_spt_info = {
.phy_ops = &ich8_phy_ops, .phy_ops = &ich8_phy_ops,
.nvm_ops = &spt_nvm_ops, .nvm_ops = &spt_nvm_ops,
}; };
const struct e1000_info e1000_pch_cnp_info = {
.mac = e1000_pch_cnp,
.flags = FLAG_IS_ICH
| FLAG_HAS_WOL
| FLAG_HAS_HW_TIMESTAMP
| FLAG_HAS_CTRLEXT_ON_LOAD
| FLAG_HAS_AMT
| FLAG_HAS_FLASH
| FLAG_HAS_JUMBO_FRAMES
| FLAG_APME_IN_WUC,
.flags2 = FLAG2_HAS_PHY_STATS
| FLAG2_HAS_EEE,
.pba = 26,
.max_hw_frame_size = 9022,
.get_variants = e1000_get_variants_ich8lan,
.mac_ops = &ich8_mac_ops,
.phy_ops = &ich8_phy_ops,
.nvm_ops = &spt_nvm_ops,
};
...@@ -71,6 +71,7 @@ static const struct e1000_info *e1000_info_tbl[] = { ...@@ -71,6 +71,7 @@ static const struct e1000_info *e1000_info_tbl[] = {
[board_pch2lan] = &e1000_pch2_info, [board_pch2lan] = &e1000_pch2_info,
[board_pch_lpt] = &e1000_pch_lpt_info, [board_pch_lpt] = &e1000_pch_lpt_info,
[board_pch_spt] = &e1000_pch_spt_info, [board_pch_spt] = &e1000_pch_spt_info,
[board_pch_cnp] = &e1000_pch_cnp_info,
}; };
struct e1000_reg_info { struct e1000_reg_info {
...@@ -7514,6 +7515,10 @@ static const struct pci_device_id e1000_pci_tbl[] = { ...@@ -7514,6 +7515,10 @@ static const struct pci_device_id e1000_pci_tbl[] = {
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V4), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_LM5), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt }, { PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_SPT_I219_V5), board_pch_spt },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM6), board_pch_cnp },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V6), board_pch_cnp },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_LM7), board_pch_cnp },
{ PCI_VDEVICE(INTEL, E1000_DEV_ID_PCH_CNP_I219_V7), board_pch_cnp },
{ 0, 0, 0, 0, 0, 0, 0 } /* terminate list */ { 0, 0, 0, 0, 0, 0, 0 } /* terminate list */
}; };
......
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